Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	680392	1			T12	559		T26	7		T7	47944
auto[1]	10547337	1			T1	5083		T2	3155		T5	57950
auto[2]	550521	1			T12	337		T26	2		T7	42517
auto[3]	10423232	1			T1	5166		T2	3076		T5	58035

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14327946	1			T1	8519		T2	4432		T5	96249
auto[1]	2141214	1			T1	833		T2	859		T5	9255
auto[2]	2128978	1			T1	801		T2	806		T5	9530
auto[3]	3603344	1			T1	96		T2	134		T5	951

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7977720

1

T1

10235

T2

6228

T5

115844

auto[1]

14223762

1

T1

14

T2

3

T5

141

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	250526	1			T12	458		T7	39508		T28	32
auto[0]	auto[0]	auto[1]	25830	1			T12	41		T26	3		T7	4014
auto[0]	auto[0]	auto[2]	25752	1			T12	54		T26	1		T7	3973
auto[0]	auto[0]	auto[3]	6396	1			T12	5		T26	3		T7	402
auto[0]	auto[1]	auto[0]	3033274	1			T1	4204		T2	2243		T5	47882
auto[0]	auto[1]	auto[1]	321934	1			T1	406		T2	629		T5	4618
auto[0]	auto[1]	auto[2]	306672	1			T1	419		T2	215		T5	4908
auto[0]	auto[1]	auto[3]	68648	1			T1	46		T2	68		T5	473
auto[0]	auto[2]	auto[0]	207008	1			T12	259		T7	35938		T28	21
auto[0]	auto[2]	auto[1]	21347	1			T12	22		T26	1		T7	3532
auto[0]	auto[2]	auto[2]	21477	1			T12	49		T7	2736		T28	3
auto[0]	auto[2]	auto[3]	5029	1			T12	7		T26	1		T7	270
auto[0]	auto[3]	auto[0]	2993106	1			T1	4303		T2	2186		T5	48245
auto[0]	auto[3]	auto[1]	303293	1			T1	425		T2	230		T5	4627
auto[0]	auto[3]	auto[2]	317949	1			T1	382		T2	591		T5	4614
auto[0]	auto[3]	auto[3]	69479	1			T1	50		T2	66		T5	477
auto[1]	auto[0]	auto[0]	12476	1			T7	38		T98	898		T146	3
auto[1]	auto[0]	auto[1]	55051	1			T12	1		T7	6		T98	4133
auto[1]	auto[0]	auto[2]	55277	1			T7	3		T98	4192		T144	6488
auto[1]	auto[0]	auto[3]	249084	1			T147	2		T98	18641		T144	29259
auto[1]	auto[1]	auto[0]	3910492	1			T1	7		T5	60		T4	67
auto[1]	auto[1]	auto[1]	696602	1			T1	1		T5	4		T4	863
auto[1]	auto[1]	auto[2]	675163	1			T5	4		T4	322		T11	3
auto[1]	auto[1]	auto[3]	1534552	1			T5	1		T4	3982		T10	2
auto[1]	auto[2]	auto[0]	11038	1			T7	31		T28	1		T98	791
auto[1]	auto[2]	auto[1]	48777	1			T7	3		T147	1		T98	3829
auto[1]	auto[2]	auto[2]	42838	1			T7	7		T98	2905		T144	4327
auto[1]	auto[2]	auto[3]	193007	1			T147	1		T98	12684		T144	19702
auto[1]	auto[3]	auto[0]	3910026	1			T1	5		T2	3		T5	62
auto[1]	auto[3]	auto[1]	668380	1			T1	1		T5	6		T4	281
auto[1]	auto[3]	auto[2]	683850	1			T5	4		T4	891		T11	3
auto[1]	auto[3]	auto[3]	1477149	1			T4	3971		T11	1		T43	549