Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13631484	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

54415658

1

T1

46533

T2

150392

T3

3001

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	33922703	1			T1	126916		T2	82501		T3	1641
values[0x0]	15700796	1			T1	42844		T2	40058		T3	783
values[0x1]	18423643	1			T1	84379		T2	42882		T3	901

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6791562	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

61255580

1

T1

150849

T2

157937

T3

3170

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	270288	1			T1	991		T2	610		T4	829
valid_sources[0x01]	261436	1			T1	1094		T2	609		T4	626
valid_sources[0x02]	261984	1			T1	1337		T2	652		T4	607
valid_sources[0x03]	319099	1			T1	1050		T2	654		T4	578
valid_sources[0x04]	272745	1			T1	898		T2	694		T4	692
valid_sources[0x05]	309997	1			T1	850		T2	746		T4	787
valid_sources[0x06]	252988	1			T1	863		T2	604		T4	623
valid_sources[0x07]	258624	1			T1	1089		T2	690		T4	650
valid_sources[0x08]	267342	1			T1	1128		T2	625		T4	870
valid_sources[0x09]	377110	1			T1	940		T2	630		T4	642
valid_sources[0x0a]	255662	1			T1	1228		T2	635		T4	677
valid_sources[0x0b]	334152	1			T1	995		T2	549		T4	625
valid_sources[0x0c]	245878	1			T1	972		T2	647		T4	658
valid_sources[0x0d]	239782	1			T1	1194		T2	601		T4	888
valid_sources[0x0e]	262468	1			T1	972		T2	627		T4	647
valid_sources[0x0f]	255109	1			T1	1013		T2	613		T4	529
valid_sources[0x10]	238760	1			T1	743		T2	607		T4	591
valid_sources[0x11]	272622	1			T1	994		T2	672		T4	620
valid_sources[0x12]	367148	1			T1	918		T2	616		T4	909
valid_sources[0x13]	241230	1			T1	822		T2	667		T4	711
valid_sources[0x14]	253651	1			T1	987		T2	593		T4	616
valid_sources[0x15]	264183	1			T1	1170		T2	620		T4	865
valid_sources[0x16]	270686	1			T1	951		T2	645		T4	645
valid_sources[0x17]	301281	1			T1	931		T2	597		T4	725
valid_sources[0x18]	259610	1			T1	1086		T2	686		T4	554
valid_sources[0x19]	380459	1			T1	1000		T2	694		T4	560
valid_sources[0x1a]	279316	1			T1	907		T2	622		T4	635
valid_sources[0x1b]	248871	1			T1	1074		T2	552		T4	805
valid_sources[0x1c]	271134	1			T1	875		T2	720		T4	837
valid_sources[0x1d]	270263	1			T1	949		T2	709		T4	480
valid_sources[0x1e]	273669	1			T1	1153		T2	619		T4	666
valid_sources[0x1f]	277452	1			T1	1058		T2	688		T4	529
valid_sources[0x20]	247017	1			T1	943		T2	631		T4	769
valid_sources[0x21]	259133	1			T1	1031		T2	729		T4	795
valid_sources[0x22]	227588	1			T1	1118		T2	624		T4	670
valid_sources[0x23]	277243	1			T1	926		T2	594		T4	843
valid_sources[0x24]	261587	1			T1	817		T2	739		T4	788
valid_sources[0x25]	258662	1			T1	977		T2	641		T4	715
valid_sources[0x26]	257169	1			T1	1029		T2	643		T4	856
valid_sources[0x27]	252819	1			T1	865		T2	604		T4	414
valid_sources[0x28]	253495	1			T1	976		T2	582		T4	609
valid_sources[0x29]	256385	1			T1	1006		T2	634		T4	845
valid_sources[0x2a]	279077	1			T1	1022		T2	659		T4	550
valid_sources[0x2b]	296031	1			T1	970		T2	677		T4	589
valid_sources[0x2c]	231502	1			T1	936		T2	630		T4	1308
valid_sources[0x2d]	297208	1			T1	1201		T2	626		T4	558
valid_sources[0x2e]	228755	1			T1	966		T2	611		T4	518
valid_sources[0x2f]	286252	1			T1	1127		T2	680		T4	715
valid_sources[0x30]	330925	1			T1	1045		T2	598		T4	672
valid_sources[0x31]	232109	1			T1	920		T2	687		T4	727
valid_sources[0x32]	290201	1			T1	827		T2	658		T4	876
valid_sources[0x33]	252003	1			T1	946		T2	627		T4	843
valid_sources[0x34]	284813	1			T1	1069		T2	596		T4	685
valid_sources[0x35]	237501	1			T1	995		T2	718		T4	792
valid_sources[0x36]	243117	1			T1	1057		T2	640		T4	438
valid_sources[0x37]	251502	1			T1	1076		T2	604		T4	828
valid_sources[0x38]	276609	1			T1	1194		T2	641		T4	471
valid_sources[0x39]	229283	1			T1	1002		T2	634		T4	971
valid_sources[0x3a]	316575	1			T1	1087		T2	617		T4	664
valid_sources[0x3b]	273307	1			T1	926		T2	724		T4	596
valid_sources[0x3c]	234198	1			T1	835		T2	712		T4	583
valid_sources[0x3d]	314517	1			T1	1024		T2	685		T4	623
valid_sources[0x3e]	236694	1			T1	1015		T2	646		T4	623
valid_sources[0x3f]	232920	1			T1	1159		T2	743		T4	621
valid_sources[0x40]	291510	1			T1	988		T2	637		T4	574
valid_sources[0x41]	238686	1			T1	991		T2	677		T4	790
valid_sources[0x42]	334317	1			T1	1038		T2	635		T4	694
valid_sources[0x43]	242730	1			T1	1058		T2	742		T4	496
valid_sources[0x44]	267635	1			T1	978		T2	664		T4	734
valid_sources[0x45]	274053	1			T1	966		T2	633		T4	746
valid_sources[0x46]	248940	1			T1	1159		T2	693		T4	721
valid_sources[0x47]	267893	1			T1	983		T2	659		T4	1212
valid_sources[0x48]	283904	1			T1	1035		T2	589		T4	847
valid_sources[0x49]	305835	1			T1	1086		T2	683		T4	872
valid_sources[0x4a]	353849	1			T1	1083		T2	661		T4	640
valid_sources[0x4b]	266479	1			T1	986		T2	632		T4	676
valid_sources[0x4c]	246255	1			T1	1023		T2	644		T4	709
valid_sources[0x4d]	268852	1			T1	1085		T2	683		T4	844
valid_sources[0x4e]	259842	1			T1	799		T2	669		T4	519
valid_sources[0x4f]	267258	1			T1	991		T2	657		T4	524
valid_sources[0x50]	225924	1			T1	1100		T2	615		T4	563
valid_sources[0x51]	276890	1			T1	840		T2	584		T4	607
valid_sources[0x52]	251750	1			T1	1024		T2	638		T4	922
valid_sources[0x53]	298513	1			T1	1159		T2	641		T4	566
valid_sources[0x54]	270472	1			T1	1097		T2	620		T4	1144
valid_sources[0x55]	298743	1			T1	964		T2	709		T4	533
valid_sources[0x56]	273011	1			T1	846		T2	643		T4	754
valid_sources[0x57]	248784	1			T1	1066		T2	666		T4	762
valid_sources[0x58]	257425	1			T1	1011		T2	691		T4	645
valid_sources[0x59]	289695	1			T1	822		T2	662		T4	693
valid_sources[0x5a]	239234	1			T1	1090		T2	633		T4	886
valid_sources[0x5b]	245372	1			T1	934		T2	555		T4	1075
valid_sources[0x5c]	247765	1			T1	871		T2	596		T4	536
valid_sources[0x5d]	270662	1			T1	922		T2	706		T4	820
valid_sources[0x5e]	241071	1			T1	1132		T2	616		T4	830
valid_sources[0x5f]	286327	1			T1	945		T2	679		T4	1190
valid_sources[0x60]	242387	1			T1	1035		T2	689		T4	411
valid_sources[0x61]	300014	1			T1	1081		T2	675		T4	836
valid_sources[0x62]	334415	1			T1	904		T2	613		T4	761
valid_sources[0x63]	246776	1			T1	962		T2	660		T4	1086
valid_sources[0x64]	236240	1			T1	1005		T2	669		T4	701
valid_sources[0x65]	253630	1			T1	822		T2	615		T4	783
valid_sources[0x66]	279193	1			T1	964		T2	658		T4	895
valid_sources[0x67]	232936	1			T1	964		T2	658		T4	728
valid_sources[0x68]	258015	1			T1	1007		T2	631		T4	1222
valid_sources[0x69]	276937	1			T1	945		T2	599		T4	593
valid_sources[0x6a]	261792	1			T1	1067		T2	574		T4	923
valid_sources[0x6b]	281992	1			T1	1092		T2	609		T4	622
valid_sources[0x6c]	241686	1			T1	1160		T2	621		T4	483
valid_sources[0x6d]	256037	1			T1	899		T2	618		T4	593
valid_sources[0x6e]	272394	1			T1	985		T2	638		T4	912
valid_sources[0x6f]	265068	1			T1	961		T2	623		T4	621
valid_sources[0x70]	252499	1			T1	839		T2	692		T4	784
valid_sources[0x71]	320211	1			T1	1077		T2	714		T4	673
valid_sources[0x72]	308868	1			T1	914		T2	609		T4	854
valid_sources[0x73]	278088	1			T1	964		T2	624		T4	990
valid_sources[0x74]	238372	1			T1	1190		T2	698		T4	511
valid_sources[0x75]	264347	1			T1	1059		T2	662		T4	703
valid_sources[0x76]	294606	1			T1	1055		T2	595		T4	586
valid_sources[0x77]	270499	1			T1	1053		T2	631		T4	1061
valid_sources[0x78]	254312	1			T1	1070		T2	662		T3	3325
valid_sources[0x79]	299308	1			T1	953		T2	656		T4	557
valid_sources[0x7a]	305184	1			T1	1145		T2	629		T4	704
valid_sources[0x7b]	239657	1			T1	960		T2	624		T4	698
valid_sources[0x7c]	266731	1			T1	951		T2	616		T4	837
valid_sources[0x7d]	247594	1			T1	895		T2	666		T4	611
valid_sources[0x7e]	232834	1			T1	918		T2	650		T4	617
valid_sources[0x7f]	246681	1			T1	1069		T2	675		T4	509
valid_sources[0x80]	294270	1			T1	1049		T2	605		T4	534

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27110985

1

T1

23364

T2

75024

T3

1479

values[0x0]

all_enables

biggest_size

13655295

1

T1

11645

T2

37822

T3

740

values[0x1]

all_enables

biggest_size

13649378

1

T1

11524

T2

37546

T3

782

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34954	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

123363

1

T2

8

T4

5

T6

35

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	46652	1			T6	47		T10	11		T20	7
values[0x0]	53853	1			T1	3		T2	19		T4	12
values[0x1]	57812	1			T1	4		T2	15		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26569	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

131748

1

T2

10

T4

7

T6

38

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	612	1			T6	1		T23	9		T25	7
valid_sources[0x01]	540	1			T23	15		T25	6		T26	2
valid_sources[0x02]	725	1			T6	1		T23	13		T8	1
valid_sources[0x03]	479	1			T23	11		T25	9		T26	8
valid_sources[0x04]	498	1			T23	17		T8	4		T25	11
valid_sources[0x05]	597	1			T1	1		T2	1		T23	13
valid_sources[0x06]	763	1			T9	1		T23	15		T101	3
valid_sources[0x07]	575	1			T20	7		T23	10		T25	5
valid_sources[0x08]	555	1			T1	1		T23	14		T25	10
valid_sources[0x09]	658	1			T23	17		T25	11		T26	13
valid_sources[0x0a]	744	1			T6	3		T9	1		T23	8
valid_sources[0x0b]	702	1			T6	1		T23	11		T50	1
valid_sources[0x0c]	559	1			T23	17		T43	1		T13	1
valid_sources[0x0d]	534	1			T23	16		T8	3		T25	12
valid_sources[0x0e]	743	1			T23	9		T25	11		T26	8
valid_sources[0x0f]	700	1			T23	8		T24	2		T77	1
valid_sources[0x10]	674	1			T9	3		T23	20		T8	1
valid_sources[0x11]	757	1			T2	1		T23	11		T8	1
valid_sources[0x12]	640	1			T5	1		T11	1		T23	14
valid_sources[0x13]	701	1			T4	1		T23	11		T8	3
valid_sources[0x14]	442	1			T9	1		T23	12		T25	13
valid_sources[0x15]	575	1			T23	7		T8	2		T25	5
valid_sources[0x16]	460	1			T23	8		T25	6		T143	1
valid_sources[0x17]	530	1			T6	3		T23	8		T8	1
valid_sources[0x18]	544	1			T23	16		T25	10		T26	16
valid_sources[0x19]	531	1			T23	4		T8	1		T25	11
valid_sources[0x1a]	838	1			T4	1		T23	9		T24	2
valid_sources[0x1b]	559	1			T6	1		T23	6		T8	2
valid_sources[0x1c]	714	1			T23	15		T25	9		T26	7
valid_sources[0x1d]	477	1			T23	12		T43	1		T8	1
valid_sources[0x1e]	418	1			T6	3		T23	15		T53	3
valid_sources[0x1f]	509	1			T23	9		T101	3		T8	1
valid_sources[0x20]	606	1			T23	9		T25	9		T26	5
valid_sources[0x21]	518	1			T23	13		T25	14		T132	2
valid_sources[0x22]	647	1			T23	14		T8	1		T25	10
valid_sources[0x23]	624	1			T23	14		T24	1		T25	10
valid_sources[0x24]	607	1			T9	1		T23	16		T42	1
valid_sources[0x25]	642	1			T23	19		T25	6		T26	3
valid_sources[0x26]	867	1			T4	3		T6	1		T23	14
valid_sources[0x27]	524	1			T63	1		T23	9		T8	1
valid_sources[0x28]	491	1			T23	19		T8	1		T25	11
valid_sources[0x29]	1101	1			T6	1		T23	8		T25	13
valid_sources[0x2a]	541	1			T4	1		T23	10		T24	1
valid_sources[0x2b]	489	1			T23	10		T25	9		T26	22
valid_sources[0x2c]	479	1			T23	10		T25	13		T26	11
valid_sources[0x2d]	508	1			T2	1		T23	10		T50	1
valid_sources[0x2e]	714	1			T23	10		T42	1		T25	14
valid_sources[0x2f]	651	1			T6	1		T23	15		T7	1
valid_sources[0x30]	587	1			T6	1		T64	1		T23	13
valid_sources[0x31]	714	1			T1	2		T6	4		T23	10
valid_sources[0x32]	779	1			T23	16		T25	5		T132	2
valid_sources[0x33]	807	1			T6	1		T12	1		T23	13
valid_sources[0x34]	619	1			T6	1		T23	12		T8	1
valid_sources[0x35]	441	1			T6	3		T23	12		T25	6
valid_sources[0x36]	693	1			T23	17		T27	1		T25	10
valid_sources[0x37]	595	1			T4	1		T6	1		T23	11
valid_sources[0x38]	531	1			T23	12		T25	10		T26	10
valid_sources[0x39]	539	1			T23	14		T25	11		T144	10
valid_sources[0x3a]	555	1			T23	13		T24	3		T25	10
valid_sources[0x3b]	503	1			T2	1		T23	9		T8	1
valid_sources[0x3c]	724	1			T23	6		T25	7		T26	25
valid_sources[0x3d]	518	1			T6	3		T20	1		T23	12
valid_sources[0x3e]	527	1			T23	7		T25	11		T26	15
valid_sources[0x3f]	862	1			T2	1		T4	1		T6	1
valid_sources[0x40]	944	1			T2	1		T23	18		T24	1
valid_sources[0x41]	648	1			T23	15		T25	7		T46	2
valid_sources[0x42]	534	1			T20	2		T23	13		T8	1
valid_sources[0x43]	585	1			T23	6		T25	14		T26	51
valid_sources[0x44]	490	1			T23	13		T25	3		T26	7
valid_sources[0x45]	737	1			T9	1		T23	16		T25	11
valid_sources[0x46]	627	1			T23	16		T25	15		T26	16
valid_sources[0x47]	741	1			T23	11		T24	1		T8	3
valid_sources[0x48]	897	1			T2	1		T23	18		T25	8
valid_sources[0x49]	935	1			T2	1		T6	1		T23	11
valid_sources[0x4a]	795	1			T12	1		T23	17		T8	1
valid_sources[0x4b]	530	1			T9	2		T23	11		T25	7
valid_sources[0x4c]	540	1			T2	1		T23	20		T24	2
valid_sources[0x4d]	513	1			T3	1		T10	50		T23	10
valid_sources[0x4e]	985	1			T4	1		T23	12		T25	9
valid_sources[0x4f]	535	1			T23	18		T77	1		T8	1
valid_sources[0x50]	583	1			T6	1		T23	10		T25	11
valid_sources[0x51]	562	1			T6	1		T23	15		T25	8
valid_sources[0x52]	610	1			T23	10		T8	1		T25	9
valid_sources[0x53]	971	1			T6	1		T23	16		T25	11
valid_sources[0x54]	507	1			T23	13		T25	6		T26	11
valid_sources[0x55]	675	1			T23	8		T8	1		T25	6
valid_sources[0x56]	723	1			T2	1		T6	1		T9	1
valid_sources[0x57]	866	1			T4	1		T6	2		T23	16
valid_sources[0x58]	848	1			T6	1		T23	14		T25	7
valid_sources[0x59]	665	1			T23	9		T8	1		T25	8
valid_sources[0x5a]	558	1			T6	2		T23	14		T8	1
valid_sources[0x5b]	537	1			T2	1		T23	11		T25	8
valid_sources[0x5c]	559	1			T23	13		T43	3		T8	1
valid_sources[0x5d]	589	1			T23	21		T8	1		T25	10
valid_sources[0x5e]	763	1			T23	7		T25	12		T134	1
valid_sources[0x5f]	472	1			T23	10		T51	5		T13	1
valid_sources[0x60]	422	1			T23	12		T25	10		T26	7
valid_sources[0x61]	776	1			T23	5		T25	13		T26	11
valid_sources[0x62]	579	1			T23	9		T25	10		T26	25
valid_sources[0x63]	639	1			T6	1		T23	16		T8	1
valid_sources[0x64]	728	1			T23	9		T25	7		T132	2
valid_sources[0x65]	604	1			T23	15		T8	1		T25	7
valid_sources[0x66]	593	1			T23	15		T24	3		T8	1
valid_sources[0x67]	544	1			T6	1		T23	10		T50	1
valid_sources[0x68]	701	1			T6	2		T23	9		T25	4
valid_sources[0x69]	617	1			T2	2		T4	1		T6	2
valid_sources[0x6a]	555	1			T23	11		T8	3		T25	8
valid_sources[0x6b]	493	1			T23	18		T25	8		T26	3
valid_sources[0x6c]	558	1			T23	13		T42	1		T8	1
valid_sources[0x6d]	676	1			T6	2		T23	12		T8	3
valid_sources[0x6e]	616	1			T23	14		T25	10		T26	15
valid_sources[0x6f]	867	1			T6	3		T9	1		T23	3
valid_sources[0x70]	751	1			T9	2		T23	12		T8	1
valid_sources[0x71]	562	1			T23	12		T8	1		T25	9
valid_sources[0x72]	475	1			T23	7		T24	1		T25	13
valid_sources[0x73]	589	1			T23	7		T25	12		T26	6
valid_sources[0x74]	700	1			T23	11		T25	12		T26	21
valid_sources[0x75]	466	1			T12	7		T23	11		T8	1
valid_sources[0x76]	624	1			T23	11		T101	1		T25	12
valid_sources[0x77]	477	1			T6	1		T9	1		T23	8
valid_sources[0x78]	615	1			T23	11		T25	4		T145	1
valid_sources[0x79]	805	1			T23	13		T25	11		T26	10
valid_sources[0x7a]	499	1			T4	1		T6	1		T23	7
valid_sources[0x7b]	585	1			T23	8		T25	11		T26	17
valid_sources[0x7c]	520	1			T23	14		T25	9		T26	14
valid_sources[0x7d]	592	1			T6	1		T23	9		T25	5
valid_sources[0x7e]	468	1			T23	10		T78	3		T25	6
valid_sources[0x7f]	633	1			T23	9		T8	5		T25	1
valid_sources[0x80]	567	1			T5	3		T20	7		T23	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

34071

1

T6

21

T10

5

T20

2

values[0x0]

all_enables

biggest_size

45651

1

T2

6

T4

3

T6

9

values[0x1]

all_enables

biggest_size

43641

1

T2

2

T4

2

T6

5