Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13327855

1

T1

207606

T2

15049

T3

324

full_word

49728181

1

T1

46533

T2

150392

T3

3001

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	63055736	1			T1	254139		T2	165441		T3	3325
auto[TlIntgErrCmd]	100	1			T57	3		T58	4		T59	7
auto[TlIntgErrData]	105	1			T57	5		T58	5		T59	7
auto[TlIntgErrBoth]	95	1			T57	2		T58	11		T59	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28900159

1

T1

126916

T2

82501

T3

1641

auto[1]

34155877

1

T1

127223

T2

82940

T3

1684

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6385916	1			T1	103552		T2	7477		T3	162
auto[TlIntgErrNone]	partial	auto[1]	6941658	1			T1	104054		T2	7572		T3	162
auto[TlIntgErrNone]	full_word	auto[0]	22514108	1			T1	23364		T2	75024		T3	1479
auto[TlIntgErrNone]	full_word	auto[1]	27214054	1			T1	23169		T2	75368		T3	1522
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T57	1		T59	3		T118	1
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T57	2		T58	3		T59	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T58	1		T119	1		T120	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T59	1		T119	2		T121	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T57	4		T58	2		T59	5
auto[TlIntgErrData]	partial	auto[1]	43	1			T58	1		T59	1		T122	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T57	1		T123	1		T124	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T58	2		T59	1		T125	2
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T57	1		T58	3		T59	2
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T57	1		T58	8		T59	4
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T126	1		T127	1		-	-