Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	777340	1			T4	7733		T5	6656		T9	56
auto[1]	9770087	1			T1	106766		T2	48139		T4	5425
auto[2]	644920	1			T4	5001		T5	5812		T9	57
auto[3]	9641433	1			T1	106912		T2	48701		T4	2674

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13679901	1			T1	7117		T2	80913		T4	16048
auto[1]	1954797	1			T1	32073		T2	7599		T4	1910
auto[2]	1971084	1			T1	31833		T2	7614		T4	2607
auto[3]	3227998	1			T1	142655		T2	714		T4	268

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8320357

1

T2

96756

T4

20818

T6

1826

auto[1]

12513423

1

T1

213678

T2

84

T4

15

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	234612	1			T4	6457		T5	5510		T9	49
auto[0]	auto[0]	auto[1]	23815	1			T4	591		T5	533		T9	5
auto[0]	auto[0]	auto[2]	23739	1			T4	623		T5	541		T9	2
auto[0]	auto[0]	auto[3]	4973	1			T4	58		T5	67		T12	57
auto[0]	auto[1]	auto[0]	3193232	1			T2	40164		T4	4129		T6	733
auto[0]	auto[1]	auto[1]	327855	1			T2	3583		T4	786		T6	58
auto[0]	auto[1]	auto[2]	323936	1			T2	4002		T4	441		T6	90
auto[0]	auto[1]	auto[3]	66045	1			T2	353		T4	63		T6	6
auto[0]	auto[2]	auto[0]	201144	1			T4	3865		T5	4811		T12	3847
auto[0]	auto[2]	auto[1]	20290	1			T4	372		T5	511		T12	426
auto[0]	auto[2]	auto[2]	21458	1			T4	694		T5	432		T9	53
auto[0]	auto[2]	auto[3]	4138	1			T4	67		T5	47		T9	4
auto[0]	auto[3]	auto[0]	3159662	1			T2	40679		T4	1585		T6	781
auto[0]	auto[3]	auto[1]	321018	1			T2	4007		T4	158		T6	79
auto[0]	auto[3]	auto[2]	326627	1			T2	3607		T4	849		T6	69
auto[0]	auto[3]	auto[3]	67813	1			T2	361		T4	80		T6	10
auto[1]	auto[0]	auto[0]	16391	1			T4	3		T5	4		T51	13
auto[1]	auto[0]	auto[1]	72888	1			T4	1		T5	1		T12	2
auto[1]	auto[0]	auto[2]	72897	1			T51	1		T8	1		T139	1
auto[1]	auto[0]	auto[3]	328025	1			T89	1		T138	3779		T91	1
auto[1]	auto[1]	auto[0]	3433925	1			T1	3610		T2	30		T4	5
auto[1]	auto[1]	auto[1]	601046	1			T1	16062		T2	5		T4	1
auto[1]	auto[1]	auto[2]	553186	1			T1	15868		T2	2		T41	4
auto[1]	auto[1]	auto[3]	1270862	1			T1	71226		T64	6		T50	738
auto[1]	auto[2]	auto[0]	12258	1			T4	3		T5	11		T12	4
auto[1]	auto[2]	auto[1]	53911	1			T51	1		T8	2		T116	1
auto[1]	auto[2]	auto[2]	60869	1			T12	2		T51	2		T8	2
auto[1]	auto[2]	auto[3]	270852	1			T138	3314		T91	1		T140	9985
auto[1]	auto[3]	auto[0]	3428677	1			T1	3507		T2	40		T4	1
auto[1]	auto[3]	auto[1]	533974	1			T1	16011		T2	4		T4	1
auto[1]	auto[3]	auto[2]	588372	1			T1	15965		T2	3		T5	1
auto[1]	auto[3]	auto[3]	1215290	1			T1	71429		T50	722		T101	617