Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	279142787	180493	0	0
ctrl_regwen_rd_A	279142787	4034	0	0
exec_rd_A	279142787	3555	0	0
exec_regwen_rd_A	279142787	3618	0	0
readback_rd_A	279142787	2102	0	0
readback_regwen_rd_A	279142787	1997	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279142787	180493	0	0
T7	6959	0	0	0
T22	0	3076	0	0
T23	152445	4612	0	0
T24	613877	0	0	0
T25	0	2930	0	0
T26	0	4489	0	0
T27	1829	0	0	0
T42	63959	0	0	0
T43	43992	0	0	0
T45	0	1146	0	0
T48	0	4901	0	0
T49	0	1730	0	0
T50	287863	0	0	0
T51	175574	0	0	0
T52	12110	0	0	0
T53	97362	0	0	0
T54	0	3602	0	0
T55	0	3452	0	0
T65	0	2337	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279142787	4034	0	0
T16	1209	0	0	0
T22	0	247	0	0
T28	2835	0	0	0
T45	24722	76	0	0
T46	44892	0	0	0
T49	0	180	0	0
T54	0	317	0	0
T65	0	180	0	0
T66	31658	0	0	0
T67	107478	0	0	0
T68	352328	0	0	0
T108	0	108	0	0
T109	0	395	0	0
T110	0	202	0	0
T111	0	219	0	0
T112	0	203	0	0
T113	10781	0	0	0
T114	8680	0	0	0
T115	210281	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279142787	3555	0	0
T16	1209	0	0	0
T22	0	176	0	0
T28	2835	0	0	0
T45	24722	77	0	0
T46	44892	0	0	0
T49	0	120	0	0
T54	0	238	0	0
T65	0	197	0	0
T66	31658	0	0	0
T67	107478	0	0	0
T68	352328	0	0	0
T108	0	70	0	0
T109	0	368	0	0
T110	0	109	0	0
T111	0	159	0	0
T112	0	182	0	0
T113	10781	0	0	0
T114	8680	0	0	0
T115	210281	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279142787	3618	0	0
T16	1209	0	0	0
T22	0	227	0	0
T28	2835	0	0	0
T45	24722	85	0	0
T46	44892	0	0	0
T49	0	180	0	0
T54	0	330	0	0
T65	0	184	0	0
T66	31658	0	0	0
T67	107478	0	0	0
T68	352328	0	0	0
T108	0	71	0	0
T109	0	313	0	0
T110	0	94	0	0
T111	0	195	0	0
T112	0	207	0	0
T113	10781	0	0	0
T114	8680	0	0	0
T115	210281	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279142787	2102	0	0
T16	1209	0	0	0
T22	0	134	0	0
T28	2835	0	0	0
T45	24722	34	0	0
T46	44892	0	0	0
T49	0	161	0	0
T54	0	216	0	0
T65	0	111	0	0
T66	31658	0	0	0
T67	107478	0	0	0
T68	352328	0	0	0
T108	0	40	0	0
T109	0	367	0	0
T110	0	115	0	0
T111	0	167	0	0
T112	0	212	0	0
T113	10781	0	0	0
T114	8680	0	0	0
T115	210281	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	279142787	1997	0	0
T16	1209	0	0	0
T22	0	175	0	0
T28	2835	0	0	0
T45	24722	36	0	0
T46	44892	0	0	0
T49	0	146	0	0
T54	0	235	0	0
T65	0	165	0	0
T66	31658	0	0	0
T67	107478	0	0	0
T68	352328	0	0	0
T108	0	27	0	0
T109	0	332	0	0
T110	0	76	0	0
T111	0	186	0	0
T112	0	172	0	0
T113	10781	0	0	0
T114	8680	0	0	0
T115	210281	0	0	0