Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13929114	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

58794074

1

T1

8076

T2

7586

T3

4885

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36247938	1			T1	4438		T2	4649		T3	3042
values[0x0]	16847277	1			T1	2141		T2	2210		T3	1371
values[0x1]	19627973	1			T1	2268		T2	2431		T3	1594

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6939092	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

65784096

1

T1

8468

T2

8447

T3

5438

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	283694	1			T3	44		T4	32		T10	196
valid_sources[0x01]	302376	1			T3	18		T4	53		T10	197
valid_sources[0x02]	288672	1			T3	19		T4	26		T10	187
valid_sources[0x03]	306017	1			T3	13		T4	25		T10	170
valid_sources[0x04]	296438	1			T3	12		T4	41		T10	134
valid_sources[0x05]	302835	1			T3	25		T4	35		T10	201
valid_sources[0x06]	300689	1			T3	43		T4	34		T10	171
valid_sources[0x07]	262167	1			T3	27		T4	12		T10	188
valid_sources[0x08]	284849	1			T3	53		T4	22		T10	184
valid_sources[0x09]	276076	1			T3	21		T4	35		T10	166
valid_sources[0x0a]	281840	1			T3	21		T4	57		T10	184
valid_sources[0x0b]	280659	1			T3	43		T4	56		T10	180
valid_sources[0x0c]	253140	1			T3	23		T4	43		T10	170
valid_sources[0x0d]	290431	1			T3	19		T4	33		T10	202
valid_sources[0x0e]	274974	1			T3	25		T4	44		T10	193
valid_sources[0x0f]	356791	1			T3	28		T4	53		T10	175
valid_sources[0x10]	331346	1			T3	33		T4	49		T10	168
valid_sources[0x11]	245834	1			T3	28		T4	25		T10	183
valid_sources[0x12]	282790	1			T3	13		T4	48		T10	171
valid_sources[0x13]	289250	1			T3	23		T4	24		T10	175
valid_sources[0x14]	293407	1			T3	17		T4	24		T10	156
valid_sources[0x15]	299830	1			T3	38		T4	24		T10	164
valid_sources[0x16]	260221	1			T3	24		T4	43		T10	168
valid_sources[0x17]	272716	1			T3	23		T4	58		T10	172
valid_sources[0x18]	283242	1			T3	16		T4	45		T10	182
valid_sources[0x19]	336906	1			T3	34		T4	48		T10	190
valid_sources[0x1a]	269765	1			T3	8		T4	40		T10	208
valid_sources[0x1b]	274702	1			T3	10		T4	23		T10	181
valid_sources[0x1c]	282161	1			T3	19		T4	34		T10	176
valid_sources[0x1d]	295703	1			T3	25		T4	15		T10	200
valid_sources[0x1e]	299950	1			T3	39		T4	63		T10	178
valid_sources[0x1f]	259545	1			T3	27		T4	23		T10	179
valid_sources[0x20]	245443	1			T3	25		T4	37		T10	164
valid_sources[0x21]	323045	1			T3	23		T4	27		T10	171
valid_sources[0x22]	256078	1			T3	4		T4	32		T10	190
valid_sources[0x23]	251422	1			T3	14		T4	46		T10	186
valid_sources[0x24]	256941	1			T3	16		T4	56		T10	198
valid_sources[0x25]	294515	1			T3	52		T4	43		T10	182
valid_sources[0x26]	252342	1			T3	29		T4	41		T10	177
valid_sources[0x27]	290173	1			T3	21		T4	38		T10	144
valid_sources[0x28]	271501	1			T3	39		T4	58		T10	167
valid_sources[0x29]	257048	1			T3	20		T4	48		T10	215
valid_sources[0x2a]	280161	1			T3	11		T4	35		T10	170
valid_sources[0x2b]	309754	1			T3	17		T4	57		T10	191
valid_sources[0x2c]	337483	1			T3	33		T4	53		T10	187
valid_sources[0x2d]	251476	1			T3	17		T4	28		T10	197
valid_sources[0x2e]	265841	1			T3	41		T4	33		T10	171
valid_sources[0x2f]	270337	1			T3	20		T4	17		T10	190
valid_sources[0x30]	301128	1			T3	9		T4	60		T10	190
valid_sources[0x31]	292748	1			T3	20		T4	9		T10	188
valid_sources[0x32]	249467	1			T3	30		T4	48		T10	179
valid_sources[0x33]	262665	1			T3	23		T4	31		T10	169
valid_sources[0x34]	315902	1			T3	15		T4	34		T10	184
valid_sources[0x35]	248968	1			T3	34		T4	27		T10	192
valid_sources[0x36]	330577	1			T3	24		T4	29		T10	201
valid_sources[0x37]	313458	1			T3	16		T4	51		T10	149
valid_sources[0x38]	291621	1			T3	33		T4	44		T10	164
valid_sources[0x39]	261450	1			T3	33		T4	38		T10	182
valid_sources[0x3a]	283393	1			T3	28		T4	23		T10	217
valid_sources[0x3b]	286860	1			T3	21		T4	27		T10	181
valid_sources[0x3c]	263522	1			T3	15		T4	32		T10	208
valid_sources[0x3d]	273332	1			T3	21		T4	55		T10	177
valid_sources[0x3e]	298008	1			T3	12		T4	38		T10	199
valid_sources[0x3f]	257139	1			T3	12		T4	28		T10	193
valid_sources[0x40]	257212	1			T3	15		T4	24		T10	194
valid_sources[0x41]	273537	1			T3	14		T4	28		T10	174
valid_sources[0x42]	273378	1			T3	14		T4	30		T10	203
valid_sources[0x43]	242535	1			T3	16		T4	49		T10	187
valid_sources[0x44]	310635	1			T3	16		T4	33		T10	166
valid_sources[0x45]	254956	1			T3	25		T4	19		T10	182
valid_sources[0x46]	255519	1			T3	28		T4	33		T10	178
valid_sources[0x47]	282186	1			T3	21		T4	34		T10	183
valid_sources[0x48]	277658	1			T3	15		T4	33		T10	183
valid_sources[0x49]	251843	1			T3	26		T4	21		T10	201
valid_sources[0x4a]	291863	1			T3	34		T4	57		T10	185
valid_sources[0x4b]	315139	1			T3	27		T4	65		T10	211
valid_sources[0x4c]	264580	1			T3	25		T4	49		T10	202
valid_sources[0x4d]	270371	1			T3	22		T4	34		T10	196
valid_sources[0x4e]	240486	1			T3	16		T4	24		T10	173
valid_sources[0x4f]	273320	1			T3	14		T4	44		T10	176
valid_sources[0x50]	285375	1			T3	17		T4	37		T10	178
valid_sources[0x51]	260023	1			T3	27		T4	28		T10	205
valid_sources[0x52]	267122	1			T3	29		T4	42		T10	178
valid_sources[0x53]	277315	1			T3	23		T4	29		T10	162
valid_sources[0x54]	247841	1			T3	16		T4	41		T10	211
valid_sources[0x55]	276313	1			T3	31		T4	39		T10	164
valid_sources[0x56]	244517	1			T3	9		T4	64		T10	169
valid_sources[0x57]	262840	1			T3	61		T4	18		T10	182
valid_sources[0x58]	333783	1			T3	9		T4	30		T10	162
valid_sources[0x59]	297971	1			T3	22		T4	25		T10	178
valid_sources[0x5a]	273504	1			T3	30		T4	54		T10	223
valid_sources[0x5b]	256702	1			T3	24		T4	35		T10	156
valid_sources[0x5c]	320900	1			T3	22		T4	43		T10	192
valid_sources[0x5d]	295230	1			T3	16		T4	28		T10	182
valid_sources[0x5e]	269817	1			T3	32		T4	38		T10	183
valid_sources[0x5f]	255217	1			T3	28		T4	44		T10	165
valid_sources[0x60]	324678	1			T3	31		T4	64		T10	213
valid_sources[0x61]	292982	1			T3	21		T4	37		T10	163
valid_sources[0x62]	338278	1			T3	14		T4	34		T10	176
valid_sources[0x63]	333306	1			T3	16		T4	68		T10	164
valid_sources[0x64]	330260	1			T3	12		T4	56		T10	178
valid_sources[0x65]	372245	1			T3	12		T4	14		T10	184
valid_sources[0x66]	293673	1			T3	27		T4	65		T10	212
valid_sources[0x67]	255984	1			T3	21		T4	44		T10	176
valid_sources[0x68]	274302	1			T3	15		T4	32		T10	185
valid_sources[0x69]	269553	1			T3	3		T4	63		T10	202
valid_sources[0x6a]	277826	1			T3	17		T4	49		T10	193
valid_sources[0x6b]	277904	1			T3	18		T4	29		T10	183
valid_sources[0x6c]	251093	1			T3	24		T4	36		T10	193
valid_sources[0x6d]	330830	1			T3	19		T4	84		T10	175
valid_sources[0x6e]	323288	1			T3	15		T4	40		T10	197
valid_sources[0x6f]	280382	1			T3	7		T4	36		T10	191
valid_sources[0x70]	285354	1			T3	12		T4	44		T10	185
valid_sources[0x71]	249998	1			T3	16		T4	60		T10	192
valid_sources[0x72]	247949	1			T3	3		T4	49		T10	181
valid_sources[0x73]	266995	1			T3	22		T4	30		T10	181
valid_sources[0x74]	287496	1			T3	29		T4	28		T10	206
valid_sources[0x75]	277513	1			T3	19		T4	28		T10	154
valid_sources[0x76]	302051	1			T3	27		T4	58		T10	204
valid_sources[0x77]	290440	1			T3	36		T4	38		T10	182
valid_sources[0x78]	260603	1			T3	23		T4	32		T10	190
valid_sources[0x79]	264521	1			T3	22		T4	36		T10	169
valid_sources[0x7a]	261769	1			T3	24		T4	22		T10	181
valid_sources[0x7b]	254833	1			T3	18		T4	43		T10	202
valid_sources[0x7c]	263656	1			T3	10		T4	54		T10	170
valid_sources[0x7d]	273127	1			T3	18		T4	32		T10	176
valid_sources[0x7e]	250885	1			T3	19		T4	47		T10	178
valid_sources[0x7f]	276187	1			T3	32		T4	53		T10	187
valid_sources[0x80]	287411	1			T3	20		T4	16		T10	181

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29287451

1

T1

4043

T2

3785

T3

2478

values[0x0]

all_enables

biggest_size

14757773

1

T1

2016

T2

1944

T3

1206

values[0x1]

all_enables

biggest_size

14748850

1

T1

2017

T2

1857

T3

1201

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35859	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

134730

1

T4

1

T10

5

T5

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	49496	1			T13	970		T7	2		T21	1291
values[0x0]	58437	1			T4	1		T10	11		T11	1
values[0x1]	62656	1			T1	1		T2	2		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27403	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

143186

1

T2

1

T3

1

T4

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	674	1			T13	13		T21	3		T80	1
valid_sources[0x01]	510	1			T13	3		T21	1		T26	10
valid_sources[0x02]	656	1			T13	28		T21	1		T9	2
valid_sources[0x03]	656	1			T13	7		T98	1		T26	7
valid_sources[0x04]	430	1			T13	5		T23	1		T9	1
valid_sources[0x05]	829	1			T11	1		T13	10		T80	1
valid_sources[0x06]	488	1			T13	6		T21	1		T9	3
valid_sources[0x07]	653	1			T13	29		T26	8		T47	12
valid_sources[0x08]	627	1			T13	26		T9	1		T26	13
valid_sources[0x09]	576	1			T13	32		T9	1		T64	1
valid_sources[0x0a]	632	1			T13	5		T9	1		T64	1
valid_sources[0x0b]	701	1			T13	22		T21	174		T26	9
valid_sources[0x0c]	663	1			T13	29		T26	12		T20	2
valid_sources[0x0d]	593	1			T1	1		T13	9		T44	1
valid_sources[0x0e]	603	1			T4	1		T13	40		T43	2
valid_sources[0x0f]	734	1			T13	9		T26	9		T47	27
valid_sources[0x10]	493	1			T13	27		T44	3		T9	1
valid_sources[0x11]	548	1			T13	6		T21	5		T9	1
valid_sources[0x12]	1018	1			T13	12		T21	219		T9	1
valid_sources[0x13]	695	1			T13	11		T26	4		T47	6
valid_sources[0x14]	781	1			T10	1		T13	57		T21	192
valid_sources[0x15]	481	1			T13	7		T14	2		T22	1
valid_sources[0x16]	582	1			T13	10		T21	2		T44	2
valid_sources[0x17]	682	1			T13	11		T64	1		T26	3
valid_sources[0x18]	717	1			T10	1		T13	14		T14	1
valid_sources[0x19]	762	1			T13	8		T21	192		T9	1
valid_sources[0x1a]	540	1			T13	19		T14	1		T82	1
valid_sources[0x1b]	664	1			T13	12		T21	2		T26	11
valid_sources[0x1c]	690	1			T13	7		T14	1		T23	1
valid_sources[0x1d]	801	1			T13	8		T21	173		T9	1
valid_sources[0x1e]	973	1			T13	2		T14	1		T26	9
valid_sources[0x1f]	559	1			T13	12		T98	1		T9	1
valid_sources[0x20]	650	1			T13	21		T21	1		T23	1
valid_sources[0x21]	531	1			T13	38		T21	3		T26	4
valid_sources[0x22]	575	1			T13	26		T23	1		T64	1
valid_sources[0x23]	580	1			T13	10		T9	1		T64	2
valid_sources[0x24]	570	1			T13	6		T137	17		T26	13
valid_sources[0x25]	511	1			T13	2		T9	1		T26	10
valid_sources[0x26]	918	1			T13	46		T21	1		T80	1
valid_sources[0x27]	735	1			T13	8		T26	7		T20	1
valid_sources[0x28]	935	1			T13	1		T21	5		T9	1
valid_sources[0x29]	603	1			T10	1		T13	4		T21	52
valid_sources[0x2a]	590	1			T13	12		T21	3		T9	1
valid_sources[0x2b]	686	1			T13	29		T21	1		T9	2
valid_sources[0x2c]	785	1			T13	4		T21	3		T23	1
valid_sources[0x2d]	862	1			T13	38		T14	1		T21	89
valid_sources[0x2e]	640	1			T13	3		T21	2		T22	13
valid_sources[0x2f]	483	1			T10	1		T13	27		T138	2
valid_sources[0x30]	500	1			T13	8		T64	1		T26	12
valid_sources[0x31]	648	1			T13	7		T21	1		T64	1
valid_sources[0x32]	504	1			T13	7		T9	1		T64	1
valid_sources[0x33]	716	1			T13	14		T9	2		T26	8
valid_sources[0x34]	783	1			T2	1		T13	3		T21	1
valid_sources[0x35]	597	1			T13	19		T21	5		T64	1
valid_sources[0x36]	607	1			T13	2		T21	1		T99	1
valid_sources[0x37]	948	1			T13	32		T21	93		T81	1
valid_sources[0x38]	540	1			T13	6		T14	1		T23	2
valid_sources[0x39]	574	1			T13	4		T21	3		T139	3
valid_sources[0x3a]	531	1			T10	1		T13	5		T26	8
valid_sources[0x3b]	608	1			T13	1		T21	1		T139	6
valid_sources[0x3c]	543	1			T13	16		T21	38		T81	1
valid_sources[0x3d]	560	1			T13	8		T21	3		T9	1
valid_sources[0x3e]	587	1			T13	33		T21	4		T9	1
valid_sources[0x3f]	553	1			T13	2		T21	13		T9	2
valid_sources[0x40]	697	1			T13	10		T21	70		T9	2
valid_sources[0x41]	503	1			T13	14		T14	1		T9	1
valid_sources[0x42]	453	1			T13	20		T26	8		T47	1
valid_sources[0x43]	766	1			T13	23		T82	1		T139	5
valid_sources[0x44]	723	1			T2	1		T13	6		T21	5
valid_sources[0x45]	708	1			T13	15		T23	1		T64	2
valid_sources[0x46]	602	1			T13	24		T49	1		T26	12
valid_sources[0x47]	648	1			T13	24		T21	1		T9	1
valid_sources[0x48]	465	1			T10	1		T13	4		T26	4
valid_sources[0x49]	1010	1			T13	8		T23	1		T26	7
valid_sources[0x4a]	607	1			T13	3		T21	2		T26	12
valid_sources[0x4b]	705	1			T13	35		T21	1		T64	2
valid_sources[0x4c]	813	1			T13	14		T15	6		T21	158
valid_sources[0x4d]	751	1			T13	3		T7	84		T23	2
valid_sources[0x4e]	635	1			T13	7		T21	1		T26	4
valid_sources[0x4f]	503	1			T13	9		T21	19		T80	1
valid_sources[0x50]	474	1			T13	8		T21	4		T44	3
valid_sources[0x51]	747	1			T13	6		T21	23		T64	1
valid_sources[0x52]	483	1			T13	1		T139	1		T9	2
valid_sources[0x53]	713	1			T13	16		T21	98		T22	7
valid_sources[0x54]	537	1			T13	30		T21	2		T44	1
valid_sources[0x55]	771	1			T13	7		T82	1		T8	121
valid_sources[0x56]	659	1			T13	7		T9	1		T64	1
valid_sources[0x57]	963	1			T13	3		T14	1		T21	178
valid_sources[0x58]	699	1			T13	3		T21	2		T9	2
valid_sources[0x59]	753	1			T13	14		T21	24		T44	2
valid_sources[0x5a]	713	1			T13	13		T9	2		T64	2
valid_sources[0x5b]	573	1			T13	17		T21	55		T26	14
valid_sources[0x5c]	616	1			T13	13		T9	2		T26	10
valid_sources[0x5d]	556	1			T13	24		T21	34		T9	1
valid_sources[0x5e]	583	1			T13	7		T21	2		T23	1
valid_sources[0x5f]	682	1			T21	116		T9	2		T26	6
valid_sources[0x60]	893	1			T13	9		T64	1		T65	148
valid_sources[0x61]	931	1			T10	1		T13	4		T9	1
valid_sources[0x62]	705	1			T13	3		T21	229		T99	1
valid_sources[0x63]	543	1			T13	25		T98	1		T23	1
valid_sources[0x64]	556	1			T13	8		T21	1		T81	4
valid_sources[0x65]	496	1			T13	21		T21	6		T23	1
valid_sources[0x66]	584	1			T13	9		T14	1		T21	2
valid_sources[0x67]	550	1			T13	13		T23	1		T9	1
valid_sources[0x68]	575	1			T13	6		T15	7		T21	5
valid_sources[0x69]	582	1			T5	1		T13	5		T21	144
valid_sources[0x6a]	883	1			T10	1		T13	8		T9	2
valid_sources[0x6b]	656	1			T13	1		T21	1		T26	12
valid_sources[0x6c]	503	1			T13	25		T23	1		T26	10
valid_sources[0x6d]	857	1			T13	25		T67	2		T140	1
valid_sources[0x6e]	1006	1			T13	21		T23	1		T9	1
valid_sources[0x6f]	660	1			T13	17		T41	32		T9	3
valid_sources[0x70]	890	1			T13	30		T21	3		T9	1
valid_sources[0x71]	547	1			T13	8		T100	1		T26	13
valid_sources[0x72]	1256	1			T13	42		T21	427		T9	2
valid_sources[0x73]	506	1			T13	20		T21	2		T9	1
valid_sources[0x74]	761	1			T13	32		T141	2		T26	14
valid_sources[0x75]	663	1			T13	14		T14	1		T21	7
valid_sources[0x76]	818	1			T13	5		T16	17		T26	11
valid_sources[0x77]	758	1			T13	29		T21	181		T9	3
valid_sources[0x78]	471	1			T13	16		T14	1		T139	1
valid_sources[0x79]	544	1			T13	1		T9	1		T26	8
valid_sources[0x7a]	742	1			T13	34		T9	1		T26	8
valid_sources[0x7b]	495	1			T13	8		T21	2		T82	1
valid_sources[0x7c]	517	1			T13	27		T64	1		T26	8
valid_sources[0x7d]	454	1			T13	1		T21	1		T9	1
valid_sources[0x7e]	672	1			T13	24		T44	2		T23	1
valid_sources[0x7f]	723	1			T13	38		T21	1		T26	8
valid_sources[0x80]	656	1			T10	3		T13	27		T21	94

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

36920

1

T13

895

T21

1192

T22

3

values[0x0]

all_enables

biggest_size

49781

1

T4

1

T10

4

T5

1

values[0x1]

all_enables

biggest_size

48029

1

T10

1

T13

1229

T7

9