Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13600718

1

T1

771

T2

1704

T3

1122

full_word

53732665

1

T1

8076

T2

7586

T3

4885

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	67333113	1			T1	8847		T2	9290		T3	6007
auto[TlIntgErrCmd]	93	1			T58	2		T59	10		T60	3
auto[TlIntgErrData]	92	1			T58	4		T59	8		T60	2
auto[TlIntgErrBoth]	85	1			T58	4		T59	2		T60	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30798650

1

T1

4438

T2

4649

T3

3042

auto[1]

36534733

1

T1

4409

T2

4641

T3

2965

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6497496	1			T1	395		T2	864		T3	564
auto[TlIntgErrNone]	partial	auto[1]	7102977	1			T1	376		T2	840		T3	558
auto[TlIntgErrNone]	full_word	auto[0]	24301040	1			T1	4043		T2	3785		T3	2478
auto[TlIntgErrNone]	full_word	auto[1]	29431600	1			T1	4033		T2	3801		T3	2407
auto[TlIntgErrCmd]	partial	auto[0]	23	1			T58	2		T59	4		T60	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T59	4		T60	1		T126	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T59	1		T125	1		T121	1
auto[TlIntgErrCmd]	full_word	auto[1]	11	1			T59	1		T60	1		T124	2
auto[TlIntgErrData]	partial	auto[0]	51	1			T58	4		T59	2		T60	2
auto[TlIntgErrData]	partial	auto[1]	36	1			T59	4		T126	3		T124	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T59	1		T122	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T59	1		T122	1		T127	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T58	1		T59	1		T60	1
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T58	3		T59	1		T60	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T128	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T60	2		T125	1		T129	1