Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	642525	1			T22	8		T42	16		T41	1616
auto[1]	11123150	1			T1	4416		T2	4647		T3	3042
auto[2]	533596	1			T22	7		T42	14		T41	1375
auto[3]	11026616	1			T1	4388		T2	4640		T3	2964

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14276541	1			T1	7385		T2	6220		T3	3970
auto[1]	2307521	1			T1	653		T2	1363		T3	914
auto[2]	2317525	1			T1	700		T2	1419		T3	893
auto[3]	4424300	1			T1	66		T2	285		T3	229

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9162904

1

T1

8793

T2

9277

T3

6005

auto[1]

14162983

1

T1

11

T2

10

T3

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	276062	1			T22	6		T42	10		T41	1337
auto[0]	auto[0]	auto[1]	28172	1			T22	1		T42	4		T41	128
auto[0]	auto[0]	auto[2]	28530	1			T22	1		T42	2		T41	135
auto[0]	auto[0]	auto[3]	7068	1			T41	16		T8	27		T86	52
auto[0]	auto[1]	auto[0]	3512551	1			T1	3705		T2	3105		T3	2007
auto[0]	auto[1]	auto[1]	359942	1			T1	312		T2	675		T3	470
auto[0]	auto[1]	auto[2]	351924	1			T1	359		T2	731		T3	450
auto[0]	auto[1]	auto[3]	65828	1			T1	32		T2	133		T3	114
auto[0]	auto[2]	auto[0]	233013	1			T41	1172		T8	1115		T9	3561
auto[0]	auto[2]	auto[1]	23913	1			T41	127		T8	111		T9	367
auto[0]	auto[2]	auto[2]	26259	1			T22	5		T42	13		T41	67
auto[0]	auto[2]	auto[3]	5669	1			T22	2		T42	1		T41	7
auto[0]	auto[3]	auto[0]	3470419	1			T1	3671		T2	3108		T3	1963
auto[0]	auto[3]	auto[1]	347528	1			T1	340		T2	688		T3	443
auto[0]	auto[3]	auto[2]	359252	1			T1	340		T2	685		T3	443
auto[0]	auto[3]	auto[3]	66774	1			T1	34		T2	152		T3	115
auto[1]	auto[0]	auto[0]	10336	1			T82	219		T8	2		T9	2
auto[1]	auto[0]	auto[1]	45240	1			T82	908		T65	1		T132	2
auto[1]	auto[0]	auto[2]	45101	1			T82	887		T133	1		T131	1331
auto[1]	auto[0]	auto[3]	202016	1			T82	3988		T88	3		T131	6128
auto[1]	auto[1]	auto[0]	3382103	1			T1	6		T2	3		T4	7
auto[1]	auto[1]	auto[1]	741589	1			T1	1		T3	1		T6	9489
auto[1]	auto[1]	auto[2]	734541	1			T1	1		T6	10765		T13	1
auto[1]	auto[1]	auto[3]	1974672	1			T6	43291		T66	768		T80	802
auto[1]	auto[2]	auto[0]	8088	1			T41	2		T9	2		T134	2
auto[1]	auto[2]	auto[1]	35357	1			T134	1		T132	3		T131	833
auto[1]	auto[2]	auto[2]	36308	1			T82	870		T65	1		T130	1
auto[1]	auto[2]	auto[3]	164989	1			T82	3792		T131	5814		T135	11444
auto[1]	auto[3]	auto[0]	3383969	1			T1	3		T2	4		T11	2
auto[1]	auto[3]	auto[1]	725780	1			T11	1		T6	10676		T7	2
auto[1]	auto[3]	auto[2]	735610	1			T2	3		T6	9608		T13	3
auto[1]	auto[3]	auto[3]	1937284	1			T6	43098		T66	713		T80	820