Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	305958331	190956	0	0
ctrl_regwen_rd_A	305958331	4155	0	0
exec_rd_A	305958331	4238	0	0
exec_regwen_rd_A	305958331	4575	0	0
readback_rd_A	305958331	2364	0	0
readback_regwen_rd_A	305958331	2146	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305958331	190956	0	0
T7	899796	0	0	0
T13	101596	5731	0	0
T14	1011	0	0	0
T15	1724	0	0	0
T16	1187	0	0	0
T21	136264	8312	0	0
T22	354255	0	0	0
T24	0	2300	0	0
T26	0	3771	0	0
T43	14284	0	0	0
T47	0	3044	0	0
T48	0	3114	0	0
T66	285451	0	0	0
T67	1555	0	0	0
T68	0	2079	0	0
T69	0	11890	0	0
T70	0	6560	0	0
T71	0	1083	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305958331	4155	0	0
T48	179178	98	0	0
T71	21447	57	0	0
T104	0	37	0	0
T105	0	230	0	0
T106	0	439	0	0
T107	0	244	0	0
T108	0	222	0	0
T109	0	196	0	0
T110	0	401	0	0
T111	0	276	0	0
T112	2322	0	0	0
T113	479493	0	0	0
T114	409952	0	0	0
T115	42046	0	0	0
T116	3408	0	0	0
T117	261331	0	0	0
T118	122564	0	0	0
T119	8220	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305958331	4238	0	0
T48	179178	67	0	0
T71	21447	58	0	0
T104	0	46	0	0
T105	0	242	0	0
T106	0	315	0	0
T107	0	298	0	0
T108	0	133	0	0
T109	0	217	0	0
T110	0	363	0	0
T111	0	289	0	0
T112	2322	0	0	0
T113	479493	0	0	0
T114	409952	0	0	0
T115	42046	0	0	0
T116	3408	0	0	0
T117	261331	0	0	0
T118	122564	0	0	0
T119	8220	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305958331	4575	0	0
T48	179178	94	0	0
T71	21447	74	0	0
T104	0	55	0	0
T105	0	339	0	0
T106	0	482	0	0
T107	0	277	0	0
T108	0	168	0	0
T109	0	289	0	0
T110	0	365	0	0
T111	0	288	0	0
T112	2322	0	0	0
T113	479493	0	0	0
T114	409952	0	0	0
T115	42046	0	0	0
T116	3408	0	0	0
T117	261331	0	0	0
T118	122564	0	0	0
T119	8220	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305958331	2364	0	0
T48	179178	68	0	0
T71	21447	55	0	0
T104	0	50	0	0
T105	0	260	0	0
T106	0	335	0	0
T107	0	239	0	0
T108	0	230	0	0
T109	0	192	0	0
T110	0	354	0	0
T111	0	202	0	0
T112	2322	0	0	0
T113	479493	0	0	0
T114	409952	0	0	0
T115	42046	0	0	0
T116	3408	0	0	0
T117	261331	0	0	0
T118	122564	0	0	0
T119	8220	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305958331	2146	0	0
T48	179178	120	0	0
T71	21447	48	0	0
T104	0	30	0	0
T105	0	247	0	0
T106	0	371	0	0
T107	0	127	0	0
T108	0	195	0	0
T109	0	159	0	0
T110	0	251	0	0
T111	0	287	0	0
T112	2322	0	0	0
T113	479493	0	0	0
T114	409952	0	0	0
T115	42046	0	0	0
T116	3408	0	0	0
T117	261331	0	0	0
T118	122564	0	0	0
T119	8220	0	0	0