Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	148007754	1			T1	560180		T2	273328		T3	2520
instr_valid_dis	117001903	1			T1	560180		T2	273328		T3	2520
instr_en	21503164	1			T4	199168		T9	61296		T11	79112

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10528798	1			T11	33936		T20	24750		T5	36680
sram_ifetch_valid_disable	115712914	1			T1	560180		T2	273328		T3	2520
sram_ifetch_enable	21766042	1			T4	1384		T9	47195		T11	57538

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	148007754	1			T1	560180		T2	273328		T3	2520
hw_debug_en_valid_off	112814438	1			T1	560180		T2	273328		T3	2520
hw_debug_en_on	23717173	1			T4	135546		T9	61296		T11	25738

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	115712914	1			T1	560180		T2	273328		T3	2520
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	103239320	1			T1	560180		T2	273328		T3	2520
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8579343	1			T4	197784		T9	14101		T11	6688
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3364223	1			T20	24700		T5	17794		T64	38542
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1510071	1			T64	38542		T67	28356		T133	33944
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1208648	1			T42	22588		T112	17064		T134	92
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5026212	1			T5	18886		T64	29426		T42	430356
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2386263	1			T5	18886		T42	422742		T43	74
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1743847	1			T64	29426		T42	7614		T68	15460
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9494733	1			T4	135546		T9	14101		T11	6688
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4599580	1			T4	32000		T5	148364		T64	2112
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3221981	1			T4	103546		T9	14101		T11	6688

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9132156	1			T4	1384		T9	47195		T11	38488
lc_exec_en	9196228	1			T9	47195		T11	19050		T20	14234
valid_exec_dis	109888069	1			T1	560180		T2	273328		T3	2520
invalid_exec_dis	32294840	1			T4	1384		T9	47195		T11	91474