Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44443339	1			T1	51134		T2	124279		T3	237
triple_byte_access	2632809	1			T1	45764		T2	2513		T3	234
halfword_access	3950840	1			T1	68832		T2	3685		T3	292
byte_access	5278150	1			T1	91593		T2	5009		T3	404
zero_access	1327927	1			T1	22767		T2	1178		T3	93

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28760050

1

T1

139910

T2

68430

T3

648

auto[1]

28873015

1

T1

140180

T2

68234

T3

612

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22168072	1			T1	25441		T2	62170		T3	125
auto[0]	triple_byte_access	1313664	1			T1	22762		T2	1280		T3	116
auto[0]	halfword_access	1973177	1			T1	34647		T2	1868		T3	153
auto[0]	byte_access	2637835	1			T1	45810		T2	2544		T3	209
auto[0]	zero_access	667302	1			T1	11250		T2	568		T3	45
auto[1]	word_access	22275267	1			T1	25693		T2	62109		T3	112
auto[1]	triple_byte_access	1319145	1			T1	23002		T2	1233		T3	118
auto[1]	halfword_access	1977663	1			T1	34185		T2	1817		T3	139
auto[1]	byte_access	2640315	1			T1	45783		T2	2465		T3	195
auto[1]	zero_access	660625	1			T1	11517		T2	610		T3	48