Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13929654	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

58559524

1

T1

48

T3

32968

T5

18432

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36138867	1			T1	400		T3	90820		T5	9216
values[0x0]	16782739	1			T1	188		T3	30355		T5	4623
values[0x1]	19567572	1			T1	431		T3	59936		T5	4593

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6938140	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

65551038

1

T1

457

T3

107402

T5

18432

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	286823	1			T1	6		T3	686		T5	45
valid_sources[0x01]	253853	1			T1	5		T3	724		T5	76
valid_sources[0x02]	260898	1			T3	715		T5	73		T4	36
valid_sources[0x03]	311000	1			T3	717		T5	60		T4	3
valid_sources[0x04]	282740	1			T3	757		T5	88		T4	7
valid_sources[0x05]	355727	1			T3	691		T5	70		T4	41
valid_sources[0x06]	259496	1			T1	9		T3	703		T5	43
valid_sources[0x07]	263765	1			T3	691		T5	66		T4	7
valid_sources[0x08]	272323	1			T3	708		T5	63		T4	26
valid_sources[0x09]	264968	1			T3	714		T5	59		T4	18
valid_sources[0x0a]	299270	1			T3	719		T5	60		T4	19
valid_sources[0x0b]	263368	1			T1	1		T3	765		T5	82
valid_sources[0x0c]	267879	1			T1	4		T3	743		T5	67
valid_sources[0x0d]	299238	1			T1	1		T3	706		T5	111
valid_sources[0x0e]	252662	1			T1	2		T3	705		T5	62
valid_sources[0x0f]	278451	1			T3	689		T5	65		T4	13
valid_sources[0x10]	267114	1			T3	725		T5	65		T4	8
valid_sources[0x11]	285233	1			T3	736		T5	62		T4	11
valid_sources[0x12]	297603	1			T3	740		T5	95		T4	30
valid_sources[0x13]	284781	1			T3	746		T5	81		T4	28
valid_sources[0x14]	254483	1			T1	1		T3	726		T5	64
valid_sources[0x15]	265723	1			T1	19		T3	703		T5	74
valid_sources[0x16]	250415	1			T3	699		T5	81		T4	37
valid_sources[0x17]	277264	1			T1	6		T3	691		T5	74
valid_sources[0x18]	280914	1			T3	736		T5	56		T4	30
valid_sources[0x19]	303872	1			T1	12		T3	666		T5	90
valid_sources[0x1a]	249204	1			T3	640		T5	70		T4	7
valid_sources[0x1b]	310834	1			T1	12		T3	721		T5	62
valid_sources[0x1c]	283189	1			T1	7		T3	674		T5	69
valid_sources[0x1d]	276927	1			T1	27		T3	673		T5	64
valid_sources[0x1e]	269882	1			T3	738		T5	91		T4	31
valid_sources[0x1f]	275064	1			T1	3		T3	726		T5	88
valid_sources[0x20]	260860	1			T3	677		T5	81		T4	4
valid_sources[0x21]	283293	1			T1	1		T3	674		T5	54
valid_sources[0x22]	277059	1			T1	1		T3	743		T5	88
valid_sources[0x23]	250530	1			T1	7		T3	716		T5	56
valid_sources[0x24]	289284	1			T3	707		T5	58		T4	30
valid_sources[0x25]	261846	1			T3	686		T5	74		T4	40
valid_sources[0x26]	318377	1			T1	3		T3	665		T5	80
valid_sources[0x27]	270686	1			T1	3		T3	716		T5	81
valid_sources[0x28]	291718	1			T3	704		T5	73		T4	45
valid_sources[0x29]	378986	1			T1	5		T3	685		T5	69
valid_sources[0x2a]	284405	1			T1	7		T3	711		T5	68
valid_sources[0x2b]	252826	1			T1	1		T3	679		T5	86
valid_sources[0x2c]	285660	1			T1	23		T3	679		T5	78
valid_sources[0x2d]	261386	1			T1	6		T3	686		T5	82
valid_sources[0x2e]	257097	1			T1	11		T3	679		T5	81
valid_sources[0x2f]	283344	1			T1	2		T3	741		T5	59
valid_sources[0x30]	259575	1			T1	1		T3	705		T5	68
valid_sources[0x31]	261304	1			T3	743		T5	60		T4	19
valid_sources[0x32]	369899	1			T3	670		T5	109		T4	23
valid_sources[0x33]	290068	1			T1	16		T3	720		T5	65
valid_sources[0x34]	262807	1			T1	33		T3	738		T5	72
valid_sources[0x35]	272719	1			T3	706		T5	83		T4	10
valid_sources[0x36]	249917	1			T1	3		T3	716		T5	54
valid_sources[0x37]	250403	1			T3	687		T5	64		T4	52
valid_sources[0x38]	272652	1			T1	1		T3	722		T5	55
valid_sources[0x39]	254279	1			T1	10		T3	738		T5	45
valid_sources[0x3a]	290663	1			T3	703		T5	65		T4	23
valid_sources[0x3b]	269228	1			T3	703		T5	86		T4	46
valid_sources[0x3c]	289419	1			T1	14		T3	682		T5	71
valid_sources[0x3d]	258020	1			T3	718		T5	75		T4	17
valid_sources[0x3e]	262534	1			T3	661		T5	48		T4	20
valid_sources[0x3f]	304638	1			T1	1		T3	706		T5	47
valid_sources[0x40]	252455	1			T3	682		T5	87		T4	32
valid_sources[0x41]	288436	1			T1	15		T3	728		T5	84
valid_sources[0x42]	254347	1			T1	11		T3	694		T5	57
valid_sources[0x43]	278352	1			T1	3		T3	715		T5	69
valid_sources[0x44]	257336	1			T1	2		T3	685		T5	80
valid_sources[0x45]	307743	1			T3	688		T5	67		T4	16
valid_sources[0x46]	265277	1			T1	3		T3	651		T5	59
valid_sources[0x47]	279690	1			T1	3		T3	745		T5	72
valid_sources[0x48]	286614	1			T1	10		T3	685		T5	92
valid_sources[0x49]	297182	1			T1	1		T3	716		T5	66
valid_sources[0x4a]	276357	1			T1	2		T3	710		T5	66
valid_sources[0x4b]	296438	1			T1	1		T3	678		T5	84
valid_sources[0x4c]	275846	1			T3	783		T5	62		T4	5
valid_sources[0x4d]	293846	1			T3	749		T5	96		T4	19
valid_sources[0x4e]	275180	1			T3	676		T5	53		T4	23
valid_sources[0x4f]	320162	1			T1	9		T3	720		T5	63
valid_sources[0x50]	288642	1			T3	716		T5	94		T4	10
valid_sources[0x51]	278340	1			T1	14		T3	705		T5	73
valid_sources[0x52]	323845	1			T3	797		T5	81		T4	79
valid_sources[0x53]	260776	1			T1	16		T3	738		T5	66
valid_sources[0x54]	256623	1			T3	670		T5	88		T4	38
valid_sources[0x55]	277143	1			T1	11		T3	710		T5	84
valid_sources[0x56]	262222	1			T1	4		T3	652		T5	69
valid_sources[0x57]	268864	1			T3	729		T5	69		T4	10
valid_sources[0x58]	293818	1			T3	733		T5	63		T4	13
valid_sources[0x59]	356101	1			T3	703		T5	78		T4	36
valid_sources[0x5a]	259374	1			T1	1		T3	707		T5	92
valid_sources[0x5b]	343524	1			T1	2		T3	705		T5	62
valid_sources[0x5c]	336220	1			T3	753		T5	47		T4	4
valid_sources[0x5d]	287721	1			T1	10		T3	724		T5	74
valid_sources[0x5e]	312114	1			T1	10		T3	711		T5	71
valid_sources[0x5f]	293757	1			T3	750		T5	67		T4	22
valid_sources[0x60]	277969	1			T3	759		T5	41		T4	41
valid_sources[0x61]	292928	1			T3	714		T5	63		T4	18
valid_sources[0x62]	251122	1			T1	2		T3	725		T5	85
valid_sources[0x63]	317621	1			T3	710		T5	103		T4	50
valid_sources[0x64]	279985	1			T1	5		T3	697		T5	72
valid_sources[0x65]	297339	1			T3	720		T5	117		T4	6
valid_sources[0x66]	262945	1			T3	690		T5	78		T4	40
valid_sources[0x67]	290275	1			T3	739		T5	58		T4	25
valid_sources[0x68]	302593	1			T3	668		T5	84		T4	16
valid_sources[0x69]	253303	1			T3	701		T5	73		T4	8
valid_sources[0x6a]	271079	1			T3	728		T5	74		T4	24
valid_sources[0x6b]	266178	1			T3	708		T5	53		T4	27
valid_sources[0x6c]	265915	1			T3	719		T5	68		T4	71
valid_sources[0x6d]	330780	1			T1	1		T3	637		T5	78
valid_sources[0x6e]	258786	1			T1	6		T3	680		T5	82
valid_sources[0x6f]	256825	1			T3	675		T5	75		T4	13
valid_sources[0x70]	274750	1			T1	15		T3	751		T5	71
valid_sources[0x71]	249349	1			T3	722		T5	63		T6	69
valid_sources[0x72]	279074	1			T3	681		T5	81		T4	27
valid_sources[0x73]	258808	1			T1	1		T3	720		T5	86
valid_sources[0x74]	253938	1			T1	2		T3	673		T5	68
valid_sources[0x75]	310765	1			T3	730		T5	77		T4	18
valid_sources[0x76]	271500	1			T1	4		T3	669		T5	43
valid_sources[0x77]	253108	1			T1	3		T3	737		T5	94
valid_sources[0x78]	297675	1			T3	744		T5	63		T4	54
valid_sources[0x79]	262359	1			T3	678		T5	82		T4	22
valid_sources[0x7a]	340343	1			T1	7		T3	726		T5	67
valid_sources[0x7b]	260978	1			T3	727		T5	86		T4	28
valid_sources[0x7c]	267299	1			T3	693		T5	65		T4	16
valid_sources[0x7d]	250723	1			T3	722		T5	69		T4	10
valid_sources[0x7e]	260290	1			T3	713		T5	54		T4	20
valid_sources[0x7f]	272717	1			T1	11		T3	714		T5	59
valid_sources[0x80]	256011	1			T3	701		T5	69		T4	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29178211

1

T1

3

T3

16461

T5

9216

values[0x0]

all_enables

biggest_size

14693039

1

T1

20

T3

8208

T5

4623

values[0x1]

all_enables

biggest_size

14688274

1

T1

25

T3

8299

T5

4593

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35797	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

125564

1

T2

2

T3

1

T5

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	47627	1			T10	17		T11	297		T7	19
values[0x0]	55011	1			T1	1		T2	4		T3	4
values[0x1]	58723	1			T1	2		T2	7		T5	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27415	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

133946

1

T2

2

T3

1

T5

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	578	1			T11	5		T21	4		T72	1
valid_sources[0x01]	582	1			T11	4		T8	1		T21	1
valid_sources[0x02]	698	1			T11	2		T8	1		T21	6
valid_sources[0x03]	844	1			T11	4		T7	2		T8	1
valid_sources[0x04]	589	1			T11	2		T7	1		T9	1
valid_sources[0x05]	646	1			T8	1		T21	1		T18	1
valid_sources[0x06]	577	1			T11	7		T8	1		T21	1
valid_sources[0x07]	566	1			T11	11		T21	3		T19	1
valid_sources[0x08]	1009	1			T11	2		T8	1		T13	16
valid_sources[0x09]	660	1			T11	1		T38	4		T22	14
valid_sources[0x0a]	368	1			T11	5		T8	2		T21	6
valid_sources[0x0b]	581	1			T11	5		T21	3		T9	2
valid_sources[0x0c]	601	1			T11	6		T21	10		T67	5
valid_sources[0x0d]	720	1			T8	3		T66	3		T50	19
valid_sources[0x0e]	787	1			T11	1		T21	1		T22	98
valid_sources[0x0f]	807	1			T11	4		T21	3		T9	1
valid_sources[0x10]	641	1			T11	1		T21	11		T9	2
valid_sources[0x11]	760	1			T11	5		T8	1		T21	2
valid_sources[0x12]	568	1			T11	6		T22	8		T67	3
valid_sources[0x13]	454	1			T11	4		T8	1		T22	3
valid_sources[0x14]	598	1			T11	2		T8	1		T9	1
valid_sources[0x15]	858	1			T11	2		T18	1		T67	1
valid_sources[0x16]	590	1			T11	6		T7	1		T21	18
valid_sources[0x17]	600	1			T11	3		T7	1		T8	1
valid_sources[0x18]	479	1			T11	1		T8	1		T72	1
valid_sources[0x19]	626	1			T11	4		T8	2		T21	11
valid_sources[0x1a]	755	1			T11	2		T8	1		T54	1
valid_sources[0x1b]	494	1			T11	4		T8	1		T21	14
valid_sources[0x1c]	627	1			T5	1		T11	6		T8	1
valid_sources[0x1d]	482	1			T11	5		T22	1		T72	1
valid_sources[0x1e]	427	1			T11	2		T21	1		T18	2
valid_sources[0x1f]	754	1			T5	1		T11	5		T21	1
valid_sources[0x20]	949	1			T11	1		T8	1		T21	6
valid_sources[0x21]	671	1			T11	2		T21	4		T17	4
valid_sources[0x22]	486	1			T11	3		T8	1		T21	1
valid_sources[0x23]	577	1			T3	1		T11	9		T8	2
valid_sources[0x24]	692	1			T11	3		T21	7		T45	1
valid_sources[0x25]	622	1			T11	5		T21	3		T133	1
valid_sources[0x26]	835	1			T11	6		T21	3		T18	1
valid_sources[0x27]	550	1			T11	4		T8	2		T21	1
valid_sources[0x28]	552	1			T11	4		T8	1		T21	3
valid_sources[0x29]	979	1			T11	6		T21	1		T18	1
valid_sources[0x2a]	522	1			T11	2		T7	1		T8	1
valid_sources[0x2b]	466	1			T11	3		T7	1		T8	2
valid_sources[0x2c]	480	1			T11	4		T21	7		T18	1
valid_sources[0x2d]	687	1			T11	3		T8	1		T21	1
valid_sources[0x2e]	665	1			T11	7		T8	1		T21	6
valid_sources[0x2f]	506	1			T11	2		T8	1		T22	4
valid_sources[0x30]	839	1			T5	1		T11	3		T7	1
valid_sources[0x31]	752	1			T11	3		T8	1		T21	5
valid_sources[0x32]	594	1			T11	2		T8	2		T21	1
valid_sources[0x33]	659	1			T11	7		T7	1		T21	2
valid_sources[0x34]	567	1			T11	3		T21	4		T54	1
valid_sources[0x35]	759	1			T11	8		T21	4		T133	1
valid_sources[0x36]	778	1			T11	5		T7	1		T22	1
valid_sources[0x37]	767	1			T11	2		T21	10		T72	3
valid_sources[0x38]	534	1			T11	4		T21	2		T67	1
valid_sources[0x39]	555	1			T11	3		T8	6		T21	4
valid_sources[0x3a]	475	1			T11	2		T8	2		T21	1
valid_sources[0x3b]	588	1			T11	3		T7	2		T8	1
valid_sources[0x3c]	1068	1			T11	3		T21	4		T9	7
valid_sources[0x3d]	477	1			T5	1		T11	2		T8	1
valid_sources[0x3e]	777	1			T11	3		T21	4		T9	12
valid_sources[0x3f]	600	1			T3	1		T11	3		T8	1
valid_sources[0x40]	705	1			T11	12		T8	3		T21	2
valid_sources[0x41]	647	1			T11	7		T66	2		T33	1
valid_sources[0x42]	857	1			T11	1		T21	2		T54	2
valid_sources[0x43]	647	1			T11	11		T21	3		T18	1
valid_sources[0x44]	518	1			T11	7		T8	2		T21	9
valid_sources[0x45]	616	1			T11	1		T8	1		T21	1
valid_sources[0x46]	758	1			T11	2		T21	3		T19	1
valid_sources[0x47]	493	1			T11	4		T7	1		T8	1
valid_sources[0x48]	466	1			T11	1		T7	1		T8	1
valid_sources[0x49]	472	1			T1	3		T11	2		T8	1
valid_sources[0x4a]	953	1			T11	1		T8	3		T21	9
valid_sources[0x4b]	689	1			T11	3		T8	1		T21	3
valid_sources[0x4c]	565	1			T11	1		T8	1		T18	1
valid_sources[0x4d]	647	1			T11	3		T21	5		T22	5
valid_sources[0x4e]	965	1			T11	11		T8	2		T22	130
valid_sources[0x4f]	510	1			T3	1		T11	7		T21	1
valid_sources[0x50]	509	1			T11	7		T21	8		T134	2
valid_sources[0x51]	697	1			T11	4		T21	1		T18	1
valid_sources[0x52]	606	1			T11	4		T21	4		T22	6
valid_sources[0x53]	783	1			T11	2		T21	15		T54	1
valid_sources[0x54]	559	1			T11	2		T8	4		T18	2
valid_sources[0x55]	565	1			T11	3		T21	12		T18	1
valid_sources[0x56]	432	1			T11	3		T8	1		T9	1
valid_sources[0x57]	419	1			T11	3		T7	1		T18	1
valid_sources[0x58]	484	1			T11	5		T7	1		T21	6
valid_sources[0x59]	503	1			T11	4		T54	1		T130	2
valid_sources[0x5a]	586	1			T11	5		T21	11		T18	1
valid_sources[0x5b]	840	1			T11	3		T21	1		T19	7
valid_sources[0x5c]	548	1			T11	5		T8	1		T21	3
valid_sources[0x5d]	464	1			T11	5		T8	1		T21	3
valid_sources[0x5e]	716	1			T11	5		T8	1		T24	1
valid_sources[0x5f]	517	1			T11	5		T19	1		T72	1
valid_sources[0x60]	624	1			T11	1		T21	1		T19	4
valid_sources[0x61]	514	1			T11	3		T8	3		T21	5
valid_sources[0x62]	571	1			T11	5		T8	1		T21	6
valid_sources[0x63]	743	1			T4	1		T11	3		T8	1
valid_sources[0x64]	863	1			T11	3		T8	5		T21	2
valid_sources[0x65]	412	1			T11	2		T8	3		T21	3
valid_sources[0x66]	572	1			T11	5		T7	1		T21	1
valid_sources[0x67]	729	1			T11	8		T8	1		T54	1
valid_sources[0x68]	474	1			T11	5		T18	1		T66	5
valid_sources[0x69]	694	1			T11	3		T8	1		T21	5
valid_sources[0x6a]	656	1			T11	5		T22	104		T66	4
valid_sources[0x6b]	602	1			T11	5		T8	1		T21	1
valid_sources[0x6c]	725	1			T11	6		T8	1		T21	1
valid_sources[0x6d]	419	1			T11	3		T8	1		T21	4
valid_sources[0x6e]	769	1			T11	4		T22	3		T72	1
valid_sources[0x6f]	469	1			T11	2		T21	3		T45	2
valid_sources[0x70]	550	1			T11	3		T9	2		T135	5
valid_sources[0x71]	469	1			T5	1		T11	7		T40	5
valid_sources[0x72]	451	1			T11	5		T8	1		T133	1
valid_sources[0x73]	671	1			T11	3		T21	3		T22	28
valid_sources[0x74]	559	1			T11	6		T54	1		T135	1
valid_sources[0x75]	808	1			T11	4		T7	1		T8	1
valid_sources[0x76]	690	1			T11	3		T8	1		T21	8
valid_sources[0x77]	545	1			T11	5		T8	1		T21	1
valid_sources[0x78]	569	1			T11	6		T22	25		T72	1
valid_sources[0x79]	794	1			T11	2		T8	1		T21	1
valid_sources[0x7a]	600	1			T11	8		T8	1		T21	1
valid_sources[0x7b]	949	1			T11	5		T8	1		T21	5
valid_sources[0x7c]	472	1			T11	4		T8	1		T21	1
valid_sources[0x7d]	965	1			T11	5		T8	1		T21	3
valid_sources[0x7e]	635	1			T10	78		T11	8		T8	2
valid_sources[0x7f]	490	1			T11	5		T8	2		T21	3
valid_sources[0x80]	520	1			T11	6		T54	1		T72	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

35166

1

T10

9

T11

265

T7

9

values[0x0]

all_enables

biggest_size

46250

1

T3

1

T5

1

T6

2

values[0x1]

all_enables

biggest_size

44148

1

T2

2

T5

1

T6

2