Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13587609

1

T1

971

T3

148143

T4

930

full_word

53436328

1

T1

48

T3

32968

T5

18432

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	67023647	1			T1	1019		T3	181111		T5	18432
auto[TlIntgErrCmd]	99	1			T60	2		T61	8		T62	8
auto[TlIntgErrData]	102	1			T60	6		T61	2		T62	7
auto[TlIntgErrBoth]	89	1			T60	2		T62	5		T116	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30630395

1

T1

400

T3

90820

T5

9216

auto[1]

36393542

1

T1

619

T3

90291

T5

9216

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6490893	1			T1	397		T3	74359		T4	476
auto[TlIntgErrNone]	partial	auto[1]	7096455	1			T1	574		T3	73784		T4	454
auto[TlIntgErrNone]	full_word	auto[0]	24139370	1			T1	3		T3	16461		T5	9216
auto[TlIntgErrNone]	full_word	auto[1]	29296929	1			T1	45		T3	16507		T5	9216
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T61	7		T62	4		T115	2
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T60	2		T61	1		T62	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T122	1		T123	1		T125	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T62	1		T116	1		T115	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T60	3		T61	1		T62	4
auto[TlIntgErrData]	partial	auto[1]	47	1			T60	3		T61	1		T62	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T117	1		T126	1		T127	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T116	1		T117	2		T118	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T60	1		T62	2		T116	2
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T62	3		T116	1		T115	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T116	1		T118	1		T128	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T60	1		T129	1		T123	2