Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	649926	1			T1	28		T3	3652		T10	1878
auto[1]	10651869	1			T1	65		T3	11895		T4	2562
auto[2]	534552	1			T1	21		T3	2790		T10	1700
auto[3]	10549359	1			T1	112		T3	10845		T4	2498

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14036151	1			T3	458		T4	3359		T10	3299
auto[1]	2185610	1			T1	1		T3	2969		T4	771
auto[2]	2192398	1			T1	10		T3	3897		T4	757
auto[3]	3971547	1			T1	215		T3	21858		T4	173

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8396191

1

T1

226

T4

5058

T10

4281

auto[1]

13989515

1

T3

29182

T4

2

T10

5

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	248769	1			T10	1548		T11	9		T39	256
auto[0]	auto[0]	auto[1]	25580	1			T10	157		T11	2		T39	29
auto[0]	auto[0]	auto[2]	25492	1			T10	159		T11	1		T39	26
auto[0]	auto[0]	auto[3]	6748	1			T1	28		T10	11		T39	5
auto[0]	auto[1]	auto[0]	3184677	1			T4	1685		T10	239		T11	58
auto[0]	auto[1]	auto[1]	333215	1			T1	1		T4	399		T10	170
auto[0]	auto[1]	auto[2]	326245	1			T1	3		T4	386		T10	18
auto[0]	auto[1]	auto[3]	82460	1			T1	61		T4	90		T10	18
auto[0]	auto[2]	auto[0]	216426	1			T10	1399		T67	2115		T113	38
auto[0]	auto[2]	auto[1]	22010	1			T10	149		T37	21		T67	209
auto[0]	auto[2]	auto[2]	23402	1			T10	140		T11	5		T39	150
auto[0]	auto[2]	auto[3]	5564	1			T1	21		T10	11		T11	1
auto[0]	auto[3]	auto[0]	3154765	1			T4	1673		T10	109		T11	52
auto[0]	auto[3]	auto[1]	323419	1			T4	371		T10	13		T11	7
auto[0]	auto[3]	auto[2]	332922	1			T1	7		T4	371		T10	131
auto[0]	auto[3]	auto[3]	84497	1			T1	105		T4	83		T10	9
auto[1]	auto[0]	auto[0]	11407	1			T3	140		T10	2		T39	2
auto[1]	auto[0]	auto[1]	51267	1			T3	546		T10	1		T38	5436
auto[1]	auto[0]	auto[2]	50932	1			T3	523		T38	5519		T130	2
auto[1]	auto[0]	auto[3]	229731	1			T3	2443		T37	1		T38	24973
auto[1]	auto[1]	auto[0]	3606636	1			T3	211		T4	1		T8	63
auto[1]	auto[1]	auto[1]	705395	1			T3	1946		T4	1		T8	4
auto[1]	auto[1]	auto[2]	698400	1			T3	1066		T8	4		T40	12179
auto[1]	auto[1]	auto[3]	1714841	1			T3	8672		T40	54677		T55	494
auto[1]	auto[2]	auto[0]	8893	1			T10	1		T38	1171		T67	2
auto[1]	auto[2]	auto[1]	39260	1			T38	5272		T130	1		T131	1
auto[1]	auto[2]	auto[2]	39897	1			T3	492		T38	3625		T67	1
auto[1]	auto[2]	auto[3]	179100	1			T3	2298		T38	16677		T113	2
auto[1]	auto[3]	auto[0]	3604578	1			T3	107		T10	1		T8	55
auto[1]	auto[3]	auto[1]	685464	1			T3	477		T8	9		T21	1
auto[1]	auto[3]	auto[2]	695108	1			T3	1816		T8	3		T39	1
auto[1]	auto[3]	auto[3]	1668606	1			T3	8445		T40	54226		T55	463