Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	304199067	185180	0	0
ctrl_regwen_rd_A	304199067	4127	0	0
exec_rd_A	304199067	4251	0	0
exec_regwen_rd_A	304199067	4453	0	0
readback_rd_A	304199067	2873	0	0
readback_regwen_rd_A	304199067	2461	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304199067	185180	0	0
T7	30563	0	0	0
T8	109322	0	0	0
T11	45195	1579	0	0
T12	1051	0	0	0
T21	28417	1950	0	0
T22	0	3257	0	0
T37	16743	0	0	0
T39	128605	0	0	0
T40	373822	0	0	0
T46	0	3164	0	0
T50	0	5287	0	0
T54	346677	0	0	0
T55	185413	0	0	0
T57	0	6528	0	0
T66	0	1182	0	0
T68	0	1380	0	0
T69	0	1812	0	0
T70	0	1460	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304199067	4127	0	0
T19	503489	0	0	0
T22	96494	233	0	0
T46	0	109	0	0
T48	0	55	0	0
T52	22800	0	0	0
T66	0	91	0	0
T67	264407	0	0	0
T68	0	84	0	0
T70	0	141	0	0
T71	142612	0	0	0
T103	477909	0	0	0
T104	339961	0	0	0
T105	232167	0	0	0
T108	0	150	0	0
T109	0	508	0	0
T110	0	450	0	0
T111	0	245	0	0
T112	81509	0	0	0
T113	73938	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304199067	4251	0	0
T19	503489	0	0	0
T22	96494	257	0	0
T46	0	133	0	0
T48	0	153	0	0
T52	22800	0	0	0
T66	0	95	0	0
T67	264407	0	0	0
T68	0	64	0	0
T70	0	92	0	0
T71	142612	0	0	0
T103	477909	0	0	0
T104	339961	0	0	0
T105	232167	0	0	0
T108	0	227	0	0
T109	0	486	0	0
T110	0	477	0	0
T111	0	306	0	0
T112	81509	0	0	0
T113	73938	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304199067	4453	0	0
T19	503489	0	0	0
T22	96494	245	0	0
T46	0	99	0	0
T48	0	94	0	0
T52	22800	0	0	0
T66	0	131	0	0
T67	264407	0	0	0
T68	0	126	0	0
T70	0	164	0	0
T71	142612	0	0	0
T103	477909	0	0	0
T104	339961	0	0	0
T105	232167	0	0	0
T108	0	176	0	0
T109	0	476	0	0
T110	0	471	0	0
T111	0	230	0	0
T112	81509	0	0	0
T113	73938	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304199067	2873	0	0
T19	503489	0	0	0
T22	96494	146	0	0
T46	0	142	0	0
T48	0	108	0	0
T52	22800	0	0	0
T66	0	74	0	0
T67	264407	0	0	0
T68	0	69	0	0
T70	0	158	0	0
T71	142612	0	0	0
T103	477909	0	0	0
T104	339961	0	0	0
T105	232167	0	0	0
T108	0	137	0	0
T109	0	427	0	0
T110	0	452	0	0
T111	0	296	0	0
T112	81509	0	0	0
T113	73938	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304199067	2461	0	0
T19	503489	0	0	0
T22	96494	216	0	0
T46	0	100	0	0
T48	0	49	0	0
T52	22800	0	0	0
T66	0	78	0	0
T67	264407	0	0	0
T68	0	65	0	0
T70	0	101	0	0
T71	142612	0	0	0
T103	477909	0	0	0
T104	339961	0	0	0
T105	232167	0	0	0
T108	0	143	0	0
T109	0	401	0	0
T110	0	356	0	0
T111	0	280	0	0
T112	81509	0	0	0
T113	73938	0	0	0