Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13813220	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

61163047

1

T1

119084

T2

143555

T3

6142

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37374347	1			T1	65147		T2	78995		T3	2048
values[0x0]	17421638	1			T1	31779		T2	38032		T3	2050
values[0x1]	20180282	1			T1	33956		T2	40864		T3	2044

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6882982	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

68093285

1

T1

125095

T2

150804

T3

6142

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	278657	1			T1	520		T2	534		T3	17
valid_sources[0x01]	300550	1			T1	486		T2	451		T3	22
valid_sources[0x02]	281577	1			T1	471		T2	645		T3	28
valid_sources[0x03]	277403	1			T1	530		T2	702		T3	29
valid_sources[0x04]	271216	1			T1	518		T2	648		T3	25
valid_sources[0x05]	280501	1			T1	564		T2	650		T3	22
valid_sources[0x06]	260520	1			T1	593		T2	428		T3	16
valid_sources[0x07]	262010	1			T1	535		T2	644		T3	17
valid_sources[0x08]	269226	1			T1	416		T2	362		T3	21
valid_sources[0x09]	301405	1			T1	485		T2	634		T3	27
valid_sources[0x0a]	350595	1			T1	536		T2	746		T3	15
valid_sources[0x0b]	290728	1			T1	504		T2	373		T3	27
valid_sources[0x0c]	310196	1			T1	420		T2	356		T3	25
valid_sources[0x0d]	281361	1			T1	569		T2	676		T3	22
valid_sources[0x0e]	285444	1			T1	471		T2	510		T3	19
valid_sources[0x0f]	313912	1			T1	540		T2	578		T3	15
valid_sources[0x10]	277981	1			T1	542		T2	565		T3	33
valid_sources[0x11]	284765	1			T1	528		T2	620		T3	19
valid_sources[0x12]	304103	1			T1	477		T2	619		T3	24
valid_sources[0x13]	263701	1			T1	496		T2	318		T3	24
valid_sources[0x14]	282739	1			T1	499		T2	866		T3	12
valid_sources[0x15]	270876	1			T1	510		T2	514		T3	35
valid_sources[0x16]	274720	1			T1	466		T2	876		T3	25
valid_sources[0x17]	284812	1			T1	563		T2	481		T3	20
valid_sources[0x18]	275744	1			T1	540		T2	589		T3	19
valid_sources[0x19]	286722	1			T1	511		T2	716		T3	24
valid_sources[0x1a]	292437	1			T1	451		T2	570		T3	26
valid_sources[0x1b]	316829	1			T1	536		T2	587		T3	13
valid_sources[0x1c]	269673	1			T1	450		T2	809		T3	19
valid_sources[0x1d]	260811	1			T1	508		T2	1003		T3	32
valid_sources[0x1e]	317366	1			T1	500		T2	428		T3	21
valid_sources[0x1f]	281304	1			T1	490		T2	841		T3	23
valid_sources[0x20]	280923	1			T1	551		T2	508		T3	28
valid_sources[0x21]	273124	1			T1	594		T2	748		T3	16
valid_sources[0x22]	289350	1			T1	571		T2	637		T3	33
valid_sources[0x23]	338929	1			T1	461		T2	645		T3	36
valid_sources[0x24]	266515	1			T1	438		T2	515		T3	32
valid_sources[0x25]	279681	1			T1	568		T2	548		T3	29
valid_sources[0x26]	292697	1			T1	505		T2	766		T3	26
valid_sources[0x27]	312298	1			T1	477		T2	348		T3	30
valid_sources[0x28]	341280	1			T1	503		T2	336		T3	24
valid_sources[0x29]	268448	1			T1	525		T2	845		T3	26
valid_sources[0x2a]	293337	1			T1	604		T2	812		T3	15
valid_sources[0x2b]	260401	1			T1	513		T2	527		T3	26
valid_sources[0x2c]	330686	1			T1	550		T2	634		T3	32
valid_sources[0x2d]	288522	1			T1	498		T2	532		T3	19
valid_sources[0x2e]	285131	1			T1	490		T2	679		T3	38
valid_sources[0x2f]	330289	1			T1	557		T2	603		T3	22
valid_sources[0x30]	287785	1			T1	479		T2	800		T3	27
valid_sources[0x31]	290746	1			T1	531		T2	535		T3	33
valid_sources[0x32]	334641	1			T1	530		T2	800		T3	27
valid_sources[0x33]	282204	1			T1	474		T2	917		T3	21
valid_sources[0x34]	267313	1			T1	523		T2	728		T3	19
valid_sources[0x35]	283069	1			T1	524		T2	927		T3	20
valid_sources[0x36]	259343	1			T1	573		T2	517		T3	25
valid_sources[0x37]	265735	1			T1	510		T2	702		T3	27
valid_sources[0x38]	272341	1			T1	510		T2	617		T3	18
valid_sources[0x39]	281763	1			T1	472		T2	674		T3	32
valid_sources[0x3a]	288395	1			T1	503		T2	658		T3	29
valid_sources[0x3b]	310185	1			T1	529		T2	663		T3	18
valid_sources[0x3c]	298539	1			T1	444		T2	534		T3	20
valid_sources[0x3d]	301093	1			T1	511		T2	550		T3	28
valid_sources[0x3e]	308098	1			T1	584		T2	597		T3	22
valid_sources[0x3f]	289414	1			T1	416		T2	882		T3	29
valid_sources[0x40]	290811	1			T1	562		T2	676		T3	27
valid_sources[0x41]	298308	1			T1	561		T2	595		T3	24
valid_sources[0x42]	320197	1			T1	564		T2	443		T3	27
valid_sources[0x43]	342565	1			T1	546		T2	808		T3	30
valid_sources[0x44]	290490	1			T1	554		T2	886		T3	24
valid_sources[0x45]	302958	1			T1	551		T2	413		T3	29
valid_sources[0x46]	288635	1			T1	491		T2	429		T3	29
valid_sources[0x47]	262109	1			T1	499		T2	440		T3	18
valid_sources[0x48]	305147	1			T1	562		T2	1018		T3	26
valid_sources[0x49]	292694	1			T1	548		T2	482		T3	21
valid_sources[0x4a]	304832	1			T1	472		T2	608		T3	29
valid_sources[0x4b]	265622	1			T1	513		T2	761		T3	29
valid_sources[0x4c]	262398	1			T1	531		T2	726		T3	22
valid_sources[0x4d]	265969	1			T1	530		T2	571		T3	14
valid_sources[0x4e]	325264	1			T1	521		T2	542		T3	28
valid_sources[0x4f]	290313	1			T1	505		T2	504		T3	16
valid_sources[0x50]	291534	1			T1	567		T2	540		T3	20
valid_sources[0x51]	265833	1			T1	532		T2	514		T3	20
valid_sources[0x52]	326930	1			T1	506		T2	471		T3	22
valid_sources[0x53]	288276	1			T1	529		T2	719		T3	15
valid_sources[0x54]	280596	1			T1	576		T2	1085		T3	19
valid_sources[0x55]	278791	1			T1	473		T2	605		T3	21
valid_sources[0x56]	322438	1			T1	494		T2	767		T3	23
valid_sources[0x57]	300682	1			T1	594		T2	577		T3	20
valid_sources[0x58]	263549	1			T1	545		T2	500		T3	35
valid_sources[0x59]	285786	1			T1	467		T2	677		T3	19
valid_sources[0x5a]	270497	1			T1	462		T2	998		T3	26
valid_sources[0x5b]	297055	1			T1	519		T2	509		T3	19
valid_sources[0x5c]	278739	1			T1	524		T2	537		T3	25
valid_sources[0x5d]	297435	1			T1	482		T2	783		T3	14
valid_sources[0x5e]	295343	1			T1	447		T2	593		T3	21
valid_sources[0x5f]	290394	1			T1	488		T2	632		T3	27
valid_sources[0x60]	279634	1			T1	542		T2	599		T3	21
valid_sources[0x61]	290947	1			T1	518		T2	765		T3	19
valid_sources[0x62]	298209	1			T1	508		T2	552		T3	21
valid_sources[0x63]	288575	1			T1	435		T2	399		T3	16
valid_sources[0x64]	293719	1			T1	460		T2	752		T3	20
valid_sources[0x65]	295826	1			T1	527		T2	439		T3	25
valid_sources[0x66]	280029	1			T1	555		T2	591		T3	26
valid_sources[0x67]	290373	1			T1	518		T2	480		T3	16
valid_sources[0x68]	270991	1			T1	543		T2	415		T3	29
valid_sources[0x69]	318496	1			T1	485		T2	573		T3	32
valid_sources[0x6a]	255303	1			T1	442		T2	631		T3	32
valid_sources[0x6b]	297282	1			T1	519		T2	535		T3	32
valid_sources[0x6c]	270245	1			T1	459		T2	675		T3	29
valid_sources[0x6d]	269815	1			T1	474		T2	433		T3	28
valid_sources[0x6e]	275113	1			T1	559		T2	615		T3	24
valid_sources[0x6f]	295755	1			T1	482		T2	470		T3	27
valid_sources[0x70]	329770	1			T1	525		T2	448		T3	20
valid_sources[0x71]	331763	1			T1	429		T2	579		T3	14
valid_sources[0x72]	315084	1			T1	451		T2	782		T3	25
valid_sources[0x73]	266195	1			T1	501		T2	569		T3	31
valid_sources[0x74]	268999	1			T1	448		T2	417		T3	26
valid_sources[0x75]	356271	1			T1	600		T2	451		T3	31
valid_sources[0x76]	299958	1			T1	528		T2	645		T3	22
valid_sources[0x77]	274126	1			T1	488		T2	352		T3	28
valid_sources[0x78]	324617	1			T1	482		T2	281		T3	39
valid_sources[0x79]	300383	1			T1	502		T2	689		T3	26
valid_sources[0x7a]	260484	1			T1	472		T2	614		T3	21
valid_sources[0x7b]	294235	1			T1	452		T2	584		T3	20
valid_sources[0x7c]	303021	1			T1	527		T2	577		T3	35
valid_sources[0x7d]	317051	1			T1	490		T2	587		T3	18
valid_sources[0x7e]	258624	1			T1	494		T2	694		T3	22
valid_sources[0x7f]	259743	1			T1	505		T2	797		T3	30
valid_sources[0x80]	294726	1			T1	529		T2	790		T3	22

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30474103

1

T1

59206

T2

71787

T3

2048

values[0x0]

all_enables

biggest_size

15347186

1

T1

30051

T2

35942

T3

2050

values[0x1]

all_enables

biggest_size

15341758

1

T1

29827

T2

35826

T3

2044

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37273	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

143965

1

T1

5

T2

26

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	52209	1			T2	15		T12	22		T23	643
values[0x0]	61565	1			T1	12		T2	35		T3	5
values[0x1]	67464	1			T1	13		T2	24		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28294	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

152944

1

T1

7

T2

30

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	662	1			T9	1		T23	17		T24	2
valid_sources[0x01]	704	1			T2	1		T9	1		T23	13
valid_sources[0x02]	905	1			T23	9		T24	1		T27	4
valid_sources[0x03]	586	1			T2	1		T23	13		T87	1
valid_sources[0x04]	582	1			T1	1		T23	4		T24	1
valid_sources[0x05]	922	1			T12	1		T23	15		T87	1
valid_sources[0x06]	712	1			T8	1		T23	14		T24	1
valid_sources[0x07]	718	1			T2	1		T12	1		T23	8
valid_sources[0x08]	510	1			T23	10		T24	1		T129	3
valid_sources[0x09]	813	1			T2	1		T23	4		T21	1
valid_sources[0x0a]	580	1			T12	1		T23	13		T15	2
valid_sources[0x0b]	602	1			T2	2		T12	1		T23	9
valid_sources[0x0c]	502	1			T23	10		T139	1		T136	2
valid_sources[0x0d]	771	1			T2	1		T23	7		T24	1
valid_sources[0x0e]	510	1			T10	2		T23	7		T129	1
valid_sources[0x0f]	1027	1			T23	8		T68	7		T86	13
valid_sources[0x10]	589	1			T9	1		T23	18		T21	1
valid_sources[0x11]	662	1			T9	1		T23	11		T24	2
valid_sources[0x12]	489	1			T23	8		T139	1		T136	2
valid_sources[0x13]	592	1			T2	1		T12	3		T23	9
valid_sources[0x14]	698	1			T23	9		T24	1		T67	4
valid_sources[0x15]	637	1			T23	11		T24	5		T43	1
valid_sources[0x16]	801	1			T9	1		T23	11		T24	1
valid_sources[0x17]	830	1			T8	1		T12	1		T23	8
valid_sources[0x18]	786	1			T12	1		T23	14		T24	1
valid_sources[0x19]	1124	1			T12	2		T23	18		T24	1
valid_sources[0x1a]	566	1			T23	10		T24	1		T21	1
valid_sources[0x1b]	878	1			T23	2		T24	1		T57	1
valid_sources[0x1c]	592	1			T23	9		T24	4		T57	1
valid_sources[0x1d]	882	1			T23	11		T24	1		T87	1
valid_sources[0x1e]	812	1			T12	1		T23	8		T24	5
valid_sources[0x1f]	757	1			T12	1		T23	8		T24	2
valid_sources[0x20]	591	1			T23	11		T24	4		T67	3
valid_sources[0x21]	622	1			T23	7		T57	1		T21	1
valid_sources[0x22]	782	1			T12	1		T23	8		T68	2
valid_sources[0x23]	552	1			T12	1		T23	7		T24	3
valid_sources[0x24]	713	1			T23	7		T24	1		T47	1
valid_sources[0x25]	645	1			T23	6		T24	1		T140	1
valid_sources[0x26]	663	1			T9	1		T13	7		T23	22
valid_sources[0x27]	1020	1			T12	1		T23	7		T24	1
valid_sources[0x28]	512	1			T23	11		T24	2		T27	27
valid_sources[0x29]	657	1			T23	4		T24	2		T43	1
valid_sources[0x2a]	729	1			T23	10		T24	2		T139	2
valid_sources[0x2b]	649	1			T2	1		T3	3		T12	1
valid_sources[0x2c]	708	1			T23	8		T24	2		T87	1
valid_sources[0x2d]	751	1			T2	4		T23	15		T24	1
valid_sources[0x2e]	729	1			T12	1		T23	11		T139	1
valid_sources[0x2f]	657	1			T2	2		T23	3		T24	1
valid_sources[0x30]	592	1			T23	8		T24	1		T67	17
valid_sources[0x31]	701	1			T23	11		T64	5		T141	1
valid_sources[0x32]	894	1			T23	16		T24	1		T136	1
valid_sources[0x33]	540	1			T12	1		T23	4		T43	1
valid_sources[0x34]	794	1			T1	1		T12	2		T23	9
valid_sources[0x35]	741	1			T1	1		T23	12		T24	2
valid_sources[0x36]	887	1			T12	1		T23	7		T7	4
valid_sources[0x37]	712	1			T12	2		T23	12		T24	2
valid_sources[0x38]	644	1			T2	2		T23	14		T20	2
valid_sources[0x39]	557	1			T23	11		T24	2		T139	1
valid_sources[0x3a]	559	1			T23	3		T24	2		T57	1
valid_sources[0x3b]	790	1			T23	8		T24	3		T140	1
valid_sources[0x3c]	833	1			T9	1		T12	1		T23	9
valid_sources[0x3d]	676	1			T12	1		T23	16		T24	1
valid_sources[0x3e]	528	1			T2	2		T23	11		T24	1
valid_sources[0x3f]	720	1			T23	8		T24	2		T139	1
valid_sources[0x40]	730	1			T23	4		T87	3		T136	1
valid_sources[0x41]	720	1			T23	6		T24	1		T67	3
valid_sources[0x42]	723	1			T23	3		T142	1		T143	1
valid_sources[0x43]	568	1			T23	6		T48	3		T27	5
valid_sources[0x44]	680	1			T2	1		T23	15		T99	1
valid_sources[0x45]	656	1			T2	1		T12	2		T23	11
valid_sources[0x46]	1030	1			T1	1		T23	9		T21	1
valid_sources[0x47]	729	1			T3	3		T23	8		T24	1
valid_sources[0x48]	531	1			T2	2		T23	13		T140	1
valid_sources[0x49]	643	1			T9	1		T12	1		T23	15
valid_sources[0x4a]	658	1			T2	2		T12	1		T23	6
valid_sources[0x4b]	606	1			T23	13		T136	1		T52	1
valid_sources[0x4c]	570	1			T23	9		T24	1		T136	1
valid_sources[0x4d]	524	1			T2	1		T23	10		T139	1
valid_sources[0x4e]	693	1			T12	2		T23	10		T68	1
valid_sources[0x4f]	783	1			T23	3		T68	4		T21	1
valid_sources[0x50]	653	1			T1	1		T12	1		T23	11
valid_sources[0x51]	610	1			T23	7		T24	1		T139	1
valid_sources[0x52]	578	1			T23	13		T24	3		T138	1
valid_sources[0x53]	726	1			T23	9		T7	1		T130	4
valid_sources[0x54]	654	1			T9	1		T23	10		T24	1
valid_sources[0x55]	721	1			T8	1		T23	10		T130	1
valid_sources[0x56]	657	1			T1	1		T9	1		T23	11
valid_sources[0x57]	779	1			T23	6		T24	1		T126	2
valid_sources[0x58]	528	1			T23	8		T57	1		T139	1
valid_sources[0x59]	766	1			T2	1		T3	3		T9	1
valid_sources[0x5a]	1124	1			T23	15		T24	2		T139	2
valid_sources[0x5b]	799	1			T23	6		T24	2		T139	1
valid_sources[0x5c]	557	1			T12	2		T23	9		T137	1
valid_sources[0x5d]	664	1			T1	1		T12	1		T23	18
valid_sources[0x5e]	740	1			T8	1		T23	8		T140	1
valid_sources[0x5f]	537	1			T2	1		T12	2		T23	13
valid_sources[0x60]	636	1			T12	1		T23	6		T24	1
valid_sources[0x61]	785	1			T23	7		T139	1		T138	1
valid_sources[0x62]	670	1			T23	14		T24	2		T139	1
valid_sources[0x63]	604	1			T23	12		T24	5		T57	1
valid_sources[0x64]	685	1			T23	10		T24	1		T140	2
valid_sources[0x65]	800	1			T23	9		T24	1		T136	3
valid_sources[0x66]	747	1			T1	1		T12	2		T23	13
valid_sources[0x67]	598	1			T12	1		T23	10		T136	1
valid_sources[0x68]	617	1			T23	10		T25	1		T24	1
valid_sources[0x69]	552	1			T2	1		T9	1		T23	4
valid_sources[0x6a]	643	1			T12	1		T23	10		T24	1
valid_sources[0x6b]	949	1			T23	4		T24	2		T52	5
valid_sources[0x6c]	563	1			T1	1		T2	1		T12	1
valid_sources[0x6d]	552	1			T23	6		T24	1		T139	1
valid_sources[0x6e]	768	1			T9	1		T23	13		T126	1
valid_sources[0x6f]	679	1			T12	1		T23	11		T57	1
valid_sources[0x70]	1299	1			T2	1		T23	7		T140	1
valid_sources[0x71]	727	1			T23	4		T141	1		T100	1
valid_sources[0x72]	689	1			T2	2		T23	10		T139	1
valid_sources[0x73]	543	1			T8	1		T23	6		T47	1
valid_sources[0x74]	843	1			T8	3		T12	1		T23	12
valid_sources[0x75]	769	1			T12	1		T23	5		T24	1
valid_sources[0x76]	540	1			T12	1		T23	4		T24	1
valid_sources[0x77]	616	1			T23	7		T24	3		T21	1
valid_sources[0x78]	730	1			T23	6		T57	1		T139	1
valid_sources[0x79]	611	1			T23	9		T24	2		T67	6
valid_sources[0x7a]	701	1			T1	1		T23	13		T67	6
valid_sources[0x7b]	631	1			T23	19		T14	3		T67	3
valid_sources[0x7c]	989	1			T23	10		T139	1		T66	12
valid_sources[0x7d]	541	1			T23	8		T24	1		T139	1
valid_sources[0x7e]	555	1			T12	2		T23	17		T24	1
valid_sources[0x7f]	729	1			T23	7		T24	1		T139	1
valid_sources[0x80]	477	1			T2	1		T8	1		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

39475

1

T2

8

T12

11

T23

589

values[0x0]

all_enables

biggest_size

52779

1

T1

3

T2

14

T3

1

values[0x1]

all_enables

biggest_size

51711

1

T1

2

T2

4

T3

1