Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13482599

1

T1

11798

T2

11494

T4

24770

full_word

55912325

1

T1

119084

T2

115047

T3

6142

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69394624	1			T1	130882		T2	126541		T3	6142
auto[TlIntgErrCmd]	111	1			T61	5		T62	3		T63	12
auto[TlIntgErrData]	97	1			T61	6		T62	1		T63	4
auto[TlIntgErrBoth]	92	1			T61	9		T62	6		T63	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31731774

1

T1

65147

T2

47645

T3

2048

auto[1]

37663150

1

T1

65735

T2

78896

T3

4094

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6423051	1			T1	5941		T2	4366		T4	12423
auto[TlIntgErrNone]	partial	auto[1]	7059266	1			T1	5857		T2	7128		T4	12347
auto[TlIntgErrNone]	full_word	auto[0]	25308581	1			T1	59206		T2	43279		T3	2048
auto[TlIntgErrNone]	full_word	auto[1]	30603726	1			T1	59878		T2	71768		T3	4094
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T61	3		T62	2		T63	2
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T61	2		T62	1		T63	8
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T118	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T63	2		T111	2		T119	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T61	4		T62	1		T63	1
auto[TlIntgErrData]	partial	auto[1]	41	1			T61	2		T63	3		T115	2
auto[TlIntgErrData]	full_word	auto[0]	1	1			T113	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1			T120	1		T121	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T61	2		T62	1		T63	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T61	6		T62	3		T63	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T62	1		T116	1		T122	2
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T61	1		T62	1		T116	1