Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	639873	1			T2	26		T23	2		T24	903
auto[1]	10356112	1			T1	49895		T2	405		T4	114075
auto[2]	542985	1			T2	33		T23	7		T24	469
auto[3]	10265337	1			T1	50398		T2	388		T4	114489

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14015805	1			T1	83143		T2	593		T4	188916
auto[1]	2094883	1			T1	8082		T2	100		T4	18795
auto[2]	2119649	1			T1	8242		T2	141		T4	18980
auto[3]	3573970	1			T1	826		T2	18		T4	1873

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8015165

1

T1

100196

T2

851

T4

23

auto[1]

13789142

1

T1

97

T2

1

T4

228541

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	330531	1			T2	21		T23	2		T24	729
auto[0]	auto[0]	auto[1]	33807	1			T2	3		T24	84		T68	3
auto[0]	auto[0]	auto[2]	33755	1			T2	2		T24	81		T20	1
auto[0]	auto[0]	auto[3]	7802	1			T24	8		T21	3		T129	37
auto[0]	auto[1]	auto[0]	2985262	1			T1	41315		T2	306		T4	13
auto[0]	auto[1]	auto[1]	316209	1			T1	3970		T2	59		T9	2778
auto[0]	auto[1]	auto[2]	297711	1			T1	4135		T2	33		T4	3
auto[0]	auto[1]	auto[3]	56926	1			T1	424		T2	6		T9	286
auto[0]	auto[2]	auto[0]	283381	1			T21	289		T129	3494		T130	321
auto[0]	auto[2]	auto[1]	28907	1			T21	27		T22	1		T129	350
auto[0]	auto[2]	auto[2]	31398	1			T2	28		T23	6		T24	419
auto[0]	auto[2]	auto[3]	6449	1			T2	5		T23	1		T24	49
auto[0]	auto[3]	auto[0]	2937384	1			T1	41748		T2	265		T4	7
auto[0]	auto[3]	auto[1]	292602	1			T1	4103		T2	38		T9	2889
auto[0]	auto[3]	auto[2]	315015	1			T1	4099		T2	78		T9	2888
auto[0]	auto[3]	auto[3]	58026	1			T1	402		T2	7		T9	273
auto[1]	auto[0]	auto[0]	7983	1			T24	1		T49	190		T68	1
auto[1]	auto[0]	auto[1]	34952	1			T49	863		T131	2		T109	2
auto[1]	auto[0]	auto[2]	34822	1			T49	835		T129	3		T131	1
auto[1]	auto[0]	auto[3]	156221	1			T49	3756		T132	2		T133	1
auto[1]	auto[1]	auto[0]	3735471	1			T1	44		T2	1		T4	94260
auto[1]	auto[1]	auto[1]	691617	1			T1	4		T4	9360		T9	3
auto[1]	auto[1]	auto[2]	688645	1			T1	3		T4	9502		T10	3
auto[1]	auto[1]	auto[3]	1584271	1			T4	937		T13	1224		T49	11171
auto[1]	auto[2]	auto[0]	4863	1			T21	1		T129	4		T131	18
auto[1]	auto[2]	auto[1]	20600	1			T131	1		T109	2		T134	1
auto[1]	auto[2]	auto[2]	30367	1			T24	1		T49	743		T131	1
auto[1]	auto[2]	auto[3]	137020	1			T49	3288		T127	3649		T135	3
auto[1]	auto[3]	auto[0]	3730930	1			T1	36		T4	94636		T9	28
auto[1]	auto[3]	auto[1]	676189	1			T1	5		T4	9435		T9	6
auto[1]	auto[3]	auto[2]	687936	1			T1	5		T4	9475		T10	3
auto[1]	auto[3]	auto[3]	1567255	1			T4	936		T13	1151		T49	10867