Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	334684695	210217	0	0
ctrl_regwen_rd_A	334684695	3586	0	0
exec_rd_A	334684695	3544	0	0
exec_regwen_rd_A	334684695	3974	0	0
readback_rd_A	334684695	2700	0	0
readback_regwen_rd_A	334684695	2161	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334684695	210217	0	0
T14	630	0	0	0
T20	88534	0	0	0
T23	78133	2650	0	0
T24	688177	0	0	0
T25	32907	0	0	0
T26	0	1188	0	0
T27	0	3866	0	0
T40	0	3086	0	0
T49	172650	0	0	0
T52	0	1919	0	0
T54	0	5260	0	0
T56	0	7656	0	0
T57	96402	0	0	0
T58	302951	0	0	0
T59	5695	0	0	0
T60	8572	0	0	0
T66	0	3882	0	0
T69	0	1129	0	0
T70	0	1610	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334684695	3586	0	0
T14	630	0	0	0
T20	88534	0	0	0
T23	78133	114	0	0
T24	688177	0	0	0
T25	32907	0	0	0
T26	0	123	0	0
T27	0	173	0	0
T40	0	264	0	0
T44	0	99	0	0
T45	0	563	0	0
T49	172650	0	0	0
T57	96402	0	0	0
T58	302951	0	0	0
T59	5695	0	0	0
T60	8572	0	0	0
T66	0	171	0	0
T69	0	45	0	0
T106	0	198	0	0
T107	0	380	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334684695	3544	0	0
T14	630	0	0	0
T20	88534	0	0	0
T23	78133	186	0	0
T24	688177	0	0	0
T25	32907	0	0	0
T26	0	98	0	0
T27	0	130	0	0
T40	0	183	0	0
T44	0	160	0	0
T45	0	497	0	0
T49	172650	0	0	0
T57	96402	0	0	0
T58	302951	0	0	0
T59	5695	0	0	0
T60	8572	0	0	0
T66	0	194	0	0
T69	0	50	0	0
T106	0	270	0	0
T107	0	311	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334684695	3974	0	0
T14	630	0	0	0
T20	88534	0	0	0
T23	78133	111	0	0
T24	688177	0	0	0
T25	32907	0	0	0
T26	0	102	0	0
T27	0	196	0	0
T40	0	204	0	0
T44	0	216	0	0
T45	0	549	0	0
T49	172650	0	0	0
T57	96402	0	0	0
T58	302951	0	0	0
T59	5695	0	0	0
T60	8572	0	0	0
T66	0	188	0	0
T69	0	67	0	0
T106	0	246	0	0
T107	0	401	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334684695	2700	0	0
T14	630	0	0	0
T20	88534	0	0	0
T23	78133	101	0	0
T24	688177	0	0	0
T25	32907	0	0	0
T26	0	127	0	0
T27	0	131	0	0
T40	0	243	0	0
T44	0	86	0	0
T45	0	432	0	0
T49	172650	0	0	0
T57	96402	0	0	0
T58	302951	0	0	0
T59	5695	0	0	0
T60	8572	0	0	0
T66	0	102	0	0
T69	0	39	0	0
T106	0	209	0	0
T107	0	404	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334684695	2161	0	0
T14	630	0	0	0
T20	88534	0	0	0
T23	78133	42	0	0
T24	688177	0	0	0
T25	32907	0	0	0
T26	0	92	0	0
T27	0	147	0	0
T40	0	191	0	0
T44	0	101	0	0
T45	0	412	0	0
T49	172650	0	0	0
T57	96402	0	0	0
T58	302951	0	0	0
T59	5695	0	0	0
T60	8572	0	0	0
T66	0	166	0	0
T69	0	48	0	0
T106	0	126	0	0
T107	0	281	0	0