| T796 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3143352019 |
|
|
Jun 25 06:02:22 PM PDT 24 |
Jun 25 06:02:26 PM PDT 24 |
116571409 ps |
| T797 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.176853601 |
|
|
Jun 25 06:06:27 PM PDT 24 |
Jun 25 06:06:37 PM PDT 24 |
986708069 ps |
| T798 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3410945117 |
|
|
Jun 25 06:02:22 PM PDT 24 |
Jun 25 06:03:49 PM PDT 24 |
2927497699 ps |
| T799 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3455140750 |
|
|
Jun 25 06:02:52 PM PDT 24 |
Jun 25 06:02:58 PM PDT 24 |
222791211 ps |
| T800 |
/workspace/coverage/default/18.sram_ctrl_executable.711058999 |
|
|
Jun 25 06:03:22 PM PDT 24 |
Jun 25 06:13:20 PM PDT 24 |
2609191429 ps |
| T801 |
/workspace/coverage/default/40.sram_ctrl_smoke.244108846 |
|
|
Jun 25 06:05:39 PM PDT 24 |
Jun 25 06:06:44 PM PDT 24 |
1553076310 ps |
| T802 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.1919323718 |
|
|
Jun 25 06:06:53 PM PDT 24 |
Jun 25 06:07:00 PM PDT 24 |
983515158 ps |
| T803 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2173890556 |
|
|
Jun 25 06:02:40 PM PDT 24 |
Jun 25 06:08:28 PM PDT 24 |
3441495450 ps |
| T804 |
/workspace/coverage/default/32.sram_ctrl_alert_test.99478331 |
|
|
Jun 25 06:04:57 PM PDT 24 |
Jun 25 06:04:58 PM PDT 24 |
20249637 ps |
| T805 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.3452869537 |
|
|
Jun 25 06:02:46 PM PDT 24 |
Jun 25 06:02:53 PM PDT 24 |
1883644089 ps |
| T806 |
/workspace/coverage/default/41.sram_ctrl_executable.804884396 |
|
|
Jun 25 06:05:57 PM PDT 24 |
Jun 25 06:08:39 PM PDT 24 |
71677400134 ps |
| T807 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.3326316818 |
|
|
Jun 25 06:03:54 PM PDT 24 |
Jun 25 06:07:45 PM PDT 24 |
4690336525 ps |
| T808 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.4245048898 |
|
|
Jun 25 06:02:30 PM PDT 24 |
Jun 25 06:02:49 PM PDT 24 |
832780604 ps |
| T809 |
/workspace/coverage/default/13.sram_ctrl_partial_access.3824513370 |
|
|
Jun 25 06:03:03 PM PDT 24 |
Jun 25 06:03:20 PM PDT 24 |
616342607 ps |
| T810 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.1986186188 |
|
|
Jun 25 06:05:30 PM PDT 24 |
Jun 25 06:11:22 PM PDT 24 |
30496495244 ps |
| T811 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2287863552 |
|
|
Jun 25 06:04:45 PM PDT 24 |
Jun 25 06:08:45 PM PDT 24 |
11770561156 ps |
| T812 |
/workspace/coverage/default/37.sram_ctrl_stress_all.1645855694 |
|
|
Jun 25 06:05:23 PM PDT 24 |
Jun 25 07:40:52 PM PDT 24 |
52027857766 ps |
| T813 |
/workspace/coverage/default/16.sram_ctrl_stress_all.1302630363 |
|
|
Jun 25 06:03:19 PM PDT 24 |
Jun 25 06:23:23 PM PDT 24 |
71830248422 ps |
| T814 |
/workspace/coverage/default/36.sram_ctrl_alert_test.2721201339 |
|
|
Jun 25 06:05:23 PM PDT 24 |
Jun 25 06:05:24 PM PDT 24 |
22924815 ps |
| T815 |
/workspace/coverage/default/36.sram_ctrl_executable.3929044519 |
|
|
Jun 25 06:05:23 PM PDT 24 |
Jun 25 06:19:46 PM PDT 24 |
10484276649 ps |
| T816 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.164829836 |
|
|
Jun 25 06:02:25 PM PDT 24 |
Jun 25 06:20:59 PM PDT 24 |
2659981924 ps |
| T817 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.1830838487 |
|
|
Jun 25 06:02:44 PM PDT 24 |
Jun 25 06:02:51 PM PDT 24 |
926054137 ps |
| T818 |
/workspace/coverage/default/39.sram_ctrl_alert_test.1269958943 |
|
|
Jun 25 06:05:39 PM PDT 24 |
Jun 25 06:05:40 PM PDT 24 |
12647439 ps |
| T819 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.2698256392 |
|
|
Jun 25 06:03:06 PM PDT 24 |
Jun 25 06:06:06 PM PDT 24 |
3813771987 ps |
| T820 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2494067072 |
|
|
Jun 25 06:02:42 PM PDT 24 |
Jun 25 06:02:47 PM PDT 24 |
186953110 ps |
| T821 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.389460001 |
|
|
Jun 25 06:03:10 PM PDT 24 |
Jun 25 06:06:54 PM PDT 24 |
9874361268 ps |
| T822 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2488889876 |
|
|
Jun 25 06:06:44 PM PDT 24 |
Jun 25 06:13:04 PM PDT 24 |
3301994486 ps |
| T823 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.1029095580 |
|
|
Jun 25 06:04:34 PM PDT 24 |
Jun 25 06:04:36 PM PDT 24 |
85742322 ps |
| T824 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2960533669 |
|
|
Jun 25 06:04:23 PM PDT 24 |
Jun 25 06:09:05 PM PDT 24 |
1943765345 ps |
| T825 |
/workspace/coverage/default/23.sram_ctrl_executable.254900690 |
|
|
Jun 25 06:03:54 PM PDT 24 |
Jun 25 06:11:01 PM PDT 24 |
59074662062 ps |
| T826 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.551831648 |
|
|
Jun 25 06:03:18 PM PDT 24 |
Jun 25 06:03:20 PM PDT 24 |
79112516 ps |
| T827 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3251926801 |
|
|
Jun 25 06:06:44 PM PDT 24 |
Jun 25 06:06:51 PM PDT 24 |
581492477 ps |
| T828 |
/workspace/coverage/default/6.sram_ctrl_alert_test.2062464204 |
|
|
Jun 25 06:02:48 PM PDT 24 |
Jun 25 06:02:51 PM PDT 24 |
24205798 ps |
| T829 |
/workspace/coverage/default/47.sram_ctrl_stress_all.732641648 |
|
|
Jun 25 06:06:44 PM PDT 24 |
Jun 25 06:50:14 PM PDT 24 |
51223146731 ps |
| T830 |
/workspace/coverage/default/38.sram_ctrl_regwen.399957118 |
|
|
Jun 25 06:05:28 PM PDT 24 |
Jun 25 06:13:28 PM PDT 24 |
3911826547 ps |
| T831 |
/workspace/coverage/default/14.sram_ctrl_bijection.1111472487 |
|
|
Jun 25 06:03:07 PM PDT 24 |
Jun 25 06:04:09 PM PDT 24 |
10944394235 ps |
| T832 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.2116924668 |
|
|
Jun 25 06:02:47 PM PDT 24 |
Jun 25 06:02:50 PM PDT 24 |
140696703 ps |
| T833 |
/workspace/coverage/default/38.sram_ctrl_stress_all.3261759982 |
|
|
Jun 25 06:05:30 PM PDT 24 |
Jun 25 06:42:08 PM PDT 24 |
18811072961 ps |
| T834 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.248440156 |
|
|
Jun 25 06:03:40 PM PDT 24 |
Jun 25 06:21:40 PM PDT 24 |
2930678323 ps |
| T835 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.2281484162 |
|
|
Jun 25 06:04:36 PM PDT 24 |
Jun 25 06:04:49 PM PDT 24 |
667735423 ps |
| T836 |
/workspace/coverage/default/35.sram_ctrl_partial_access.214173106 |
|
|
Jun 25 06:05:15 PM PDT 24 |
Jun 25 06:05:25 PM PDT 24 |
1544271455 ps |
| T837 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.988711653 |
|
|
Jun 25 06:02:23 PM PDT 24 |
Jun 25 06:06:58 PM PDT 24 |
5275184894 ps |
| T838 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.1655361298 |
|
|
Jun 25 06:04:13 PM PDT 24 |
Jun 25 06:09:36 PM PDT 24 |
12968148328 ps |
| T839 |
/workspace/coverage/default/1.sram_ctrl_executable.3941718230 |
|
|
Jun 25 06:02:31 PM PDT 24 |
Jun 25 06:24:31 PM PDT 24 |
35314084318 ps |
| T840 |
/workspace/coverage/default/2.sram_ctrl_partial_access.1724705136 |
|
|
Jun 25 06:02:31 PM PDT 24 |
Jun 25 06:02:50 PM PDT 24 |
3712942363 ps |
| T841 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.34828668 |
|
|
Jun 25 06:04:25 PM PDT 24 |
Jun 25 06:16:29 PM PDT 24 |
1505297436 ps |
| T842 |
/workspace/coverage/default/15.sram_ctrl_alert_test.942330819 |
|
|
Jun 25 06:03:12 PM PDT 24 |
Jun 25 06:03:14 PM PDT 24 |
25094572 ps |
| T843 |
/workspace/coverage/default/44.sram_ctrl_partial_access.828856728 |
|
|
Jun 25 06:06:18 PM PDT 24 |
Jun 25 06:06:56 PM PDT 24 |
369658329 ps |
| T844 |
/workspace/coverage/default/45.sram_ctrl_partial_access.2383613387 |
|
|
Jun 25 06:06:16 PM PDT 24 |
Jun 25 06:06:36 PM PDT 24 |
926492319 ps |
| T845 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.335637544 |
|
|
Jun 25 06:03:29 PM PDT 24 |
Jun 25 06:03:41 PM PDT 24 |
1642108173 ps |
| T846 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3678066493 |
|
|
Jun 25 06:04:35 PM PDT 24 |
Jun 25 06:05:03 PM PDT 24 |
645620719 ps |
| T847 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.3027958738 |
|
|
Jun 25 06:02:35 PM PDT 24 |
Jun 25 06:02:37 PM PDT 24 |
28128276 ps |
| T848 |
/workspace/coverage/default/16.sram_ctrl_executable.329511536 |
|
|
Jun 25 06:03:19 PM PDT 24 |
Jun 25 06:22:26 PM PDT 24 |
51563494555 ps |
| T849 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.398433548 |
|
|
Jun 25 06:02:40 PM PDT 24 |
Jun 25 06:14:28 PM PDT 24 |
3108675475 ps |
| T850 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1307944389 |
|
|
Jun 25 06:05:30 PM PDT 24 |
Jun 25 06:09:56 PM PDT 24 |
583952885 ps |
| T851 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.331709452 |
|
|
Jun 25 06:05:40 PM PDT 24 |
Jun 25 06:05:51 PM PDT 24 |
901039085 ps |
| T852 |
/workspace/coverage/default/16.sram_ctrl_regwen.2706861043 |
|
|
Jun 25 06:03:12 PM PDT 24 |
Jun 25 06:24:13 PM PDT 24 |
23402391955 ps |
| T853 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.3350986128 |
|
|
Jun 25 06:03:04 PM PDT 24 |
Jun 25 06:18:37 PM PDT 24 |
5453391957 ps |
| T854 |
/workspace/coverage/default/30.sram_ctrl_regwen.3777741403 |
|
|
Jun 25 06:04:38 PM PDT 24 |
Jun 25 06:08:07 PM PDT 24 |
3384908201 ps |
| T855 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2993025136 |
|
|
Jun 25 06:04:56 PM PDT 24 |
Jun 25 06:08:07 PM PDT 24 |
9564348244 ps |
| T856 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1455790813 |
|
|
Jun 25 06:02:46 PM PDT 24 |
Jun 25 06:08:37 PM PDT 24 |
8478145628 ps |
| T857 |
/workspace/coverage/default/48.sram_ctrl_smoke.2023953936 |
|
|
Jun 25 06:06:45 PM PDT 24 |
Jun 25 06:06:48 PM PDT 24 |
140171993 ps |
| T858 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.3628760393 |
|
|
Jun 25 06:02:42 PM PDT 24 |
Jun 25 06:02:49 PM PDT 24 |
401890274 ps |
| T859 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.1480339737 |
|
|
Jun 25 06:05:56 PM PDT 24 |
Jun 25 06:09:07 PM PDT 24 |
3366110300 ps |
| T860 |
/workspace/coverage/default/33.sram_ctrl_partial_access.2767495019 |
|
|
Jun 25 06:04:54 PM PDT 24 |
Jun 25 06:06:49 PM PDT 24 |
3216512345 ps |
| T861 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.3465475644 |
|
|
Jun 25 06:04:40 PM PDT 24 |
Jun 25 06:22:05 PM PDT 24 |
12680448218 ps |
| T862 |
/workspace/coverage/default/38.sram_ctrl_alert_test.1699921623 |
|
|
Jun 25 06:05:33 PM PDT 24 |
Jun 25 06:05:35 PM PDT 24 |
15651795 ps |
| T863 |
/workspace/coverage/default/7.sram_ctrl_alert_test.1362813993 |
|
|
Jun 25 06:02:47 PM PDT 24 |
Jun 25 06:02:50 PM PDT 24 |
55978653 ps |
| T864 |
/workspace/coverage/default/29.sram_ctrl_partial_access.2558743247 |
|
|
Jun 25 06:04:27 PM PDT 24 |
Jun 25 06:04:41 PM PDT 24 |
690118788 ps |
| T865 |
/workspace/coverage/default/37.sram_ctrl_bijection.2412534695 |
|
|
Jun 25 06:05:25 PM PDT 24 |
Jun 25 06:06:37 PM PDT 24 |
3845845397 ps |
| T866 |
/workspace/coverage/default/24.sram_ctrl_smoke.3240482325 |
|
|
Jun 25 06:03:56 PM PDT 24 |
Jun 25 06:04:11 PM PDT 24 |
1517226048 ps |
| T867 |
/workspace/coverage/default/7.sram_ctrl_smoke.1425435166 |
|
|
Jun 25 06:02:47 PM PDT 24 |
Jun 25 06:03:02 PM PDT 24 |
1212041793 ps |
| T868 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3655893532 |
|
|
Jun 25 06:03:29 PM PDT 24 |
Jun 25 06:08:24 PM PDT 24 |
31173951835 ps |
| T869 |
/workspace/coverage/default/49.sram_ctrl_partial_access.740989986 |
|
|
Jun 25 06:06:53 PM PDT 24 |
Jun 25 06:07:01 PM PDT 24 |
136305208 ps |
| T870 |
/workspace/coverage/default/9.sram_ctrl_smoke.764023413 |
|
|
Jun 25 06:02:50 PM PDT 24 |
Jun 25 06:03:40 PM PDT 24 |
214473259 ps |
| T871 |
/workspace/coverage/default/42.sram_ctrl_stress_all.3075366620 |
|
|
Jun 25 06:06:06 PM PDT 24 |
Jun 25 06:47:38 PM PDT 24 |
131535708118 ps |
| T872 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.3658686230 |
|
|
Jun 25 06:03:29 PM PDT 24 |
Jun 25 06:03:34 PM PDT 24 |
103689795 ps |
| T873 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.2210569771 |
|
|
Jun 25 06:06:45 PM PDT 24 |
Jun 25 06:06:57 PM PDT 24 |
442844988 ps |
| T874 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.4155860752 |
|
|
Jun 25 06:03:39 PM PDT 24 |
Jun 25 06:03:41 PM PDT 24 |
26771358 ps |
| T875 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.3335231532 |
|
|
Jun 25 06:04:30 PM PDT 24 |
Jun 25 06:04:35 PM PDT 24 |
1476215533 ps |
| T876 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.919176658 |
|
|
Jun 25 06:05:06 PM PDT 24 |
Jun 25 06:09:16 PM PDT 24 |
1178717066 ps |
| T877 |
/workspace/coverage/default/26.sram_ctrl_bijection.689122685 |
|
|
Jun 25 06:04:23 PM PDT 24 |
Jun 25 06:05:03 PM PDT 24 |
6688868883 ps |
| T878 |
/workspace/coverage/default/22.sram_ctrl_smoke.2861796508 |
|
|
Jun 25 06:03:53 PM PDT 24 |
Jun 25 06:04:03 PM PDT 24 |
131165913 ps |
| T879 |
/workspace/coverage/default/7.sram_ctrl_bijection.416066182 |
|
|
Jun 25 06:02:46 PM PDT 24 |
Jun 25 06:03:23 PM PDT 24 |
9895620961 ps |
| T880 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.3687879087 |
|
|
Jun 25 06:02:32 PM PDT 24 |
Jun 25 06:02:35 PM PDT 24 |
504036299 ps |
| T881 |
/workspace/coverage/default/38.sram_ctrl_executable.2399047813 |
|
|
Jun 25 06:05:31 PM PDT 24 |
Jun 25 06:14:20 PM PDT 24 |
64114414370 ps |
| T882 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.1215078731 |
|
|
Jun 25 06:06:26 PM PDT 24 |
Jun 25 06:06:33 PM PDT 24 |
1138211480 ps |
| T883 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.3429579538 |
|
|
Jun 25 06:05:48 PM PDT 24 |
Jun 25 06:06:00 PM PDT 24 |
453303699 ps |
| T884 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.1185577317 |
|
|
Jun 25 06:03:21 PM PDT 24 |
Jun 25 06:03:31 PM PDT 24 |
700383404 ps |
| T885 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.2298925553 |
|
|
Jun 25 06:03:54 PM PDT 24 |
Jun 25 06:04:53 PM PDT 24 |
110129395 ps |
| T886 |
/workspace/coverage/default/35.sram_ctrl_executable.11519882 |
|
|
Jun 25 06:05:12 PM PDT 24 |
Jun 25 06:17:01 PM PDT 24 |
10651681557 ps |
| T887 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.3431779288 |
|
|
Jun 25 06:03:30 PM PDT 24 |
Jun 25 06:03:37 PM PDT 24 |
347827586 ps |
| T888 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.4239198771 |
|
|
Jun 25 06:04:23 PM PDT 24 |
Jun 25 06:04:38 PM PDT 24 |
101548790 ps |
| T889 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.1411771372 |
|
|
Jun 25 06:03:16 PM PDT 24 |
Jun 25 06:03:27 PM PDT 24 |
174090370 ps |
| T890 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.659549171 |
|
|
Jun 25 06:03:35 PM PDT 24 |
Jun 25 06:05:18 PM PDT 24 |
129181516 ps |
| T891 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.1863953959 |
|
|
Jun 25 06:05:56 PM PDT 24 |
Jun 25 06:06:04 PM PDT 24 |
1354504269 ps |
| T892 |
/workspace/coverage/default/47.sram_ctrl_bijection.2092529209 |
|
|
Jun 25 06:06:35 PM PDT 24 |
Jun 25 06:07:03 PM PDT 24 |
22073946863 ps |
| T893 |
/workspace/coverage/default/12.sram_ctrl_regwen.806814497 |
|
|
Jun 25 06:02:57 PM PDT 24 |
Jun 25 06:13:12 PM PDT 24 |
67666740061 ps |
| T894 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.3254809113 |
|
|
Jun 25 06:03:40 PM PDT 24 |
Jun 25 06:03:42 PM PDT 24 |
26552524 ps |
| T895 |
/workspace/coverage/default/46.sram_ctrl_alert_test.1667579669 |
|
|
Jun 25 06:06:37 PM PDT 24 |
Jun 25 06:06:39 PM PDT 24 |
15238043 ps |
| T896 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.1893219539 |
|
|
Jun 25 06:06:52 PM PDT 24 |
Jun 25 06:06:57 PM PDT 24 |
171426802 ps |
| T897 |
/workspace/coverage/default/19.sram_ctrl_executable.3967536290 |
|
|
Jun 25 06:03:30 PM PDT 24 |
Jun 25 06:08:06 PM PDT 24 |
5528213318 ps |
| T898 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2461207448 |
|
|
Jun 25 06:04:24 PM PDT 24 |
Jun 25 06:05:25 PM PDT 24 |
1347313977 ps |
| T899 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3363777723 |
|
|
Jun 25 06:06:46 PM PDT 24 |
Jun 25 06:16:19 PM PDT 24 |
2859854997 ps |
| T900 |
/workspace/coverage/default/31.sram_ctrl_smoke.2328476130 |
|
|
Jun 25 06:04:39 PM PDT 24 |
Jun 25 06:07:22 PM PDT 24 |
745792781 ps |
| T901 |
/workspace/coverage/default/41.sram_ctrl_smoke.3557027669 |
|
|
Jun 25 06:05:46 PM PDT 24 |
Jun 25 06:05:56 PM PDT 24 |
190778501 ps |
| T902 |
/workspace/coverage/default/33.sram_ctrl_regwen.1285786885 |
|
|
Jun 25 06:04:54 PM PDT 24 |
Jun 25 06:08:20 PM PDT 24 |
2394485579 ps |
| T903 |
/workspace/coverage/default/26.sram_ctrl_stress_all.4227471986 |
|
|
Jun 25 06:04:11 PM PDT 24 |
Jun 25 06:49:40 PM PDT 24 |
36727909945 ps |
| T904 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.2742192698 |
|
|
Jun 25 06:04:25 PM PDT 24 |
Jun 25 06:04:30 PM PDT 24 |
503016459 ps |
| T905 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.3198026049 |
|
|
Jun 25 06:04:38 PM PDT 24 |
Jun 25 06:04:43 PM PDT 24 |
817382181 ps |
| T906 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.1027492257 |
|
|
Jun 25 06:03:33 PM PDT 24 |
Jun 25 06:03:41 PM PDT 24 |
961610934 ps |
| T907 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.2193020722 |
|
|
Jun 25 06:03:55 PM PDT 24 |
Jun 25 06:04:02 PM PDT 24 |
64511643 ps |
| T908 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1048131449 |
|
|
Jun 25 06:03:24 PM PDT 24 |
Jun 25 06:07:37 PM PDT 24 |
3566975513 ps |
| T909 |
/workspace/coverage/default/13.sram_ctrl_bijection.3990945982 |
|
|
Jun 25 06:03:10 PM PDT 24 |
Jun 25 06:03:45 PM PDT 24 |
1955509329 ps |
| T910 |
/workspace/coverage/default/3.sram_ctrl_executable.3843613385 |
|
|
Jun 25 06:02:43 PM PDT 24 |
Jun 25 06:20:22 PM PDT 24 |
24884769902 ps |
| T911 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3103632956 |
|
|
Jun 25 06:05:04 PM PDT 24 |
Jun 25 06:07:28 PM PDT 24 |
4900855720 ps |
| T912 |
/workspace/coverage/default/36.sram_ctrl_bijection.3876859085 |
|
|
Jun 25 06:05:22 PM PDT 24 |
Jun 25 06:06:33 PM PDT 24 |
12586226398 ps |
| T913 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.4205597089 |
|
|
Jun 25 06:02:22 PM PDT 24 |
Jun 25 06:07:31 PM PDT 24 |
8136447282 ps |
| T914 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.769525356 |
|
|
Jun 25 06:03:05 PM PDT 24 |
Jun 25 06:05:32 PM PDT 24 |
797083704 ps |
| T915 |
/workspace/coverage/default/9.sram_ctrl_partial_access.2033512173 |
|
|
Jun 25 06:02:47 PM PDT 24 |
Jun 25 06:04:53 PM PDT 24 |
1342417615 ps |
| T916 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.3738500113 |
|
|
Jun 25 06:03:34 PM PDT 24 |
Jun 25 06:05:47 PM PDT 24 |
5676384302 ps |
| T917 |
/workspace/coverage/default/44.sram_ctrl_executable.2700910113 |
|
|
Jun 25 06:06:17 PM PDT 24 |
Jun 25 06:24:05 PM PDT 24 |
9822846908 ps |
| T918 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.1954620278 |
|
|
Jun 25 06:04:05 PM PDT 24 |
Jun 25 06:04:06 PM PDT 24 |
28927052 ps |
| T919 |
/workspace/coverage/default/23.sram_ctrl_partial_access.1741474602 |
|
|
Jun 25 06:03:53 PM PDT 24 |
Jun 25 06:03:59 PM PDT 24 |
330410176 ps |
| T920 |
/workspace/coverage/default/37.sram_ctrl_executable.1536245056 |
|
|
Jun 25 06:05:24 PM PDT 24 |
Jun 25 06:39:56 PM PDT 24 |
13818020344 ps |
| T921 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.2584450570 |
|
|
Jun 25 06:05:24 PM PDT 24 |
Jun 25 06:06:04 PM PDT 24 |
88470392 ps |
| T922 |
/workspace/coverage/default/25.sram_ctrl_bijection.1846521997 |
|
|
Jun 25 06:04:04 PM PDT 24 |
Jun 25 06:05:02 PM PDT 24 |
7245637008 ps |
| T923 |
/workspace/coverage/default/28.sram_ctrl_stress_all.2943117169 |
|
|
Jun 25 06:04:32 PM PDT 24 |
Jun 25 07:19:10 PM PDT 24 |
888868746949 ps |
| T924 |
/workspace/coverage/default/37.sram_ctrl_smoke.357383323 |
|
|
Jun 25 06:05:24 PM PDT 24 |
Jun 25 06:05:42 PM PDT 24 |
816213937 ps |
| T925 |
/workspace/coverage/default/17.sram_ctrl_smoke.3818231641 |
|
|
Jun 25 06:03:14 PM PDT 24 |
Jun 25 06:03:48 PM PDT 24 |
1619035923 ps |
| T926 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1026703767 |
|
|
Jun 25 06:04:26 PM PDT 24 |
Jun 25 06:09:34 PM PDT 24 |
33420024563 ps |
| T927 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1154837028 |
|
|
Jun 25 06:04:37 PM PDT 24 |
Jun 25 06:04:39 PM PDT 24 |
42264095 ps |
| T928 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.4289076822 |
|
|
Jun 25 06:02:55 PM PDT 24 |
Jun 25 06:13:26 PM PDT 24 |
9058613894 ps |
| T929 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.1894723884 |
|
|
Jun 25 06:06:16 PM PDT 24 |
Jun 25 06:15:06 PM PDT 24 |
91898479181 ps |
| T930 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.1661005257 |
|
|
Jun 25 06:04:05 PM PDT 24 |
Jun 25 06:04:11 PM PDT 24 |
52513417 ps |
| T931 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2699810923 |
|
|
Jun 25 06:06:44 PM PDT 24 |
Jun 25 06:10:54 PM PDT 24 |
1195957738 ps |
| T932 |
/workspace/coverage/default/17.sram_ctrl_stress_all.1909483083 |
|
|
Jun 25 06:03:29 PM PDT 24 |
Jun 25 06:31:03 PM PDT 24 |
62883731491 ps |
| T933 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.110526686 |
|
|
Jun 25 06:03:40 PM PDT 24 |
Jun 25 06:07:45 PM PDT 24 |
12397625655 ps |
| T934 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.1658277035 |
|
|
Jun 25 06:05:41 PM PDT 24 |
Jun 25 06:05:47 PM PDT 24 |
257466696 ps |
| T935 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.18738405 |
|
|
Jun 25 06:03:53 PM PDT 24 |
Jun 25 06:11:59 PM PDT 24 |
26676211503 ps |
| T936 |
/workspace/coverage/default/21.sram_ctrl_smoke.1047234381 |
|
|
Jun 25 06:03:41 PM PDT 24 |
Jun 25 06:03:45 PM PDT 24 |
260899406 ps |
| T937 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1186809278 |
|
|
Jun 25 04:51:51 PM PDT 24 |
Jun 25 04:51:53 PM PDT 24 |
45469288 ps |
| T61 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1094682540 |
|
|
Jun 25 04:52:00 PM PDT 24 |
Jun 25 04:52:03 PM PDT 24 |
266526620 ps |
| T62 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3199397667 |
|
|
Jun 25 04:52:11 PM PDT 24 |
Jun 25 04:52:14 PM PDT 24 |
222661900 ps |
| T63 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3398059005 |
|
|
Jun 25 04:52:18 PM PDT 24 |
Jun 25 04:52:21 PM PDT 24 |
188167590 ps |
| T71 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3234308337 |
|
|
Jun 25 04:51:52 PM PDT 24 |
Jun 25 04:51:53 PM PDT 24 |
27643114 ps |
| T101 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1312411417 |
|
|
Jun 25 04:51:50 PM PDT 24 |
Jun 25 04:51:52 PM PDT 24 |
18414244 ps |
| T102 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3066208179 |
|
|
Jun 25 04:51:39 PM PDT 24 |
Jun 25 04:51:41 PM PDT 24 |
45228863 ps |
| T103 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.295203377 |
|
|
Jun 25 04:51:50 PM PDT 24 |
Jun 25 04:51:53 PM PDT 24 |
26417578 ps |
| T72 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3115340280 |
|
|
Jun 25 04:52:04 PM PDT 24 |
Jun 25 04:52:06 PM PDT 24 |
50370579 ps |
| T115 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4040514814 |
|
|
Jun 25 04:52:40 PM PDT 24 |
Jun 25 04:52:42 PM PDT 24 |
252986625 ps |
| T938 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2871650569 |
|
|
Jun 25 04:52:10 PM PDT 24 |
Jun 25 04:52:13 PM PDT 24 |
46214407 ps |
| T104 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4287356835 |
|
|
Jun 25 04:52:20 PM PDT 24 |
Jun 25 04:52:22 PM PDT 24 |
23272359 ps |
| T95 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1316800364 |
|
|
Jun 25 04:51:52 PM PDT 24 |
Jun 25 04:51:54 PM PDT 24 |
52361636 ps |
| T111 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2280695899 |
|
|
Jun 25 04:51:53 PM PDT 24 |
Jun 25 04:51:57 PM PDT 24 |
576736435 ps |
| T939 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1768702241 |
|
|
Jun 25 04:51:49 PM PDT 24 |
Jun 25 04:51:53 PM PDT 24 |
364730285 ps |
| T96 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1416095899 |
|
|
Jun 25 04:52:21 PM PDT 24 |
Jun 25 04:52:23 PM PDT 24 |
26997508 ps |
| T73 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1593136840 |
|
|
Jun 25 04:52:09 PM PDT 24 |
Jun 25 04:52:11 PM PDT 24 |
23882629 ps |
| T117 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1984242596 |
|
|
Jun 25 04:52:22 PM PDT 24 |
Jun 25 04:52:25 PM PDT 24 |
79180626 ps |
| T114 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1413108337 |
|
|
Jun 25 04:52:10 PM PDT 24 |
Jun 25 04:52:14 PM PDT 24 |
536166637 ps |
| T105 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1134857738 |
|
|
Jun 25 04:52:05 PM PDT 24 |
Jun 25 04:52:06 PM PDT 24 |
21491866 ps |
| T940 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.39474284 |
|
|
Jun 25 04:52:19 PM PDT 24 |
Jun 25 04:52:21 PM PDT 24 |
56897844 ps |
| T119 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3198741464 |
|
|
Jun 25 04:52:31 PM PDT 24 |
Jun 25 04:52:35 PM PDT 24 |
344719953 ps |
| T941 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.352887722 |
|
|
Jun 25 04:52:20 PM PDT 24 |
Jun 25 04:52:24 PM PDT 24 |
249761121 ps |
| T97 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2627963456 |
|
|
Jun 25 04:51:52 PM PDT 24 |
Jun 25 04:51:54 PM PDT 24 |
16388807 ps |
| T74 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3548828923 |
|
|
Jun 25 04:52:09 PM PDT 24 |
Jun 25 04:52:10 PM PDT 24 |
16472525 ps |
| T942 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.492452330 |
|
|
Jun 25 04:52:03 PM PDT 24 |
Jun 25 04:52:05 PM PDT 24 |
31237283 ps |
| T75 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.4277737999 |
|
|
Jun 25 04:52:21 PM PDT 24 |
Jun 25 04:52:24 PM PDT 24 |
776014860 ps |
| T943 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3585367252 |
|
|
Jun 25 04:52:10 PM PDT 24 |
Jun 25 04:52:16 PM PDT 24 |
710810133 ps |
| T944 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3368639631 |
|
|
Jun 25 04:52:03 PM PDT 24 |
Jun 25 04:52:05 PM PDT 24 |
168247970 ps |
| T945 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2827884967 |
|
|
Jun 25 04:52:20 PM PDT 24 |
Jun 25 04:52:22 PM PDT 24 |
60522539 ps |
| T76 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4146257161 |
|
|
Jun 25 04:51:39 PM PDT 24 |
Jun 25 04:51:41 PM PDT 24 |
59125374 ps |
| T946 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.883685733 |
|
|
Jun 25 04:52:13 PM PDT 24 |
Jun 25 04:52:16 PM PDT 24 |
49546191 ps |
| T77 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2457536550 |
|
|
Jun 25 04:52:33 PM PDT 24 |
Jun 25 04:52:34 PM PDT 24 |
14126066 ps |
| T947 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3023273365 |
|
|
Jun 25 04:52:19 PM PDT 24 |
Jun 25 04:52:24 PM PDT 24 |
178838555 ps |
| T78 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2770858650 |
|
|
Jun 25 04:51:52 PM PDT 24 |
Jun 25 04:51:54 PM PDT 24 |
15453238 ps |
| T98 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2873565045 |
|
|
Jun 25 04:52:09 PM PDT 24 |
Jun 25 04:52:13 PM PDT 24 |
1554838906 ps |
| T79 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2902803511 |
|
|
Jun 25 04:51:41 PM PDT 24 |
Jun 25 04:51:45 PM PDT 24 |
2066073026 ps |
| T80 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.488664744 |
|
|
Jun 25 04:51:51 PM PDT 24 |
Jun 25 04:51:54 PM PDT 24 |
823603813 ps |
| T948 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.4131458637 |
|
|
Jun 25 04:52:29 PM PDT 24 |
Jun 25 04:52:31 PM PDT 24 |
67378709 ps |
| T949 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3589295688 |
|
|
Jun 25 04:52:29 PM PDT 24 |
Jun 25 04:52:32 PM PDT 24 |
327208236 ps |
| T950 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3921454995 |
|
|
Jun 25 04:52:10 PM PDT 24 |
Jun 25 04:52:14 PM PDT 24 |
152231584 ps |
| T951 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2392715691 |
|
|
Jun 25 04:51:50 PM PDT 24 |
Jun 25 04:51:54 PM PDT 24 |
124840713 ps |
| T952 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2468784297 |
|
|
Jun 25 04:52:10 PM PDT 24 |
Jun 25 04:52:12 PM PDT 24 |
18045678 ps |
| T953 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1043038194 |
|
|
Jun 25 04:52:21 PM PDT 24 |
Jun 25 04:52:24 PM PDT 24 |
49762049 ps |
| T954 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3536196238 |
|
|
Jun 25 04:52:00 PM PDT 24 |
Jun 25 04:52:06 PM PDT 24 |
140762185 ps |
| T955 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.959722178 |
|
|
Jun 25 04:52:31 PM PDT 24 |
Jun 25 04:52:36 PM PDT 24 |
51461486 ps |
| T956 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1099581592 |
|
|
Jun 25 04:52:11 PM PDT 24 |
Jun 25 04:52:13 PM PDT 24 |
74170773 ps |
| T957 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.788139515 |
|
|
Jun 25 04:52:31 PM PDT 24 |
Jun 25 04:52:35 PM PDT 24 |
99188542 ps |
| T112 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1078837542 |
|
|
Jun 25 04:52:20 PM PDT 24 |
Jun 25 04:52:23 PM PDT 24 |
93618724 ps |
| T81 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3967626952 |
|
|
Jun 25 04:51:59 PM PDT 24 |
Jun 25 04:52:02 PM PDT 24 |
98956953 ps |
| T958 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1226616817 |
|
|
Jun 25 04:51:41 PM PDT 24 |
Jun 25 04:51:45 PM PDT 24 |
60290514 ps |
| T959 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.556654182 |
|
|
Jun 25 04:52:03 PM PDT 24 |
Jun 25 04:52:05 PM PDT 24 |
13796342 ps |
| T960 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3723924745 |
|
|
Jun 25 04:51:51 PM PDT 24 |
Jun 25 04:51:55 PM PDT 24 |
568906425 ps |
| T961 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.292756821 |
|
|
Jun 25 04:52:18 PM PDT 24 |
Jun 25 04:52:20 PM PDT 24 |
24541991 ps |
| T82 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2245266120 |
|
|
Jun 25 04:52:01 PM PDT 24 |
Jun 25 04:52:03 PM PDT 24 |
283572518 ps |
| T962 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.198314349 |
|
|
Jun 25 04:52:33 PM PDT 24 |
Jun 25 04:52:35 PM PDT 24 |
83070575 ps |
| T963 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2091226345 |
|
|
Jun 25 04:52:23 PM PDT 24 |
Jun 25 04:52:25 PM PDT 24 |
95826299 ps |
| T964 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1199570626 |
|
|
Jun 25 04:52:24 PM PDT 24 |
Jun 25 04:52:29 PM PDT 24 |
142296604 ps |
| T965 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.807226894 |
|
|
Jun 25 04:52:10 PM PDT 24 |
Jun 25 04:52:13 PM PDT 24 |
67680044 ps |
| T83 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3398324603 |
|
|
Jun 25 04:52:10 PM PDT 24 |
Jun 25 04:52:12 PM PDT 24 |
41657388 ps |
| T966 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1960504321 |
|
|
Jun 25 04:52:20 PM PDT 24 |
Jun 25 04:52:22 PM PDT 24 |
40810137 ps |
| T113 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.284189521 |
|
|
Jun 25 04:52:12 PM PDT 24 |
Jun 25 04:52:16 PM PDT 24 |
465557613 ps |
| T967 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2319665335 |
|
|
Jun 25 04:52:20 PM PDT 24 |
Jun 25 04:52:22 PM PDT 24 |
98347353 ps |
| T84 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1076083804 |
|
|
Jun 25 04:52:11 PM PDT 24 |
Jun 25 04:52:16 PM PDT 24 |
464796092 ps |
| T968 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3893589149 |
|
|
Jun 25 04:52:01 PM PDT 24 |
Jun 25 04:52:02 PM PDT 24 |
13950349 ps |
| T969 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3045318248 |
|
|
Jun 25 04:52:02 PM PDT 24 |
Jun 25 04:52:03 PM PDT 24 |
21107172 ps |
| T970 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.118878117 |
|
|
Jun 25 04:52:43 PM PDT 24 |
Jun 25 04:52:45 PM PDT 24 |
33494051 ps |
| T971 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2732617148 |
|
|
Jun 25 04:52:11 PM PDT 24 |
Jun 25 04:52:15 PM PDT 24 |
36899886 ps |
| T972 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2147177689 |
|
|
Jun 25 04:51:40 PM PDT 24 |
Jun 25 04:51:44 PM PDT 24 |
92616740 ps |
| T973 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3570816954 |
|
|
Jun 25 04:52:31 PM PDT 24 |
Jun 25 04:52:33 PM PDT 24 |
62580046 ps |
| T974 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2939324311 |
|
|
Jun 25 04:51:52 PM PDT 24 |
Jun 25 04:51:55 PM PDT 24 |
158362448 ps |
| T975 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3885144865 |
|
|
Jun 25 04:52:02 PM PDT 24 |
Jun 25 04:52:07 PM PDT 24 |
134405138 ps |
| T85 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1995242621 |
|
|
Jun 25 04:52:19 PM PDT 24 |
Jun 25 04:52:23 PM PDT 24 |
227751083 ps |
| T976 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3772403724 |
|
|
Jun 25 04:52:31 PM PDT 24 |
Jun 25 04:52:32 PM PDT 24 |
22190057 ps |
| T977 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3538793965 |
|
|
Jun 25 04:52:18 PM PDT 24 |
Jun 25 04:52:20 PM PDT 24 |
40608218 ps |
| T116 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4261819737 |
|
|
Jun 25 04:52:03 PM PDT 24 |
Jun 25 04:52:06 PM PDT 24 |
368527741 ps |
| T90 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2896390240 |
|
|
Jun 25 04:52:30 PM PDT 24 |
Jun 25 04:52:34 PM PDT 24 |
2580574020 ps |
| T978 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2531867456 |
|
|
Jun 25 04:52:19 PM PDT 24 |
Jun 25 04:52:23 PM PDT 24 |
33132466 ps |
| T91 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.298909009 |
|
|
Jun 25 04:52:11 PM PDT 24 |
Jun 25 04:52:16 PM PDT 24 |
1171752204 ps |
| T92 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3362045816 |
|
|
Jun 25 04:52:22 PM PDT 24 |
Jun 25 04:52:26 PM PDT 24 |
1535810753 ps |
| T979 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3534128130 |
|
|
Jun 25 04:52:21 PM PDT 24 |
Jun 25 04:52:25 PM PDT 24 |
344297100 ps |
| T93 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.159364512 |
|
|
Jun 25 04:51:39 PM PDT 24 |
Jun 25 04:51:41 PM PDT 24 |
32919682 ps |
| T980 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.598564719 |
|
|
Jun 25 04:52:01 PM PDT 24 |
Jun 25 04:52:03 PM PDT 24 |
10811528 ps |
| T94 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2272912019 |
|
|
Jun 25 04:52:28 PM PDT 24 |
Jun 25 04:52:32 PM PDT 24 |
505790270 ps |
| T981 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.391288615 |
|
|
Jun 25 04:52:28 PM PDT 24 |
Jun 25 04:52:30 PM PDT 24 |
53535927 ps |
| T982 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3930485246 |
|
|
Jun 25 04:52:31 PM PDT 24 |
Jun 25 04:52:32 PM PDT 24 |
12724010 ps |
| T983 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2153650706 |
|
|
Jun 25 04:52:01 PM PDT 24 |
Jun 25 04:52:04 PM PDT 24 |
36794076 ps |
| T984 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3520316663 |
|
|
Jun 25 04:52:20 PM PDT 24 |
Jun 25 04:52:23 PM PDT 24 |
926480876 ps |
| T985 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3450715001 |
|
|
Jun 25 04:52:03 PM PDT 24 |
Jun 25 04:52:05 PM PDT 24 |
33071259 ps |
| T986 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1594269534 |
|
|
Jun 25 04:52:10 PM PDT 24 |
Jun 25 04:52:15 PM PDT 24 |
1929141575 ps |
| T987 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2575346834 |
|
|
Jun 25 04:52:19 PM PDT 24 |
Jun 25 04:52:22 PM PDT 24 |
1743081982 ps |
| T988 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1251659458 |
|
|
Jun 25 04:52:10 PM PDT 24 |
Jun 25 04:52:14 PM PDT 24 |
2517449926 ps |
| T989 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.939820072 |
|
|
Jun 25 04:51:50 PM PDT 24 |
Jun 25 04:51:55 PM PDT 24 |
171321929 ps |
| T990 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3258719268 |
|
|
Jun 25 04:52:14 PM PDT 24 |
Jun 25 04:52:16 PM PDT 24 |
15385111 ps |
| T991 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3702726718 |
|
|
Jun 25 04:51:49 PM PDT 24 |
Jun 25 04:51:54 PM PDT 24 |
605423684 ps |
| T992 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3158955286 |
|
|
Jun 25 04:52:11 PM PDT 24 |
Jun 25 04:52:14 PM PDT 24 |
75463645 ps |
| T993 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4138549733 |
|
|
Jun 25 04:52:30 PM PDT 24 |
Jun 25 04:52:31 PM PDT 24 |
47070488 ps |
| T994 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2490956732 |
|
|
Jun 25 04:52:21 PM PDT 24 |
Jun 25 04:52:23 PM PDT 24 |
68547209 ps |
| T995 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.204755032 |
|
|
Jun 25 04:52:27 PM PDT 24 |
Jun 25 04:52:31 PM PDT 24 |
845182984 ps |
| T996 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3516552422 |
|
|
Jun 25 04:52:45 PM PDT 24 |
Jun 25 04:52:46 PM PDT 24 |
52813785 ps |
| T997 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1641832104 |
|
|
Jun 25 04:52:00 PM PDT 24 |
Jun 25 04:52:03 PM PDT 24 |
257891979 ps |
| T998 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1046209993 |
|
|
Jun 25 04:52:32 PM PDT 24 |
Jun 25 04:52:34 PM PDT 24 |
125680467 ps |
| T999 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.484842826 |
|
|
Jun 25 04:52:29 PM PDT 24 |
Jun 25 04:52:34 PM PDT 24 |
144274424 ps |
| T1000 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2792826604 |
|
|
Jun 25 04:51:52 PM PDT 24 |
Jun 25 04:51:54 PM PDT 24 |
15113193 ps |
| T1001 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4143061959 |
|
|
Jun 25 04:52:22 PM PDT 24 |
Jun 25 04:52:24 PM PDT 24 |
26908593 ps |
| T1002 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2688499033 |
|
|
Jun 25 04:52:01 PM PDT 24 |
Jun 25 04:52:03 PM PDT 24 |
16613746 ps |
| T122 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1357854066 |
|
|
Jun 25 04:52:12 PM PDT 24 |
Jun 25 04:52:15 PM PDT 24 |
130435257 ps |
| T1003 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2256050532 |
|
|
Jun 25 04:52:03 PM PDT 24 |
Jun 25 04:52:05 PM PDT 24 |
56468635 ps |
| T1004 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1886821577 |
|
|
Jun 25 04:51:51 PM PDT 24 |
Jun 25 04:51:53 PM PDT 24 |
41026507 ps |