SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 9 | 0 | 9 | 100.00 |
Crosses | 16 | 0 | 16 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
csr_exec_cp | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 | |
en_sram_ifetch_cp | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 | |
lc_hw_debug_en_cp | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
executable_cross | 16 | 0 | 16 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
instr_invalid_dis | 144418624 | 1 | T1 | 2158 | T2 | 8044 | T3 | 6142 | ||||
instr_valid_dis | 112026344 | 1 | T1 | 2158 | T2 | 8044 | T3 | 6142 | ||||
instr_en | 21238344 | 1 | T5 | 292956 | T10 | 67416 | T25 | 19298 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
sram_ifetch_invalid_disable | 11531939 | 1 | T5 | 53652 | T10 | 155356 | T25 | 133292 | ||||
sram_ifetch_valid_disable | 113328662 | 1 | T1 | 2158 | T2 | 8044 | T3 | 6142 | ||||
sram_ifetch_enable | 19558023 | 1 | T5 | 144910 | T10 | 62650 | T25 | 137062 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
hw_debug_en_invalid_off | 144418624 | 1 | T1 | 2158 | T2 | 8044 | T3 | 6142 | ||||
hw_debug_en_valid_off | 112809358 | 1 | T1 | 2158 | T2 | 8044 | T3 | 6142 | ||||
hw_debug_en_on | 21196286 | 1 | T5 | 94762 | T10 | 100424 | T25 | 235262 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 16 | 0 | 16 | 100.00 | |
Automatically Generated Cross Bins | 12 | 0 | 12 | 100.00 | |
User Defined Cross Bins | 4 | 0 | 4 | 100.00 |
lc_hw_debug_en_cp | en_sram_ifetch_cp | csr_exec_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
hw_debug_en_invalid_off | sram_ifetch_valid_disable | instr_invalid_dis | 113328662 | 1 | T1 | 2158 | T2 | 8044 | T3 | 6142 | ||||
hw_debug_en_invalid_off | sram_ifetch_valid_disable | instr_valid_dis | 99765064 | 1 | T1 | 2158 | T2 | 8044 | T3 | 6142 | ||||
hw_debug_en_invalid_off | sram_ifetch_valid_disable | instr_en | 8976612 | 1 | T5 | 197388 | T10 | 40258 | T24 | 2442 | ||||
hw_debug_en_valid_off | sram_ifetch_invalid_disable | instr_invalid_dis | 4372686 | 1 | T10 | 79730 | T25 | 306 | T18 | 17662 | ||||
hw_debug_en_valid_off | sram_ifetch_invalid_disable | instr_valid_dis | 1778122 | 1 | T10 | 72016 | T25 | 306 | T19 | 119116 | ||||
hw_debug_en_valid_off | sram_ifetch_invalid_disable | instr_en | 1603228 | 1 | T10 | 7714 | T18 | 17662 | T147 | 22268 | ||||
hw_debug_en_on | sram_ifetch_invalid_disable | instr_invalid_dis | 5154123 | 1 | T5 | 33652 | T10 | 44350 | T25 | 122948 | ||||
hw_debug_en_on | sram_ifetch_invalid_disable | instr_valid_dis | 1748537 | 1 | T25 | 103650 | T24 | 38229 | T147 | 30190 | ||||
hw_debug_en_on | sram_ifetch_invalid_disable | instr_en | 2171590 | 1 | T5 | 9118 | T25 | 19298 | T147 | 54890 | ||||
hw_debug_en_on | sram_ifetch_valid_disable | instr_invalid_dis | 8597972 | 1 | T5 | 29608 | T10 | 56074 | T25 | 72530 | ||||
hw_debug_en_on | sram_ifetch_valid_disable | instr_valid_dis | 3552825 | 1 | T25 | 72530 | T19 | 15806 | T6 | 22510 | ||||
hw_debug_en_on | sram_ifetch_valid_disable | instr_en | 3572657 | 1 | T5 | 24952 | T10 | 27632 | T24 | 2442 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
csr_exec_en | 7736284 | 1 | T5 | 66450 | T10 | 19444 | T24 | 13244 | ||||
lc_exec_en | 7444191 | 1 | T5 | 31502 | T25 | 39784 | T24 | 24407 | ||||
valid_exec_dis | 107906665 | 1 | T1 | 2158 | T2 | 8044 | T3 | 6142 | ||||
invalid_exec_dis | 31089962 | 1 | T5 | 198562 | T10 | 218006 | T25 | 270354 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |