Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	42823460	1			T2	897		T3	3071		T4	170440
triple_byte_access	2537746	1			T2	18		T4	3321		T5	4831
halfword_access	3807172	1			T2	31		T4	5157		T5	7422
byte_access	5088004	1			T2	43		T4	6866		T5	9952
zero_access	1278890	1			T2	10		T4	1730		T5	2466

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27722842

1

T2

509

T3

1024

T4

93842

auto[1]

27812430

1

T2

490

T3

2047

T4

93672

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21366770	1			T2	465		T3	1024		T4	85241
auto[0]	triple_byte_access	1266735	1			T2	5		T4	1704		T5	2408
auto[0]	halfword_access	1901288	1			T2	17		T4	2574		T5	3693
auto[0]	byte_access	2545576	1			T2	19		T4	3469		T5	5018
auto[0]	zero_access	642473	1			T2	3		T4	854		T5	1249
auto[1]	word_access	21456690	1			T2	432		T3	2047		T4	85199
auto[1]	triple_byte_access	1271011	1			T2	13		T4	1617		T5	2423
auto[1]	halfword_access	1905884	1			T2	14		T4	2583		T5	3729
auto[1]	byte_access	2542428	1			T2	24		T4	3397		T5	4934
auto[1]	zero_access	636417	1			T2	7		T4	876		T5	1217