Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	138564362	1			T1	5380		T2	262544		T5	20000
instr_valid_dis	108447364	1			T1	5380		T2	20004		T5	20000
instr_en	20618854	1			T2	242500		T23	300588		T21	7566

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9113749	1			T2	5454		T23	26718		T16	112995
sram_ifetch_valid_disable	109757200	1			T1	5380		T2	195140		T5	20000
sram_ifetch_enable	19693413	1			T2	61950		T23	180178		T21	7566

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	138564362	1			T1	5380		T2	262544		T5	20000
hw_debug_en_valid_off	109403441	1			T1	5380		T2	135066		T5	20000
hw_debug_en_on	19474031	1			T2	87004		T23	171924		T16	112995

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	109757200	1			T1	5380		T2	195140		T5	20000
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	97449331	1			T1	5380		T5	20000		T4	18440
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8593239	1			T2	195140		T23	93692		T33	39194
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3678820	1			T23	7474		T36	39826		T62	51016
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1291694	1			T63	20000		T145	10064		T146	3354
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1673578	1			T23	7474		T62	51016		T63	70704
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3578055	1			T16	112995		T17	194114		T62	26268
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	930849	1			T16	112995		T17	12694		T62	26268
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1511104	1			T17	61218		T147	15782		T116	8068
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8517176	1			T2	87004		T23	41092		T33	24720
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3325264	1			T33	11906		T36	90		T62	15146
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3674524	1			T2	87004		T23	41092		T17	115732

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8163109	1			T2	41906		T23	180178		T21	7566
lc_exec_en	7378800	1			T23	130832		T17	119964		T36	24780
valid_exec_dis	105356576	1			T1	5380		T2	128140		T5	20000
invalid_exec_dis	28807162	1			T2	67404		T23	206896		T21	7566