Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	41591713	1			T1	764		T2	47780		T5	10000
triple_byte_access	2499860	1			T1	18		T2	1009		T4	1544
halfword_access	3752236	1			T1	22		T2	1404		T4	2238
byte_access	5008666	1			T1	33		T2	1876		T4	3053
zero_access	1260918	1			T1	7		T2	473		T4	733

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26998053

1

T1

424

T2

26516

T5

5050

auto[1]

27115340

1

T1

420

T2

26026

T5

4950

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	20741189	1			T1	383		T2	24096		T5	5050
auto[0]	triple_byte_access	1247535	1			T1	10		T2	504		T4	780
auto[0]	halfword_access	1873049	1			T1	12		T2	734		T4	1110
auto[0]	byte_access	2502325	1			T1	15		T2	947		T4	1523
auto[0]	zero_access	633955	1			T1	4		T2	235		T4	349
auto[1]	word_access	20850524	1			T1	381		T2	23684		T5	4950
auto[1]	triple_byte_access	1252325	1			T1	8		T2	505		T4	764
auto[1]	halfword_access	1879187	1			T1	10		T2	670		T4	1128
auto[1]	byte_access	2506341	1			T1	18		T2	929		T4	1530
auto[1]	zero_access	626963	1			T1	3		T2	238		T4	384