Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14694053	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

61083180

1

T1

116855

T3

17039

T4

4303

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37761639	1			T1	64166		T3	8044		T4	2683
values[0x0]	17535961	1			T1	30935		T3	4956		T4	1234
values[0x1]	20479633	1			T1	33456		T3	5314		T4	1369

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7316147	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

68461086

1

T1

122698

T3

17698

T4

4782

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	265385	1			T1	339		T4	18		T5	76
valid_sources[0x01]	376310	1			T1	694		T4	19		T5	144
valid_sources[0x02]	361629	1			T1	556		T4	23		T5	95
valid_sources[0x03]	299654	1			T1	427		T4	22		T5	65
valid_sources[0x04]	286732	1			T1	530		T4	18		T5	154
valid_sources[0x05]	322287	1			T1	549		T4	26		T5	47
valid_sources[0x06]	263495	1			T1	483		T4	23		T5	81
valid_sources[0x07]	307651	1			T1	306		T4	16		T5	87
valid_sources[0x08]	281384	1			T1	569		T4	20		T5	70
valid_sources[0x09]	284634	1			T1	332		T4	12		T5	36
valid_sources[0x0a]	253881	1			T1	574		T4	19		T5	58
valid_sources[0x0b]	268230	1			T1	355		T4	15		T5	126
valid_sources[0x0c]	300601	1			T1	575		T4	14		T5	93
valid_sources[0x0d]	315869	1			T1	436		T4	13		T5	106
valid_sources[0x0e]	292994	1			T1	299		T4	18		T5	87
valid_sources[0x0f]	266196	1			T1	643		T4	30		T5	76
valid_sources[0x10]	259724	1			T1	470		T4	20		T5	62
valid_sources[0x11]	300646	1			T1	466		T4	21		T5	77
valid_sources[0x12]	302037	1			T1	682		T4	19		T5	29
valid_sources[0x13]	296916	1			T1	444		T4	16		T5	81
valid_sources[0x14]	267798	1			T1	466		T4	24		T5	86
valid_sources[0x15]	258202	1			T1	537		T4	24		T5	43
valid_sources[0x16]	283219	1			T1	708		T4	22		T5	85
valid_sources[0x17]	318880	1			T1	671		T4	24		T5	73
valid_sources[0x18]	335969	1			T1	700		T4	28		T5	128
valid_sources[0x19]	271102	1			T1	481		T4	21		T5	73
valid_sources[0x1a]	277264	1			T1	675		T4	22		T5	46
valid_sources[0x1b]	275039	1			T1	477		T4	23		T5	69
valid_sources[0x1c]	298799	1			T1	539		T4	32		T5	69
valid_sources[0x1d]	298534	1			T1	571		T4	18		T5	166
valid_sources[0x1e]	309879	1			T1	631		T4	17		T5	73
valid_sources[0x1f]	290277	1			T1	339		T4	13		T5	138
valid_sources[0x20]	308212	1			T1	502		T4	26		T5	128
valid_sources[0x21]	261106	1			T1	501		T3	23		T4	19
valid_sources[0x22]	288434	1			T1	452		T4	25		T5	139
valid_sources[0x23]	283660	1			T1	449		T4	19		T5	112
valid_sources[0x24]	334848	1			T1	381		T4	19		T5	51
valid_sources[0x25]	314677	1			T1	357		T4	13		T5	65
valid_sources[0x26]	267013	1			T1	790		T4	22		T5	93
valid_sources[0x27]	332310	1			T1	405		T4	19		T5	83
valid_sources[0x28]	292930	1			T1	571		T4	14		T5	68
valid_sources[0x29]	310384	1			T1	650		T4	29		T5	80
valid_sources[0x2a]	267197	1			T1	253		T4	26		T5	84
valid_sources[0x2b]	262851	1			T1	389		T4	20		T5	83
valid_sources[0x2c]	302117	1			T1	375		T3	327		T4	20
valid_sources[0x2d]	294947	1			T1	409		T4	19		T5	67
valid_sources[0x2e]	281827	1			T1	555		T4	15		T5	69
valid_sources[0x2f]	348994	1			T1	509		T4	18		T5	90
valid_sources[0x30]	304145	1			T1	414		T4	17		T5	72
valid_sources[0x31]	262672	1			T1	540		T4	16		T5	45
valid_sources[0x32]	284494	1			T1	549		T4	30		T5	62
valid_sources[0x33]	256655	1			T1	367		T4	26		T5	137
valid_sources[0x34]	299478	1			T1	716		T4	20		T5	38
valid_sources[0x35]	313546	1			T1	620		T4	22		T5	84
valid_sources[0x36]	321734	1			T1	585		T4	25		T5	79
valid_sources[0x37]	368652	1			T1	364		T3	335		T4	23
valid_sources[0x38]	272886	1			T1	417		T4	11		T5	85
valid_sources[0x39]	347491	1			T1	609		T4	23		T5	105
valid_sources[0x3a]	377029	1			T1	586		T4	21		T5	78
valid_sources[0x3b]	328911	1			T1	454		T4	23		T5	54
valid_sources[0x3c]	274904	1			T1	402		T4	22		T5	142
valid_sources[0x3d]	326994	1			T1	275		T4	18		T5	106
valid_sources[0x3e]	283824	1			T1	570		T4	24		T5	151
valid_sources[0x3f]	337200	1			T1	455		T4	19		T5	115
valid_sources[0x40]	301897	1			T1	300		T4	12		T5	125
valid_sources[0x41]	359697	1			T1	441		T4	23		T5	133
valid_sources[0x42]	294049	1			T1	679		T4	20		T5	8952
valid_sources[0x43]	256230	1			T1	575		T3	765		T4	20
valid_sources[0x44]	262696	1			T1	503		T4	18		T5	125
valid_sources[0x45]	265211	1			T1	493		T4	24		T5	153
valid_sources[0x46]	282888	1			T1	740		T4	27		T5	47
valid_sources[0x47]	290041	1			T1	636		T4	19		T5	58
valid_sources[0x48]	296815	1			T1	517		T3	5348		T4	22
valid_sources[0x49]	286067	1			T1	395		T4	20		T5	44
valid_sources[0x4a]	268975	1			T1	504		T4	19		T5	35
valid_sources[0x4b]	269604	1			T1	410		T4	22		T5	54
valid_sources[0x4c]	259025	1			T1	507		T3	943		T4	16
valid_sources[0x4d]	262463	1			T1	498		T4	13		T5	63
valid_sources[0x4e]	290354	1			T1	473		T4	20		T5	34
valid_sources[0x4f]	307248	1			T1	419		T4	22		T5	108
valid_sources[0x50]	311595	1			T1	520		T4	16		T5	54
valid_sources[0x51]	337410	1			T1	366		T4	14		T5	88
valid_sources[0x52]	260859	1			T1	487		T4	18		T5	113
valid_sources[0x53]	314427	1			T1	509		T4	20		T5	89
valid_sources[0x54]	265684	1			T1	399		T4	28		T5	71
valid_sources[0x55]	301039	1			T1	795		T4	37		T5	125
valid_sources[0x56]	257638	1			T1	526		T4	12		T5	54
valid_sources[0x57]	305641	1			T1	489		T4	22		T5	52
valid_sources[0x58]	264864	1			T1	480		T4	20		T5	136
valid_sources[0x59]	282461	1			T1	384		T4	19		T5	71
valid_sources[0x5a]	266052	1			T1	560		T4	15		T5	93
valid_sources[0x5b]	297770	1			T1	469		T4	18		T5	68
valid_sources[0x5c]	284884	1			T1	525		T4	22		T5	83
valid_sources[0x5d]	254654	1			T1	354		T4	21		T5	40
valid_sources[0x5e]	257774	1			T1	515		T4	24		T5	43
valid_sources[0x5f]	307679	1			T1	869		T4	18		T5	90
valid_sources[0x60]	282149	1			T1	334		T4	17		T5	82
valid_sources[0x61]	354325	1			T1	631		T4	13		T5	104
valid_sources[0x62]	325257	1			T1	442		T4	18		T5	133
valid_sources[0x63]	299898	1			T1	562		T4	25		T5	72
valid_sources[0x64]	286797	1			T1	345		T4	21		T5	111
valid_sources[0x65]	273852	1			T1	328		T3	114		T4	23
valid_sources[0x66]	268199	1			T1	666		T4	27		T5	56
valid_sources[0x67]	318857	1			T1	518		T3	1914		T4	21
valid_sources[0x68]	284177	1			T1	551		T4	18		T5	86
valid_sources[0x69]	359845	1			T1	529		T4	19		T5	87
valid_sources[0x6a]	273005	1			T1	352		T4	18		T5	108
valid_sources[0x6b]	279185	1			T1	459		T4	22		T5	92
valid_sources[0x6c]	257112	1			T1	587		T4	27		T5	112
valid_sources[0x6d]	312434	1			T1	448		T4	26		T5	71
valid_sources[0x6e]	318149	1			T1	467		T4	25		T5	45
valid_sources[0x6f]	291714	1			T1	309		T4	19		T5	86
valid_sources[0x70]	300244	1			T1	601		T4	16		T5	115
valid_sources[0x71]	297462	1			T1	466		T4	33		T5	32
valid_sources[0x72]	296946	1			T1	695		T4	25		T5	91
valid_sources[0x73]	267773	1			T1	500		T4	24		T5	113
valid_sources[0x74]	280193	1			T1	493		T4	18		T5	75
valid_sources[0x75]	299537	1			T1	485		T4	18		T5	78
valid_sources[0x76]	312382	1			T1	688		T4	27		T5	139
valid_sources[0x77]	284520	1			T1	548		T4	22		T5	46
valid_sources[0x78]	292891	1			T1	645		T4	20		T5	45
valid_sources[0x79]	298691	1			T1	632		T4	30		T5	66
valid_sources[0x7a]	288467	1			T1	389		T4	22		T5	92
valid_sources[0x7b]	300549	1			T1	453		T4	27		T5	80
valid_sources[0x7c]	268066	1			T1	589		T4	21		T5	87
valid_sources[0x7d]	269315	1			T1	411		T4	26		T5	62
valid_sources[0x7e]	269844	1			T1	510		T4	22		T5	85
valid_sources[0x7f]	303273	1			T1	713		T4	15		T5	66
valid_sources[0x80]	285947	1			T1	750		T4	25		T5	76

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30421411

1

T1

58377

T3

7426

T4

2191

values[0x0]

all_enables

biggest_size

15332284

1

T1

29173

T3

4753

T4

1086

values[0x1]

all_enables

biggest_size

15329485

1

T1

29305

T3

4860

T4

1026

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38895	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

164707

1

T1

17

T3

2871

T5

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	58133	1			T1	13		T3	786		T5	8
values[0x0]	69958	1			T1	22		T3	1097		T4	1
values[0x1]	75511	1			T1	30		T2	1		T3	1197

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29112	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

174490

1

T1

27

T3

2975

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	694	1			T1	2		T3	12		T27	8
valid_sources[0x01]	769	1			T3	13		T24	5		T27	22
valid_sources[0x02]	659	1			T3	17		T27	17		T64	1
valid_sources[0x03]	570	1			T3	12		T74	1		T27	4
valid_sources[0x04]	845	1			T3	19		T24	13		T130	1
valid_sources[0x05]	661	1			T3	17		T24	1		T142	2
valid_sources[0x06]	800	1			T3	18		T24	13		T15	1
valid_sources[0x07]	791	1			T3	16		T24	3		T21	1
valid_sources[0x08]	573	1			T3	5		T27	38		T64	1
valid_sources[0x09]	679	1			T3	11		T27	6		T64	1
valid_sources[0x0a]	710	1			T3	14		T24	4		T8	35
valid_sources[0x0b]	692	1			T3	13		T21	1		T133	1
valid_sources[0x0c]	816	1			T3	11		T24	6		T27	10
valid_sources[0x0d]	635	1			T3	9		T50	1		T27	16
valid_sources[0x0e]	831	1			T1	2		T3	15		T27	48
valid_sources[0x0f]	1130	1			T3	19		T11	14		T24	2
valid_sources[0x10]	990	1			T3	13		T27	27		T129	1
valid_sources[0x11]	1172	1			T3	8		T130	1		T27	28
valid_sources[0x12]	791	1			T3	6		T24	4		T27	47
valid_sources[0x13]	584	1			T3	9		T40	2		T41	1
valid_sources[0x14]	620	1			T3	18		T42	7		T24	17
valid_sources[0x15]	615	1			T3	12		T21	1		T133	3
valid_sources[0x16]	797	1			T3	13		T24	15		T27	30
valid_sources[0x17]	731	1			T3	9		T27	1		T46	9
valid_sources[0x18]	809	1			T1	1		T3	12		T27	8
valid_sources[0x19]	995	1			T1	2		T3	19		T27	31
valid_sources[0x1a]	643	1			T3	8		T143	1		T27	6
valid_sources[0x1b]	917	1			T3	10		T27	23		T15	1
valid_sources[0x1c]	889	1			T3	11		T27	8		T63	1
valid_sources[0x1d]	877	1			T3	7		T27	5		T21	1
valid_sources[0x1e]	772	1			T3	14		T45	4		T27	4
valid_sources[0x1f]	906	1			T3	11		T24	14		T27	8
valid_sources[0x20]	589	1			T1	1		T3	15		T24	1
valid_sources[0x21]	721	1			T1	1		T3	13		T24	4
valid_sources[0x22]	754	1			T3	8		T27	6		T21	1
valid_sources[0x23]	580	1			T3	14		T76	5		T27	9
valid_sources[0x24]	1117	1			T3	11		T24	8		T27	52
valid_sources[0x25]	758	1			T3	14		T27	2		T63	2
valid_sources[0x26]	888	1			T3	7		T27	11		T63	1
valid_sources[0x27]	751	1			T3	13		T24	3		T64	1
valid_sources[0x28]	596	1			T3	21		T24	13		T27	2
valid_sources[0x29]	678	1			T3	15		T27	13		T144	1
valid_sources[0x2a]	796	1			T2	1		T3	14		T26	1
valid_sources[0x2b]	599	1			T3	15		T27	20		T15	1
valid_sources[0x2c]	781	1			T3	17		T24	5		T27	1
valid_sources[0x2d]	801	1			T3	17		T24	4		T145	1
valid_sources[0x2e]	579	1			T3	12		T76	3		T27	6
valid_sources[0x2f]	828	1			T3	13		T27	5		T21	2
valid_sources[0x30]	527	1			T1	1		T3	14		T12	1
valid_sources[0x31]	779	1			T3	8		T27	23		T46	21
valid_sources[0x32]	968	1			T3	10		T27	19		T64	1
valid_sources[0x33]	578	1			T3	16		T50	1		T24	2
valid_sources[0x34]	647	1			T3	17		T27	5		T46	14
valid_sources[0x35]	672	1			T3	14		T27	2		T64	3
valid_sources[0x36]	664	1			T3	7		T27	28		T63	1
valid_sources[0x37]	780	1			T1	1		T3	17		T75	1
valid_sources[0x38]	711	1			T3	6		T27	9		T46	15
valid_sources[0x39]	897	1			T1	3		T3	11		T27	1
valid_sources[0x3a]	811	1			T3	21		T24	1		T27	4
valid_sources[0x3b]	854	1			T3	22		T27	29		T15	1
valid_sources[0x3c]	1055	1			T3	10		T74	1		T24	1
valid_sources[0x3d]	637	1			T3	7		T10	1		T6	10
valid_sources[0x3e]	788	1			T3	12		T24	5		T27	11
valid_sources[0x3f]	840	1			T3	8		T24	1		T27	26
valid_sources[0x40]	558	1			T3	11		T11	2		T74	1
valid_sources[0x41]	835	1			T3	12		T24	17		T8	4
valid_sources[0x42]	759	1			T3	8		T27	11		T46	24
valid_sources[0x43]	668	1			T3	8		T27	8		T46	16
valid_sources[0x44]	935	1			T3	19		T27	3		T64	2
valid_sources[0x45]	520	1			T3	12		T12	3		T27	9
valid_sources[0x46]	805	1			T1	1		T3	11		T74	1
valid_sources[0x47]	850	1			T3	14		T27	29		T64	3
valid_sources[0x48]	923	1			T3	11		T11	1		T24	6
valid_sources[0x49]	910	1			T3	8		T24	18		T27	51
valid_sources[0x4a]	1009	1			T1	1		T3	12		T13	1
valid_sources[0x4b]	971	1			T1	1		T3	13		T24	2
valid_sources[0x4c]	871	1			T3	5		T27	48		T49	1
valid_sources[0x4d]	677	1			T3	5		T27	1		T21	1
valid_sources[0x4e]	888	1			T3	7		T24	11		T27	2
valid_sources[0x4f]	803	1			T3	10		T21	2		T64	1
valid_sources[0x50]	726	1			T3	9		T130	2		T27	13
valid_sources[0x51]	604	1			T3	13		T77	1		T27	3
valid_sources[0x52]	926	1			T3	7		T11	1		T24	2
valid_sources[0x53]	626	1			T3	7		T24	11		T27	10
valid_sources[0x54]	730	1			T3	6		T27	7		T15	1
valid_sources[0x55]	716	1			T3	19		T40	1		T27	1
valid_sources[0x56]	833	1			T3	11		T27	31		T146	1
valid_sources[0x57]	598	1			T3	10		T130	2		T27	22
valid_sources[0x58]	1121	1			T3	12		T27	37		T63	2
valid_sources[0x59]	845	1			T1	1		T3	7		T27	33
valid_sources[0x5a]	628	1			T3	9		T21	3		T46	20
valid_sources[0x5b]	856	1			T3	9		T27	1		T46	20
valid_sources[0x5c]	597	1			T3	12		T24	20		T130	1
valid_sources[0x5d]	897	1			T3	9		T40	1		T15	2
valid_sources[0x5e]	614	1			T3	14		T41	1		T24	8
valid_sources[0x5f]	690	1			T3	8		T24	5		T27	1
valid_sources[0x60]	746	1			T1	1		T3	14		T27	12
valid_sources[0x61]	660	1			T3	12		T24	14		T27	6
valid_sources[0x62]	893	1			T3	13		T27	1		T49	1
valid_sources[0x63]	707	1			T3	17		T130	1		T27	1
valid_sources[0x64]	991	1			T3	12		T27	3		T64	1
valid_sources[0x65]	998	1			T1	1		T3	11		T27	28
valid_sources[0x66]	878	1			T3	14		T27	31		T64	1
valid_sources[0x67]	732	1			T3	16		T24	1		T27	7
valid_sources[0x68]	896	1			T3	7		T75	1		T24	8
valid_sources[0x69]	738	1			T3	15		T27	35		T15	1
valid_sources[0x6a]	1151	1			T1	2		T3	11		T74	1
valid_sources[0x6b]	809	1			T3	14		T24	3		T46	21
valid_sources[0x6c]	731	1			T3	10		T4	2		T75	1
valid_sources[0x6d]	715	1			T3	9		T41	1		T27	1
valid_sources[0x6e]	745	1			T1	1		T3	8		T130	1
valid_sources[0x6f]	769	1			T3	10		T85	2		T27	9
valid_sources[0x70]	804	1			T3	11		T27	9		T64	1
valid_sources[0x71]	1258	1			T3	16		T5	44		T12	2
valid_sources[0x72]	644	1			T3	15		T24	24		T27	26
valid_sources[0x73]	657	1			T1	2		T3	8		T27	15
valid_sources[0x74]	729	1			T3	16		T74	1		T27	29
valid_sources[0x75]	841	1			T3	9		T130	3		T27	9
valid_sources[0x76]	972	1			T1	1		T3	14		T27	39
valid_sources[0x77]	716	1			T3	13		T24	6		T63	1
valid_sources[0x78]	706	1			T1	1		T3	18		T24	11
valid_sources[0x79]	579	1			T3	14		T24	25		T27	2
valid_sources[0x7a]	801	1			T3	10		T24	6		T27	6
valid_sources[0x7b]	1368	1			T3	15		T74	2		T77	1
valid_sources[0x7c]	673	1			T3	10		T24	16		T27	29
valid_sources[0x7d]	914	1			T1	1		T3	19		T24	4
valid_sources[0x7e]	824	1			T3	13		T24	3		T27	3
valid_sources[0x7f]	657	1			T3	10		T24	35		T21	1
valid_sources[0x80]	728	1			T1	1		T3	6		T27	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44827

1

T1

5

T3

707

T5

4

values[0x0]

all_enables

biggest_size

61061

1

T1

10

T3

1079

T5

4

values[0x1]

all_enables

biggest_size

58819

1

T1

2

T3

1085

T5

4