Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14422583

1

T1

9389

T3

3845

T4

983

full_word

55978560

1

T1

93436

T3

14984

T4

4303

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	70400873	1			T1	102825		T3	18829		T4	5286
auto[TlIntgErrCmd]	86	1			T56	5		T57	5		T58	6
auto[TlIntgErrData]	92	1			T56	2		T57	11		T58	7
auto[TlIntgErrBoth]	92	1			T56	3		T57	4		T58	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32273498

1

T1

38434

T3

6079

T4

2683

auto[1]

38127645

1

T1

64391

T3

12750

T4

2603

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6885176	1			T1	3476		T3	968		T4	492
auto[TlIntgErrNone]	partial	auto[1]	7537159	1			T1	5913		T3	2877		T4	491
auto[TlIntgErrNone]	full_word	auto[0]	25388199	1			T1	34958		T3	5111		T4	2191
auto[TlIntgErrNone]	full_word	auto[1]	30590339	1			T1	58478		T3	9873		T4	2112
auto[TlIntgErrCmd]	partial	auto[0]	29	1			T56	2		T58	2		T121	3
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T56	3		T57	3		T58	4
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T121	1		T123	2		T125	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T57	2		T122	1		-	-
auto[TlIntgErrData]	partial	auto[0]	37	1			T56	1		T57	3		T58	3
auto[TlIntgErrData]	partial	auto[1]	48	1			T56	1		T57	6		T58	4
auto[TlIntgErrData]	full_word	auto[0]	1	1			T57	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T57	1		T123	1		T126	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T56	2		T57	1		T58	3
auto[TlIntgErrBoth]	partial	auto[1]	39	1			T56	1		T57	3		T58	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T58	2		T127	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T128	2		T124	1		-	-