Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	714138	1			T1	16		T5	469		T11	2300
auto[1]	11137883	1			T1	301		T3	2		T4	2683
auto[2]	591400	1			T1	18		T5	477		T11	2130
auto[3]	11025764	1			T1	300		T4	2602		T5	64

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14848269	1			T1	453		T3	1		T4	3522
auto[1]	2278007	1			T1	66		T3	1		T4	780
auto[2]	2288630	1			T1	106		T4	798		T5	117
auto[3]	4054279	1			T1	10		T4	185		T5	11

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9411294

1

T1

634

T3

2

T4

5279

auto[1]

14057891

1

T1

1

T4

6

T5

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	260054	1			T1	11		T5	393		T11	1892
auto[0]	auto[0]	auto[1]	27587	1			T1	4		T5	35		T11	198
auto[0]	auto[0]	auto[2]	27603	1			T1	1		T5	39		T11	187
auto[0]	auto[0]	auto[3]	10140	1			T5	2		T11	18		T12	97
auto[0]	auto[1]	auto[0]	3617125	1			T1	230		T3	1		T4	1806
auto[0]	auto[1]	auto[1]	371397	1			T1	48		T3	1		T4	383
auto[0]	auto[1]	auto[2]	364586	1			T1	22		T4	401		T5	6
auto[0]	auto[1]	auto[3]	69919	1			T1	1		T4	91		T5	1
auto[0]	auto[2]	auto[0]	222827	1			T5	396		T11	1746		T12	7135
auto[0]	auto[2]	auto[1]	23374	1			T5	38		T11	199		T12	757
auto[0]	auto[2]	auto[2]	24551	1			T1	17		T5	38		T11	168
auto[0]	auto[2]	auto[3]	8057	1			T1	1		T5	4		T11	17
auto[0]	auto[3]	auto[0]	3579741	1			T1	211		T4	1713		T5	23
auto[0]	auto[3]	auto[1]	361614	1			T1	14		T4	396		T5	3
auto[0]	auto[3]	auto[2]	371355	1			T1	66		T4	395		T5	34
auto[0]	auto[3]	auto[3]	71364	1			T1	8		T4	94		T5	4
auto[1]	auto[0]	auto[0]	13071	1			T11	5		T12	8		T103	429
auto[1]	auto[0]	auto[1]	57924	1			T12	2		T103	1854		T137	1
auto[1]	auto[0]	auto[2]	58086	1			T103	1853		T64	1		T138	1
auto[1]	auto[0]	auto[3]	259673	1			T103	8367		T139	2		T140	1
auto[1]	auto[1]	auto[0]	3574869	1			T4	1		T11	1		T12	2
auto[1]	auto[1]	auto[1]	708401	1			T4	1		T12	1		T13	15516
auto[1]	auto[1]	auto[2]	698277	1			T13	17576		T41	4972		T25	5
auto[1]	auto[1]	auto[3]	1733309	1			T13	69374		T41	528		T25	1
auto[1]	auto[2]	auto[0]	9907	1			T5	1		T12	4		T103	241
auto[1]	auto[2]	auto[1]	43327	1			T12	1		T103	1193		T63	1
auto[1]	auto[2]	auto[2]	46793	1			T74	1		T7	1		T103	1744
auto[1]	auto[2]	auto[3]	212564	1			T103	8057		T139	1		T135	6740
auto[1]	auto[3]	auto[0]	3570675	1			T1	1		T4	2		T12	1
auto[1]	auto[3]	auto[1]	684383	1			T13	17244		T41	4872		T25	9
auto[1]	auto[3]	auto[2]	697379	1			T4	2		T13	15446		T41	4911
auto[1]	auto[3]	auto[3]	1689253	1			T13	69484		T41	468		T25	1