Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	301666155	255316	0	0
ctrl_regwen_rd_A	301666155	4250	0	0
exec_rd_A	301666155	4095	0	0
exec_regwen_rd_A	301666155	4392	0	0
readback_rd_A	301666155	2419	0	0
readback_regwen_rd_A	301666155	2375	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301666155	255316	0	0
T3	142244	4020	0	0
T4	10252	0	0	0
T5	693522	0	0	0
T9	3508	0	0	0
T10	2647	0	0	0
T11	186299	0	0	0
T12	163323	0	0	0
T13	538589	0	0	0
T24	0	628	0	0
T27	0	5194	0	0
T40	44501	0	0	0
T41	175102	0	0	0
T46	0	5783	0	0
T47	0	3275	0	0
T48	0	1970	0	0
T52	0	3507	0	0
T53	0	6756	0	0
T54	0	6920	0	0
T61	0	3029	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301666155	4250	0	0
T16	1061	0	0	0
T22	224257	0	0	0
T46	170726	457	0	0
T47	133071	0	0	0
T48	0	222	0	0
T61	0	265	0	0
T106	251683	0	0	0
T107	683874	0	0	0
T110	0	254	0	0
T111	0	153	0	0
T112	0	344	0	0
T113	0	50	0	0
T114	0	258	0	0
T115	0	193	0	0
T116	0	179	0	0
T117	30769	0	0	0
T118	302725	0	0	0
T119	258923	0	0	0
T120	258265	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301666155	4095	0	0
T16	1061	0	0	0
T22	224257	0	0	0
T46	170726	401	0	0
T47	133071	0	0	0
T48	0	181	0	0
T61	0	187	0	0
T106	251683	0	0	0
T107	683874	0	0	0
T110	0	293	0	0
T111	0	181	0	0
T112	0	333	0	0
T113	0	32	0	0
T114	0	125	0	0
T115	0	197	0	0
T116	0	229	0	0
T117	30769	0	0	0
T118	302725	0	0	0
T119	258923	0	0	0
T120	258265	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301666155	4392	0	0
T16	1061	0	0	0
T22	224257	0	0	0
T46	170726	510	0	0
T47	133071	0	0	0
T48	0	172	0	0
T61	0	160	0	0
T106	251683	0	0	0
T107	683874	0	0	0
T110	0	306	0	0
T111	0	173	0	0
T112	0	404	0	0
T113	0	40	0	0
T114	0	191	0	0
T115	0	295	0	0
T116	0	244	0	0
T117	30769	0	0	0
T118	302725	0	0	0
T119	258923	0	0	0
T120	258265	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301666155	2419	0	0
T16	1061	0	0	0
T22	224257	0	0	0
T46	170726	350	0	0
T47	133071	0	0	0
T48	0	108	0	0
T61	0	191	0	0
T106	251683	0	0	0
T107	683874	0	0	0
T110	0	307	0	0
T111	0	62	0	0
T112	0	284	0	0
T113	0	40	0	0
T114	0	224	0	0
T115	0	256	0	0
T116	0	242	0	0
T117	30769	0	0	0
T118	302725	0	0	0
T119	258923	0	0	0
T120	258265	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301666155	2375	0	0
T16	1061	0	0	0
T22	224257	0	0	0
T46	170726	398	0	0
T47	133071	0	0	0
T48	0	105	0	0
T61	0	174	0	0
T106	251683	0	0	0
T107	683874	0	0	0
T110	0	259	0	0
T111	0	140	0	0
T112	0	291	0	0
T113	0	24	0	0
T114	0	152	0	0
T115	0	237	0	0
T116	0	152	0	0
T117	30769	0	0	0
T118	302725	0	0	0
T119	258923	0	0	0
T120	258265	0	0	0