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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44


Total test records in report: 1033
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html

T302 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2122378286 Jun 28 04:36:19 PM PDT 24 Jun 28 04:45:21 PM PDT 24 111574603229 ps
T303 /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1644763993 Jun 28 04:34:27 PM PDT 24 Jun 28 04:35:07 PM PDT 24 221245014 ps
T304 /workspace/coverage/default/22.sram_ctrl_multiple_keys.2609690757 Jun 28 04:34:36 PM PDT 24 Jun 28 04:59:34 PM PDT 24 4281716894 ps
T305 /workspace/coverage/default/12.sram_ctrl_stress_pipeline.659584915 Jun 28 04:34:04 PM PDT 24 Jun 28 04:37:48 PM PDT 24 12575644171 ps
T306 /workspace/coverage/default/9.sram_ctrl_executable.2252012155 Jun 28 04:34:02 PM PDT 24 Jun 28 04:34:40 PM PDT 24 883721059 ps
T307 /workspace/coverage/default/21.sram_ctrl_executable.3759891603 Jun 28 04:34:43 PM PDT 24 Jun 28 04:57:50 PM PDT 24 87565586275 ps
T308 /workspace/coverage/default/10.sram_ctrl_stress_pipeline.677964804 Jun 28 04:34:09 PM PDT 24 Jun 28 04:39:07 PM PDT 24 5220681031 ps
T309 /workspace/coverage/default/5.sram_ctrl_bijection.4178481294 Jun 28 04:33:53 PM PDT 24 Jun 28 04:35:25 PM PDT 24 4697374015 ps
T310 /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2122196758 Jun 28 04:36:16 PM PDT 24 Jun 28 04:37:18 PM PDT 24 381349600 ps
T311 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2978450159 Jun 28 04:36:05 PM PDT 24 Jun 28 04:36:11 PM PDT 24 404546087 ps
T312 /workspace/coverage/default/16.sram_ctrl_multiple_keys.2542591977 Jun 28 04:34:27 PM PDT 24 Jun 28 04:46:32 PM PDT 24 16289066120 ps
T313 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1415074297 Jun 28 04:33:55 PM PDT 24 Jun 28 04:41:02 PM PDT 24 34780489192 ps
T314 /workspace/coverage/default/9.sram_ctrl_max_throughput.2762740765 Jun 28 04:34:05 PM PDT 24 Jun 28 04:35:28 PM PDT 24 455451860 ps
T315 /workspace/coverage/default/33.sram_ctrl_alert_test.1040018627 Jun 28 04:35:25 PM PDT 24 Jun 28 04:35:27 PM PDT 24 40920112 ps
T316 /workspace/coverage/default/17.sram_ctrl_regwen.1907810741 Jun 28 04:34:27 PM PDT 24 Jun 28 04:53:45 PM PDT 24 3474887534 ps
T317 /workspace/coverage/default/19.sram_ctrl_alert_test.2146343440 Jun 28 04:34:23 PM PDT 24 Jun 28 04:34:26 PM PDT 24 40240284 ps
T318 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3899362396 Jun 28 04:36:30 PM PDT 24 Jun 28 04:36:34 PM PDT 24 168121677 ps
T319 /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.2761328377 Jun 28 04:35:08 PM PDT 24 Jun 28 04:37:44 PM PDT 24 607572130 ps
T320 /workspace/coverage/default/43.sram_ctrl_mem_walk.247733739 Jun 28 04:36:06 PM PDT 24 Jun 28 04:36:17 PM PDT 24 443162650 ps
T321 /workspace/coverage/default/12.sram_ctrl_lc_escalation.2271964934 Jun 28 04:34:04 PM PDT 24 Jun 28 04:34:17 PM PDT 24 1348066681 ps
T322 /workspace/coverage/default/16.sram_ctrl_max_throughput.4206908174 Jun 28 04:34:24 PM PDT 24 Jun 28 04:34:26 PM PDT 24 106428499 ps
T323 /workspace/coverage/default/34.sram_ctrl_access_during_key_req.3968251563 Jun 28 04:35:21 PM PDT 24 Jun 28 04:39:26 PM PDT 24 2320978427 ps
T324 /workspace/coverage/default/15.sram_ctrl_alert_test.1352917597 Jun 28 04:34:30 PM PDT 24 Jun 28 04:34:31 PM PDT 24 19202140 ps
T325 /workspace/coverage/default/41.sram_ctrl_partial_access.2284862761 Jun 28 04:35:38 PM PDT 24 Jun 28 04:35:41 PM PDT 24 45241540 ps
T326 /workspace/coverage/default/32.sram_ctrl_mem_walk.1168794312 Jun 28 04:35:09 PM PDT 24 Jun 28 04:35:19 PM PDT 24 550268182 ps
T327 /workspace/coverage/default/40.sram_ctrl_access_during_key_req.2795974641 Jun 28 04:35:39 PM PDT 24 Jun 28 04:46:48 PM PDT 24 28773320950 ps
T328 /workspace/coverage/default/5.sram_ctrl_regwen.2189814376 Jun 28 04:33:53 PM PDT 24 Jun 28 04:51:13 PM PDT 24 6537580326 ps
T329 /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2945519697 Jun 28 04:36:06 PM PDT 24 Jun 28 04:38:38 PM PDT 24 4688082458 ps
T330 /workspace/coverage/default/14.sram_ctrl_regwen.1813750393 Jun 28 04:34:17 PM PDT 24 Jun 28 04:58:46 PM PDT 24 29029570959 ps
T331 /workspace/coverage/default/8.sram_ctrl_multiple_keys.1202458287 Jun 28 04:34:00 PM PDT 24 Jun 28 04:44:42 PM PDT 24 7119281965 ps
T332 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.639295318 Jun 28 04:36:05 PM PDT 24 Jun 28 04:44:52 PM PDT 24 41805992723 ps
T333 /workspace/coverage/default/14.sram_ctrl_lc_escalation.2685537794 Jun 28 04:34:16 PM PDT 24 Jun 28 04:34:30 PM PDT 24 2558334922 ps
T334 /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1618659512 Jun 28 04:36:18 PM PDT 24 Jun 28 04:41:11 PM PDT 24 48283451806 ps
T335 /workspace/coverage/default/42.sram_ctrl_alert_test.2539531131 Jun 28 04:35:53 PM PDT 24 Jun 28 04:35:55 PM PDT 24 15520396 ps
T336 /workspace/coverage/default/5.sram_ctrl_stress_all.3468107831 Jun 28 04:33:51 PM PDT 24 Jun 28 05:26:35 PM PDT 24 8693245216 ps
T337 /workspace/coverage/default/11.sram_ctrl_alert_test.3395020031 Jun 28 04:34:08 PM PDT 24 Jun 28 04:34:15 PM PDT 24 25524632 ps
T338 /workspace/coverage/default/25.sram_ctrl_max_throughput.3927184414 Jun 28 04:34:55 PM PDT 24 Jun 28 04:35:05 PM PDT 24 229281380 ps
T339 /workspace/coverage/default/5.sram_ctrl_lc_escalation.4121416866 Jun 28 04:33:51 PM PDT 24 Jun 28 04:34:02 PM PDT 24 2938532791 ps
T340 /workspace/coverage/default/27.sram_ctrl_alert_test.398631973 Jun 28 04:34:58 PM PDT 24 Jun 28 04:35:00 PM PDT 24 11234077 ps
T341 /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.100536385 Jun 28 04:33:51 PM PDT 24 Jun 28 04:41:47 PM PDT 24 13579689395 ps
T342 /workspace/coverage/default/0.sram_ctrl_regwen.742937460 Jun 28 04:33:23 PM PDT 24 Jun 28 04:39:09 PM PDT 24 5752200060 ps
T343 /workspace/coverage/default/12.sram_ctrl_partial_access.1306837606 Jun 28 04:34:07 PM PDT 24 Jun 28 04:36:04 PM PDT 24 676289707 ps
T344 /workspace/coverage/default/2.sram_ctrl_ram_cfg.2315726992 Jun 28 04:33:41 PM PDT 24 Jun 28 04:33:44 PM PDT 24 83932505 ps
T111 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1945284203 Jun 28 04:34:15 PM PDT 24 Jun 28 04:34:33 PM PDT 24 478830618 ps
T345 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.2911711283 Jun 28 04:35:50 PM PDT 24 Jun 28 04:35:54 PM PDT 24 373813501 ps
T346 /workspace/coverage/default/28.sram_ctrl_ram_cfg.2085003944 Jun 28 04:35:01 PM PDT 24 Jun 28 04:35:03 PM PDT 24 100776244 ps
T347 /workspace/coverage/default/39.sram_ctrl_access_during_key_req.1740338655 Jun 28 04:35:29 PM PDT 24 Jun 28 04:54:26 PM PDT 24 13117596327 ps
T348 /workspace/coverage/default/23.sram_ctrl_multiple_keys.3917489099 Jun 28 04:34:39 PM PDT 24 Jun 28 04:52:13 PM PDT 24 6053405064 ps
T349 /workspace/coverage/default/12.sram_ctrl_executable.44200415 Jun 28 04:34:18 PM PDT 24 Jun 28 04:51:11 PM PDT 24 14582673536 ps
T350 /workspace/coverage/default/5.sram_ctrl_mem_walk.1997752223 Jun 28 04:33:51 PM PDT 24 Jun 28 04:33:59 PM PDT 24 1117824062 ps
T112 /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3705909732 Jun 28 04:34:35 PM PDT 24 Jun 28 04:35:22 PM PDT 24 6058720865 ps
T351 /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.1609679754 Jun 28 04:35:32 PM PDT 24 Jun 28 04:37:12 PM PDT 24 556082045 ps
T352 /workspace/coverage/default/5.sram_ctrl_partial_access.1647870513 Jun 28 04:33:51 PM PDT 24 Jun 28 04:34:50 PM PDT 24 560095175 ps
T353 /workspace/coverage/default/32.sram_ctrl_ram_cfg.1458100898 Jun 28 04:35:10 PM PDT 24 Jun 28 04:35:13 PM PDT 24 27464222 ps
T354 /workspace/coverage/default/32.sram_ctrl_multiple_keys.782136109 Jun 28 04:35:11 PM PDT 24 Jun 28 04:51:26 PM PDT 24 8260426250 ps
T355 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.4137737592 Jun 28 04:34:04 PM PDT 24 Jun 28 04:34:15 PM PDT 24 257072114 ps
T356 /workspace/coverage/default/28.sram_ctrl_bijection.3419126258 Jun 28 04:35:05 PM PDT 24 Jun 28 04:36:11 PM PDT 24 9314410463 ps
T113 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.144262003 Jun 28 04:34:26 PM PDT 24 Jun 28 04:34:37 PM PDT 24 963669823 ps
T357 /workspace/coverage/default/32.sram_ctrl_max_throughput.1380280778 Jun 28 04:35:11 PM PDT 24 Jun 28 04:35:56 PM PDT 24 378929750 ps
T358 /workspace/coverage/default/9.sram_ctrl_smoke.950792266 Jun 28 04:34:04 PM PDT 24 Jun 28 04:34:23 PM PDT 24 1256662603 ps
T359 /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3885988191 Jun 28 04:35:52 PM PDT 24 Jun 28 04:37:02 PM PDT 24 487617160 ps
T360 /workspace/coverage/default/19.sram_ctrl_lc_escalation.89844114 Jun 28 04:34:26 PM PDT 24 Jun 28 04:34:32 PM PDT 24 974918489 ps
T361 /workspace/coverage/default/33.sram_ctrl_partial_access.2192288840 Jun 28 04:35:08 PM PDT 24 Jun 28 04:35:14 PM PDT 24 358009506 ps
T362 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1355154425 Jun 28 04:35:13 PM PDT 24 Jun 28 04:42:31 PM PDT 24 173060622065 ps
T363 /workspace/coverage/default/37.sram_ctrl_multiple_keys.62191237 Jun 28 04:35:29 PM PDT 24 Jun 28 04:55:16 PM PDT 24 5355520600 ps
T364 /workspace/coverage/default/6.sram_ctrl_regwen.3859416819 Jun 28 04:33:55 PM PDT 24 Jun 28 04:41:07 PM PDT 24 1582409932 ps
T365 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.505197792 Jun 28 04:35:24 PM PDT 24 Jun 28 04:35:31 PM PDT 24 1824042698 ps
T366 /workspace/coverage/default/19.sram_ctrl_partial_access.2713207367 Jun 28 04:34:27 PM PDT 24 Jun 28 04:34:38 PM PDT 24 1825696011 ps
T367 /workspace/coverage/default/24.sram_ctrl_access_during_key_req.3606543971 Jun 28 04:34:55 PM PDT 24 Jun 28 04:35:29 PM PDT 24 550319961 ps
T368 /workspace/coverage/default/9.sram_ctrl_mem_walk.4293259510 Jun 28 04:34:09 PM PDT 24 Jun 28 04:34:28 PM PDT 24 584278765 ps
T369 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.3807967392 Jun 28 04:36:18 PM PDT 24 Jun 28 04:38:42 PM PDT 24 817287049 ps
T370 /workspace/coverage/default/39.sram_ctrl_mem_walk.2308130336 Jun 28 04:35:38 PM PDT 24 Jun 28 04:35:44 PM PDT 24 237579809 ps
T371 /workspace/coverage/default/29.sram_ctrl_partial_access.2954457529 Jun 28 04:35:01 PM PDT 24 Jun 28 04:36:43 PM PDT 24 2675702235 ps
T372 /workspace/coverage/default/22.sram_ctrl_executable.1537144640 Jun 28 04:34:36 PM PDT 24 Jun 28 04:42:19 PM PDT 24 9954460582 ps
T373 /workspace/coverage/default/0.sram_ctrl_max_throughput.2130674410 Jun 28 04:33:25 PM PDT 24 Jun 28 04:33:28 PM PDT 24 143049896 ps
T374 /workspace/coverage/default/47.sram_ctrl_mem_walk.115946717 Jun 28 04:36:17 PM PDT 24 Jun 28 04:36:29 PM PDT 24 1360367883 ps
T375 /workspace/coverage/default/42.sram_ctrl_regwen.3047399425 Jun 28 04:35:50 PM PDT 24 Jun 28 04:51:55 PM PDT 24 7354883326 ps
T376 /workspace/coverage/default/47.sram_ctrl_executable.1064033637 Jun 28 04:36:31 PM PDT 24 Jun 28 04:49:50 PM PDT 24 46225765713 ps
T377 /workspace/coverage/default/46.sram_ctrl_ram_cfg.3118155322 Jun 28 04:36:17 PM PDT 24 Jun 28 04:36:20 PM PDT 24 38639709 ps
T378 /workspace/coverage/default/11.sram_ctrl_stress_pipeline.862625085 Jun 28 04:34:08 PM PDT 24 Jun 28 04:38:16 PM PDT 24 4766103696 ps
T379 /workspace/coverage/default/3.sram_ctrl_smoke.569120308 Jun 28 04:33:41 PM PDT 24 Jun 28 04:33:46 PM PDT 24 69459484 ps
T380 /workspace/coverage/default/49.sram_ctrl_alert_test.37587771 Jun 28 04:36:28 PM PDT 24 Jun 28 04:36:29 PM PDT 24 15679078 ps
T381 /workspace/coverage/default/3.sram_ctrl_lc_escalation.917138179 Jun 28 04:33:49 PM PDT 24 Jun 28 04:33:57 PM PDT 24 1069261148 ps
T382 /workspace/coverage/default/10.sram_ctrl_executable.2051834978 Jun 28 04:34:05 PM PDT 24 Jun 28 04:37:20 PM PDT 24 13761296246 ps
T383 /workspace/coverage/default/27.sram_ctrl_lc_escalation.50343251 Jun 28 04:34:52 PM PDT 24 Jun 28 04:35:00 PM PDT 24 589781995 ps
T384 /workspace/coverage/default/18.sram_ctrl_mem_partial_access.377915955 Jun 28 04:34:23 PM PDT 24 Jun 28 04:34:28 PM PDT 24 178865480 ps
T385 /workspace/coverage/default/0.sram_ctrl_partial_access.577574387 Jun 28 04:33:38 PM PDT 24 Jun 28 04:33:54 PM PDT 24 102518612 ps
T386 /workspace/coverage/default/43.sram_ctrl_multiple_keys.180841991 Jun 28 04:35:50 PM PDT 24 Jun 28 04:41:38 PM PDT 24 14180761958 ps
T387 /workspace/coverage/default/21.sram_ctrl_bijection.3279899179 Jun 28 04:34:44 PM PDT 24 Jun 28 04:35:26 PM PDT 24 675452289 ps
T388 /workspace/coverage/default/18.sram_ctrl_stress_pipeline.2622349560 Jun 28 04:34:28 PM PDT 24 Jun 28 04:36:21 PM PDT 24 3182634250 ps
T389 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.154613063 Jun 28 04:35:54 PM PDT 24 Jun 28 04:42:42 PM PDT 24 7739219376 ps
T390 /workspace/coverage/default/25.sram_ctrl_executable.2312866516 Jun 28 04:34:57 PM PDT 24 Jun 28 04:55:36 PM PDT 24 51028538854 ps
T391 /workspace/coverage/default/44.sram_ctrl_access_during_key_req.1516158491 Jun 28 04:36:08 PM PDT 24 Jun 28 04:47:18 PM PDT 24 31693912436 ps
T392 /workspace/coverage/default/38.sram_ctrl_max_throughput.1609080413 Jun 28 04:35:31 PM PDT 24 Jun 28 04:37:23 PM PDT 24 171190714 ps
T393 /workspace/coverage/default/26.sram_ctrl_mem_walk.265491792 Jun 28 04:34:51 PM PDT 24 Jun 28 04:35:01 PM PDT 24 139267026 ps
T394 /workspace/coverage/default/14.sram_ctrl_max_throughput.4026684055 Jun 28 04:34:18 PM PDT 24 Jun 28 04:36:26 PM PDT 24 921387169 ps
T395 /workspace/coverage/default/4.sram_ctrl_stress_pipeline.1687329395 Jun 28 04:33:38 PM PDT 24 Jun 28 04:36:27 PM PDT 24 1809155628 ps
T396 /workspace/coverage/default/12.sram_ctrl_bijection.2454443126 Jun 28 04:34:08 PM PDT 24 Jun 28 04:34:46 PM PDT 24 7560615392 ps
T397 /workspace/coverage/default/9.sram_ctrl_multiple_keys.3569791479 Jun 28 04:34:06 PM PDT 24 Jun 28 05:01:54 PM PDT 24 14791349239 ps
T398 /workspace/coverage/default/25.sram_ctrl_lc_escalation.1809518763 Jun 28 04:34:49 PM PDT 24 Jun 28 04:34:56 PM PDT 24 1766548519 ps
T399 /workspace/coverage/default/40.sram_ctrl_bijection.1091257683 Jun 28 04:35:39 PM PDT 24 Jun 28 04:36:42 PM PDT 24 7070231935 ps
T400 /workspace/coverage/default/23.sram_ctrl_partial_access.571781649 Jun 28 04:34:54 PM PDT 24 Jun 28 04:35:17 PM PDT 24 565130451 ps
T401 /workspace/coverage/default/18.sram_ctrl_access_during_key_req.2708464117 Jun 28 04:34:27 PM PDT 24 Jun 28 04:42:28 PM PDT 24 2824785311 ps
T402 /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.10176170 Jun 28 04:34:47 PM PDT 24 Jun 28 04:34:49 PM PDT 24 50484014 ps
T403 /workspace/coverage/default/2.sram_ctrl_partial_access.1804346151 Jun 28 04:33:28 PM PDT 24 Jun 28 04:33:41 PM PDT 24 176292213 ps
T404 /workspace/coverage/default/30.sram_ctrl_stress_pipeline.2154794593 Jun 28 04:35:14 PM PDT 24 Jun 28 04:38:19 PM PDT 24 2314285402 ps
T405 /workspace/coverage/default/14.sram_ctrl_partial_access.2179825701 Jun 28 04:34:18 PM PDT 24 Jun 28 04:34:37 PM PDT 24 87790182 ps
T406 /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3042930326 Jun 28 04:36:16 PM PDT 24 Jun 28 04:43:36 PM PDT 24 6738578258 ps
T407 /workspace/coverage/default/10.sram_ctrl_regwen.2678504806 Jun 28 04:34:06 PM PDT 24 Jun 28 04:49:58 PM PDT 24 10733165515 ps
T408 /workspace/coverage/default/33.sram_ctrl_executable.164765284 Jun 28 04:35:10 PM PDT 24 Jun 28 04:46:55 PM PDT 24 2218356385 ps
T409 /workspace/coverage/default/1.sram_ctrl_bijection.101026608 Jun 28 04:33:32 PM PDT 24 Jun 28 04:34:47 PM PDT 24 12718459370 ps
T410 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1376301420 Jun 28 04:34:14 PM PDT 24 Jun 28 04:36:38 PM PDT 24 5959268335 ps
T411 /workspace/coverage/default/43.sram_ctrl_smoke.4177175997 Jun 28 04:35:51 PM PDT 24 Jun 28 04:35:58 PM PDT 24 136784931 ps
T412 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.1112552330 Jun 28 04:35:50 PM PDT 24 Jun 28 04:35:57 PM PDT 24 162698609 ps
T413 /workspace/coverage/default/49.sram_ctrl_mem_walk.2640374021 Jun 28 04:36:30 PM PDT 24 Jun 28 04:36:39 PM PDT 24 138644849 ps
T414 /workspace/coverage/default/6.sram_ctrl_multiple_keys.3156194092 Jun 28 04:33:53 PM PDT 24 Jun 28 05:01:44 PM PDT 24 8384542664 ps
T415 /workspace/coverage/default/29.sram_ctrl_smoke.3047440422 Jun 28 04:35:12 PM PDT 24 Jun 28 04:35:16 PM PDT 24 307788292 ps
T416 /workspace/coverage/default/12.sram_ctrl_stress_all.2185668957 Jun 28 04:34:17 PM PDT 24 Jun 28 05:46:55 PM PDT 24 73051932934 ps
T417 /workspace/coverage/default/3.sram_ctrl_alert_test.1274521554 Jun 28 04:33:48 PM PDT 24 Jun 28 04:33:49 PM PDT 24 37240113 ps
T418 /workspace/coverage/default/47.sram_ctrl_bijection.2763726513 Jun 28 04:36:15 PM PDT 24 Jun 28 04:37:12 PM PDT 24 2471026321 ps
T419 /workspace/coverage/default/3.sram_ctrl_mem_walk.2887212000 Jun 28 04:33:41 PM PDT 24 Jun 28 04:33:53 PM PDT 24 459441260 ps
T420 /workspace/coverage/default/27.sram_ctrl_access_during_key_req.1911783929 Jun 28 04:34:49 PM PDT 24 Jun 28 04:50:37 PM PDT 24 5916620467 ps
T421 /workspace/coverage/default/41.sram_ctrl_lc_escalation.2729389201 Jun 28 04:35:38 PM PDT 24 Jun 28 04:35:43 PM PDT 24 510384692 ps
T422 /workspace/coverage/default/42.sram_ctrl_access_during_key_req.2769606568 Jun 28 04:35:51 PM PDT 24 Jun 28 04:47:01 PM PDT 24 2554499571 ps
T423 /workspace/coverage/default/4.sram_ctrl_multiple_keys.4170648802 Jun 28 04:33:39 PM PDT 24 Jun 28 04:46:06 PM PDT 24 4317040578 ps
T424 /workspace/coverage/default/8.sram_ctrl_access_during_key_req.682996353 Jun 28 04:34:04 PM PDT 24 Jun 28 04:43:22 PM PDT 24 13544375967 ps
T425 /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2425312206 Jun 28 04:34:25 PM PDT 24 Jun 28 04:36:01 PM PDT 24 2279551481 ps
T426 /workspace/coverage/default/7.sram_ctrl_multiple_keys.3474810785 Jun 28 04:33:59 PM PDT 24 Jun 28 04:50:04 PM PDT 24 141012514535 ps
T427 /workspace/coverage/default/40.sram_ctrl_ram_cfg.628957987 Jun 28 04:35:39 PM PDT 24 Jun 28 04:35:41 PM PDT 24 41911559 ps
T428 /workspace/coverage/default/47.sram_ctrl_access_during_key_req.410481635 Jun 28 04:36:17 PM PDT 24 Jun 28 04:48:25 PM PDT 24 6720105238 ps
T429 /workspace/coverage/default/6.sram_ctrl_stress_all.1108918785 Jun 28 04:33:55 PM PDT 24 Jun 28 06:03:16 PM PDT 24 179570497372 ps
T430 /workspace/coverage/default/49.sram_ctrl_multiple_keys.1255369802 Jun 28 04:36:20 PM PDT 24 Jun 28 04:49:36 PM PDT 24 30962711056 ps
T431 /workspace/coverage/default/38.sram_ctrl_mem_walk.703709835 Jun 28 04:35:31 PM PDT 24 Jun 28 04:35:40 PM PDT 24 141694532 ps
T432 /workspace/coverage/default/6.sram_ctrl_stress_pipeline.1163644535 Jun 28 04:33:53 PM PDT 24 Jun 28 04:37:29 PM PDT 24 4618451077 ps
T433 /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3577937450 Jun 28 04:35:51 PM PDT 24 Jun 28 04:37:09 PM PDT 24 249511123 ps
T434 /workspace/coverage/default/47.sram_ctrl_regwen.827531282 Jun 28 04:36:18 PM PDT 24 Jun 28 04:39:41 PM PDT 24 30161031821 ps
T435 /workspace/coverage/default/9.sram_ctrl_ram_cfg.1976740831 Jun 28 04:34:11 PM PDT 24 Jun 28 04:34:18 PM PDT 24 85550780 ps
T436 /workspace/coverage/default/1.sram_ctrl_access_during_key_req.6368490 Jun 28 04:33:26 PM PDT 24 Jun 28 04:41:13 PM PDT 24 9000422684 ps
T437 /workspace/coverage/default/5.sram_ctrl_access_during_key_req.940212569 Jun 28 04:33:54 PM PDT 24 Jun 28 04:51:38 PM PDT 24 6298412737 ps
T438 /workspace/coverage/default/4.sram_ctrl_lc_escalation.2662479473 Jun 28 04:33:43 PM PDT 24 Jun 28 04:33:48 PM PDT 24 323324768 ps
T439 /workspace/coverage/default/40.sram_ctrl_stress_all.2738506945 Jun 28 04:35:40 PM PDT 24 Jun 28 04:53:23 PM PDT 24 4173509536 ps
T440 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.4123354167 Jun 28 04:34:07 PM PDT 24 Jun 28 04:34:19 PM PDT 24 198084416 ps
T441 /workspace/coverage/default/2.sram_ctrl_smoke.1045301425 Jun 28 04:33:27 PM PDT 24 Jun 28 04:33:30 PM PDT 24 103194194 ps
T442 /workspace/coverage/default/35.sram_ctrl_mem_walk.4010118180 Jun 28 04:35:22 PM PDT 24 Jun 28 04:35:29 PM PDT 24 241778018 ps
T443 /workspace/coverage/default/23.sram_ctrl_lc_escalation.3952599675 Jun 28 04:34:44 PM PDT 24 Jun 28 04:34:55 PM PDT 24 1824853387 ps
T444 /workspace/coverage/default/42.sram_ctrl_executable.556816704 Jun 28 04:35:53 PM PDT 24 Jun 28 04:52:18 PM PDT 24 3647621166 ps
T445 /workspace/coverage/default/15.sram_ctrl_mem_partial_access.4045492386 Jun 28 04:34:19 PM PDT 24 Jun 28 04:34:26 PM PDT 24 67117922 ps
T446 /workspace/coverage/default/14.sram_ctrl_alert_test.2769408283 Jun 28 04:34:14 PM PDT 24 Jun 28 04:34:21 PM PDT 24 213894645 ps
T447 /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.810030816 Jun 28 04:35:13 PM PDT 24 Jun 28 04:35:47 PM PDT 24 1336712045 ps
T448 /workspace/coverage/default/39.sram_ctrl_partial_access.1094787945 Jun 28 04:35:30 PM PDT 24 Jun 28 04:35:33 PM PDT 24 570044550 ps
T449 /workspace/coverage/default/5.sram_ctrl_mem_partial_access.2046372340 Jun 28 04:33:52 PM PDT 24 Jun 28 04:34:00 PM PDT 24 170768957 ps
T450 /workspace/coverage/default/19.sram_ctrl_executable.1776855648 Jun 28 04:34:33 PM PDT 24 Jun 28 04:37:42 PM PDT 24 3624508044 ps
T451 /workspace/coverage/default/24.sram_ctrl_stress_pipeline.1763984218 Jun 28 04:34:47 PM PDT 24 Jun 28 04:38:40 PM PDT 24 9787815094 ps
T452 /workspace/coverage/default/47.sram_ctrl_smoke.1982033103 Jun 28 04:36:20 PM PDT 24 Jun 28 04:36:34 PM PDT 24 3082435912 ps
T453 /workspace/coverage/default/4.sram_ctrl_max_throughput.896537060 Jun 28 04:33:45 PM PDT 24 Jun 28 04:34:39 PM PDT 24 110944380 ps
T454 /workspace/coverage/default/0.sram_ctrl_alert_test.4188856957 Jun 28 04:33:29 PM PDT 24 Jun 28 04:33:31 PM PDT 24 18362581 ps
T455 /workspace/coverage/default/6.sram_ctrl_partial_access.2731861392 Jun 28 04:33:53 PM PDT 24 Jun 28 04:34:17 PM PDT 24 1022385706 ps
T456 /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1126546926 Jun 28 04:36:06 PM PDT 24 Jun 28 04:37:03 PM PDT 24 1776928713 ps
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T458 /workspace/coverage/default/14.sram_ctrl_mem_walk.3245019163 Jun 28 04:34:17 PM PDT 24 Jun 28 04:34:33 PM PDT 24 1537926678 ps
T459 /workspace/coverage/default/20.sram_ctrl_stress_pipeline.2500079597 Jun 28 04:34:41 PM PDT 24 Jun 28 04:37:34 PM PDT 24 1826395346 ps
T460 /workspace/coverage/default/49.sram_ctrl_partial_access.1205527570 Jun 28 04:36:16 PM PDT 24 Jun 28 04:36:23 PM PDT 24 232670010 ps
T461 /workspace/coverage/default/13.sram_ctrl_multiple_keys.702153469 Jun 28 04:34:13 PM PDT 24 Jun 28 04:41:40 PM PDT 24 11826760976 ps
T462 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.2672612542 Jun 28 04:35:03 PM PDT 24 Jun 28 04:35:06 PM PDT 24 98327441 ps
T463 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.10196030 Jun 28 04:34:59 PM PDT 24 Jun 28 04:35:05 PM PDT 24 312533980 ps
T464 /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.4099936732 Jun 28 04:35:22 PM PDT 24 Jun 28 04:37:47 PM PDT 24 171326296 ps
T465 /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3940289630 Jun 28 04:35:29 PM PDT 24 Jun 28 04:36:05 PM PDT 24 529110803 ps
T466 /workspace/coverage/default/19.sram_ctrl_ram_cfg.670495956 Jun 28 04:34:27 PM PDT 24 Jun 28 04:34:30 PM PDT 24 26420665 ps
T467 /workspace/coverage/default/39.sram_ctrl_alert_test.251155646 Jun 28 04:35:39 PM PDT 24 Jun 28 04:35:40 PM PDT 24 13596124 ps
T468 /workspace/coverage/default/15.sram_ctrl_mem_walk.3169170406 Jun 28 04:34:16 PM PDT 24 Jun 28 04:34:26 PM PDT 24 92066283 ps
T469 /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3031606383 Jun 28 04:34:43 PM PDT 24 Jun 28 04:35:03 PM PDT 24 400305963 ps
T470 /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.2492482545 Jun 28 04:34:34 PM PDT 24 Jun 28 04:36:28 PM PDT 24 161633204 ps
T471 /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.3135693539 Jun 28 04:35:10 PM PDT 24 Jun 28 04:42:51 PM PDT 24 19452627180 ps
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T473 /workspace/coverage/default/3.sram_ctrl_access_during_key_req.532178390 Jun 28 04:33:45 PM PDT 24 Jun 28 04:41:45 PM PDT 24 8029084670 ps
T474 /workspace/coverage/default/10.sram_ctrl_smoke.3388339984 Jun 28 04:34:06 PM PDT 24 Jun 28 04:34:49 PM PDT 24 601661631 ps
T475 /workspace/coverage/default/0.sram_ctrl_stress_pipeline.3045978996 Jun 28 04:33:23 PM PDT 24 Jun 28 04:39:17 PM PDT 24 3597089153 ps
T476 /workspace/coverage/default/44.sram_ctrl_partial_access.3772801826 Jun 28 04:36:10 PM PDT 24 Jun 28 04:36:20 PM PDT 24 584480831 ps
T477 /workspace/coverage/default/15.sram_ctrl_stress_all.1510256163 Jun 28 04:34:25 PM PDT 24 Jun 28 05:03:30 PM PDT 24 85387611092 ps
T478 /workspace/coverage/default/9.sram_ctrl_regwen.1809848300 Jun 28 04:34:05 PM PDT 24 Jun 28 04:49:58 PM PDT 24 52813482644 ps
T479 /workspace/coverage/default/47.sram_ctrl_ram_cfg.2000006137 Jun 28 04:36:18 PM PDT 24 Jun 28 04:36:20 PM PDT 24 113531151 ps
T480 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.1086652437 Jun 28 04:35:05 PM PDT 24 Jun 28 04:40:19 PM PDT 24 15714295224 ps
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T482 /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2894754598 Jun 28 04:34:56 PM PDT 24 Jun 28 04:40:00 PM PDT 24 58150030080 ps
T483 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.1160197489 Jun 28 04:35:35 PM PDT 24 Jun 28 04:37:10 PM PDT 24 151244128 ps
T484 /workspace/coverage/default/12.sram_ctrl_mem_partial_access.3720842379 Jun 28 04:34:19 PM PDT 24 Jun 28 04:34:27 PM PDT 24 69615587 ps
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T487 /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2680663015 Jun 28 04:33:50 PM PDT 24 Jun 28 04:37:56 PM PDT 24 618216340 ps
T488 /workspace/coverage/default/45.sram_ctrl_partial_access.3156709899 Jun 28 04:36:08 PM PDT 24 Jun 28 04:36:29 PM PDT 24 629116623 ps
T489 /workspace/coverage/default/13.sram_ctrl_partial_access.4017825288 Jun 28 04:34:17 PM PDT 24 Jun 28 04:34:30 PM PDT 24 1507259476 ps
T490 /workspace/coverage/default/35.sram_ctrl_multiple_keys.222800621 Jun 28 04:35:24 PM PDT 24 Jun 28 04:46:17 PM PDT 24 13195776639 ps
T491 /workspace/coverage/default/42.sram_ctrl_mem_walk.2832854116 Jun 28 04:35:51 PM PDT 24 Jun 28 04:35:59 PM PDT 24 231458318 ps
T492 /workspace/coverage/default/49.sram_ctrl_ram_cfg.345727488 Jun 28 04:36:31 PM PDT 24 Jun 28 04:36:33 PM PDT 24 27383296 ps
T493 /workspace/coverage/default/16.sram_ctrl_ram_cfg.73998051 Jun 28 04:34:24 PM PDT 24 Jun 28 04:34:27 PM PDT 24 232829988 ps
T494 /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.4207901318 Jun 28 04:34:42 PM PDT 24 Jun 28 04:34:51 PM PDT 24 63557257 ps
T495 /workspace/coverage/default/33.sram_ctrl_multiple_keys.3584059437 Jun 28 04:35:12 PM PDT 24 Jun 28 04:46:52 PM PDT 24 43858266297 ps
T496 /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.3824181484 Jun 28 04:34:55 PM PDT 24 Jun 28 04:37:14 PM PDT 24 932549882 ps
T497 /workspace/coverage/default/45.sram_ctrl_regwen.3555636109 Jun 28 04:36:08 PM PDT 24 Jun 28 04:43:53 PM PDT 24 32790202414 ps
T498 /workspace/coverage/default/21.sram_ctrl_stress_all.3418024829 Jun 28 04:34:42 PM PDT 24 Jun 28 05:24:08 PM PDT 24 7619606562 ps
T499 /workspace/coverage/default/18.sram_ctrl_multiple_keys.721367681 Jun 28 04:34:33 PM PDT 24 Jun 28 05:06:43 PM PDT 24 40047329521 ps
T500 /workspace/coverage/default/47.sram_ctrl_multiple_keys.612508722 Jun 28 04:36:17 PM PDT 24 Jun 28 04:52:49 PM PDT 24 3419771486 ps
T501 /workspace/coverage/default/8.sram_ctrl_ram_cfg.2820958296 Jun 28 04:34:10 PM PDT 24 Jun 28 04:34:17 PM PDT 24 83398493 ps
T502 /workspace/coverage/default/3.sram_ctrl_stress_pipeline.3950771248 Jun 28 04:33:38 PM PDT 24 Jun 28 04:36:49 PM PDT 24 13440026970 ps
T503 /workspace/coverage/default/33.sram_ctrl_bijection.2007088601 Jun 28 04:35:09 PM PDT 24 Jun 28 04:36:31 PM PDT 24 11034426557 ps
T29 /workspace/coverage/default/3.sram_ctrl_sec_cm.2364682631 Jun 28 04:33:43 PM PDT 24 Jun 28 04:33:46 PM PDT 24 129894430 ps
T504 /workspace/coverage/default/29.sram_ctrl_lc_escalation.2246802251 Jun 28 04:35:11 PM PDT 24 Jun 28 04:35:20 PM PDT 24 2051981568 ps
T505 /workspace/coverage/default/20.sram_ctrl_multiple_keys.492624320 Jun 28 04:34:36 PM PDT 24 Jun 28 04:45:52 PM PDT 24 42425464220 ps
T506 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3874597669 Jun 28 04:36:06 PM PDT 24 Jun 28 04:43:49 PM PDT 24 33432144941 ps
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T508 /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3762968619 Jun 28 04:35:09 PM PDT 24 Jun 28 04:39:57 PM PDT 24 3151122922 ps
T509 /workspace/coverage/default/11.sram_ctrl_smoke.1037761465 Jun 28 04:34:12 PM PDT 24 Jun 28 04:34:19 PM PDT 24 68528830 ps
T510 /workspace/coverage/default/7.sram_ctrl_stress_pipeline.306792064 Jun 28 04:33:55 PM PDT 24 Jun 28 04:37:41 PM PDT 24 20042122211 ps
T511 /workspace/coverage/default/28.sram_ctrl_mem_walk.4121726878 Jun 28 04:35:04 PM PDT 24 Jun 28 04:35:13 PM PDT 24 134324182 ps
T512 /workspace/coverage/default/42.sram_ctrl_bijection.1682569933 Jun 28 04:35:52 PM PDT 24 Jun 28 04:36:12 PM PDT 24 521492379 ps
T513 /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3288276465 Jun 28 04:34:58 PM PDT 24 Jun 28 04:38:24 PM PDT 24 5023508530 ps
T514 /workspace/coverage/default/1.sram_ctrl_alert_test.361566742 Jun 28 04:33:38 PM PDT 24 Jun 28 04:33:41 PM PDT 24 46803123 ps
T515 /workspace/coverage/default/31.sram_ctrl_access_during_key_req.4208072835 Jun 28 04:35:10 PM PDT 24 Jun 28 04:38:30 PM PDT 24 3441945941 ps
T516 /workspace/coverage/default/20.sram_ctrl_alert_test.168410613 Jun 28 04:34:35 PM PDT 24 Jun 28 04:34:37 PM PDT 24 63648730 ps
T517 /workspace/coverage/default/4.sram_ctrl_stress_all.873747321 Jun 28 04:33:45 PM PDT 24 Jun 28 05:25:05 PM PDT 24 9993169076 ps
T518 /workspace/coverage/default/20.sram_ctrl_max_throughput.1298999383 Jun 28 04:34:36 PM PDT 24 Jun 28 04:36:03 PM PDT 24 114657904 ps
T519 /workspace/coverage/default/17.sram_ctrl_alert_test.3705391085 Jun 28 04:34:29 PM PDT 24 Jun 28 04:34:31 PM PDT 24 44700530 ps
T520 /workspace/coverage/default/43.sram_ctrl_mem_partial_access.4014690621 Jun 28 04:36:08 PM PDT 24 Jun 28 04:36:14 PM PDT 24 146010356 ps
T521 /workspace/coverage/default/16.sram_ctrl_stress_pipeline.2177684418 Jun 28 04:34:25 PM PDT 24 Jun 28 04:38:51 PM PDT 24 9987584826 ps
T114 /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.132377560 Jun 28 04:35:21 PM PDT 24 Jun 28 04:36:24 PM PDT 24 1008712560 ps
T522 /workspace/coverage/default/2.sram_ctrl_mem_walk.4010754101 Jun 28 04:33:39 PM PDT 24 Jun 28 04:33:46 PM PDT 24 240239577 ps
T523 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.1379448581 Jun 28 04:34:50 PM PDT 24 Jun 28 04:34:54 PM PDT 24 114572846 ps
T524 /workspace/coverage/default/47.sram_ctrl_max_throughput.612653554 Jun 28 04:36:18 PM PDT 24 Jun 28 04:37:07 PM PDT 24 101473610 ps
T525 /workspace/coverage/default/9.sram_ctrl_access_during_key_req.556320007 Jun 28 04:34:03 PM PDT 24 Jun 28 04:36:38 PM PDT 24 1903559749 ps
T526 /workspace/coverage/default/22.sram_ctrl_ram_cfg.2477846245 Jun 28 04:34:37 PM PDT 24 Jun 28 04:34:39 PM PDT 24 89362198 ps
T527 /workspace/coverage/default/26.sram_ctrl_ram_cfg.1704763783 Jun 28 04:34:54 PM PDT 24 Jun 28 04:34:55 PM PDT 24 90926392 ps
T528 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3719209842 Jun 28 04:35:39 PM PDT 24 Jun 28 04:38:14 PM PDT 24 2176697010 ps
T529 /workspace/coverage/default/34.sram_ctrl_mem_partial_access.2775554567 Jun 28 04:35:21 PM PDT 24 Jun 28 04:35:28 PM PDT 24 584284449 ps
T530 /workspace/coverage/default/24.sram_ctrl_regwen.2570601064 Jun 28 04:34:47 PM PDT 24 Jun 28 04:36:22 PM PDT 24 269910689 ps
T531 /workspace/coverage/default/10.sram_ctrl_max_throughput.2745021565 Jun 28 04:34:05 PM PDT 24 Jun 28 04:34:41 PM PDT 24 307356697 ps
T532 /workspace/coverage/default/45.sram_ctrl_mem_walk.143983991 Jun 28 04:36:05 PM PDT 24 Jun 28 04:36:15 PM PDT 24 879887557 ps
T533 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.2845753170 Jun 28 04:35:51 PM PDT 24 Jun 28 04:35:58 PM PDT 24 67436729 ps
T534 /workspace/coverage/default/46.sram_ctrl_mem_walk.1707624141 Jun 28 04:36:17 PM PDT 24 Jun 28 04:36:23 PM PDT 24 98280210 ps
T535 /workspace/coverage/default/3.sram_ctrl_executable.1983676901 Jun 28 04:33:40 PM PDT 24 Jun 28 04:44:23 PM PDT 24 9024340866 ps
T536 /workspace/coverage/default/24.sram_ctrl_partial_access.1728706300 Jun 28 04:34:57 PM PDT 24 Jun 28 04:35:01 PM PDT 24 285798020 ps
T537 /workspace/coverage/default/22.sram_ctrl_stress_all.985213702 Jun 28 04:34:36 PM PDT 24 Jun 28 05:14:36 PM PDT 24 9550391775 ps
T538 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.3637508706 Jun 28 04:35:32 PM PDT 24 Jun 28 04:39:29 PM PDT 24 9872104587 ps
T539 /workspace/coverage/default/9.sram_ctrl_stress_all.590509654 Jun 28 04:34:05 PM PDT 24 Jun 28 05:04:40 PM PDT 24 25978129040 ps
T540 /workspace/coverage/default/16.sram_ctrl_executable.1969825345 Jun 28 04:34:24 PM PDT 24 Jun 28 04:38:04 PM PDT 24 10405324989 ps
T541 /workspace/coverage/default/7.sram_ctrl_bijection.3547204048 Jun 28 04:33:57 PM PDT 24 Jun 28 04:34:48 PM PDT 24 653733478 ps
T542 /workspace/coverage/default/16.sram_ctrl_mem_walk.118957695 Jun 28 04:34:26 PM PDT 24 Jun 28 04:34:34 PM PDT 24 373300149 ps
T543 /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.960745226 Jun 28 04:34:56 PM PDT 24 Jun 28 04:42:25 PM PDT 24 13409110629 ps
T544 /workspace/coverage/default/31.sram_ctrl_partial_access.909909546 Jun 28 04:35:10 PM PDT 24 Jun 28 04:35:27 PM PDT 24 571164480 ps
T545 /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.1075911156 Jun 28 04:34:51 PM PDT 24 Jun 28 04:35:04 PM PDT 24 86775616 ps
T546 /workspace/coverage/default/22.sram_ctrl_partial_access.1098098328 Jun 28 04:34:38 PM PDT 24 Jun 28 04:37:06 PM PDT 24 893894415 ps
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