| T793 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1772951023 |
|
|
Jun 28 04:33:35 PM PDT 24 |
Jun 28 04:34:04 PM PDT 24 |
106397308 ps |
| T794 |
/workspace/coverage/default/14.sram_ctrl_stress_all.1246177610 |
|
|
Jun 28 04:34:19 PM PDT 24 |
Jun 28 05:15:51 PM PDT 24 |
40944957153 ps |
| T795 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.964317458 |
|
|
Jun 28 04:34:25 PM PDT 24 |
Jun 28 04:38:12 PM PDT 24 |
2370927658 ps |
| T796 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3288513270 |
|
|
Jun 28 04:34:09 PM PDT 24 |
Jun 28 04:35:20 PM PDT 24 |
788476417 ps |
| T797 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.1007947487 |
|
|
Jun 28 04:35:39 PM PDT 24 |
Jun 28 04:40:07 PM PDT 24 |
2921154518 ps |
| T798 |
/workspace/coverage/default/31.sram_ctrl_executable.908682312 |
|
|
Jun 28 04:35:11 PM PDT 24 |
Jun 28 04:47:38 PM PDT 24 |
10726530639 ps |
| T799 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1193530644 |
|
|
Jun 28 04:34:08 PM PDT 24 |
Jun 28 04:40:58 PM PDT 24 |
10713699609 ps |
| T800 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.2663923859 |
|
|
Jun 28 04:34:18 PM PDT 24 |
Jun 28 04:35:53 PM PDT 24 |
133579335 ps |
| T801 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.1100399376 |
|
|
Jun 28 04:35:50 PM PDT 24 |
Jun 28 04:35:52 PM PDT 24 |
31651081 ps |
| T802 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.386572684 |
|
|
Jun 28 04:34:19 PM PDT 24 |
Jun 28 04:34:25 PM PDT 24 |
184898039 ps |
| T803 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.4036910386 |
|
|
Jun 28 04:34:33 PM PDT 24 |
Jun 28 04:34:40 PM PDT 24 |
60301230 ps |
| T804 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.641839174 |
|
|
Jun 28 04:34:16 PM PDT 24 |
Jun 28 04:34:22 PM PDT 24 |
92295484 ps |
| T805 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.1719520702 |
|
|
Jun 28 04:34:07 PM PDT 24 |
Jun 28 04:34:14 PM PDT 24 |
29717733 ps |
| T806 |
/workspace/coverage/default/8.sram_ctrl_regwen.1657499899 |
|
|
Jun 28 04:34:03 PM PDT 24 |
Jun 28 04:44:04 PM PDT 24 |
38253054061 ps |
| T807 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.3153799102 |
|
|
Jun 28 04:34:53 PM PDT 24 |
Jun 28 04:35:02 PM PDT 24 |
550585721 ps |
| T808 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3894940768 |
|
|
Jun 28 04:36:18 PM PDT 24 |
Jun 28 04:36:38 PM PDT 24 |
159499082 ps |
| T809 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.3193868326 |
|
|
Jun 28 04:34:27 PM PDT 24 |
Jun 28 04:34:32 PM PDT 24 |
353587309 ps |
| T810 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.3049506050 |
|
|
Jun 28 04:34:49 PM PDT 24 |
Jun 28 04:59:03 PM PDT 24 |
21811895221 ps |
| T811 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.4193911257 |
|
|
Jun 28 04:34:23 PM PDT 24 |
Jun 28 04:34:46 PM PDT 24 |
946545680 ps |
| T812 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.352440271 |
|
|
Jun 28 04:33:31 PM PDT 24 |
Jun 28 04:33:32 PM PDT 24 |
239970182 ps |
| T813 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.423537133 |
|
|
Jun 28 04:35:20 PM PDT 24 |
Jun 28 04:39:32 PM PDT 24 |
38871245246 ps |
| T814 |
/workspace/coverage/default/31.sram_ctrl_regwen.2509220820 |
|
|
Jun 28 04:35:07 PM PDT 24 |
Jun 28 04:50:54 PM PDT 24 |
9332453319 ps |
| T815 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.4019151247 |
|
|
Jun 28 04:34:06 PM PDT 24 |
Jun 28 04:46:01 PM PDT 24 |
12151132296 ps |
| T816 |
/workspace/coverage/default/13.sram_ctrl_stress_all.3520710537 |
|
|
Jun 28 04:34:14 PM PDT 24 |
Jun 28 05:04:27 PM PDT 24 |
129222599792 ps |
| T817 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.3000579048 |
|
|
Jun 28 04:34:32 PM PDT 24 |
Jun 28 04:34:35 PM PDT 24 |
216453513 ps |
| T818 |
/workspace/coverage/default/11.sram_ctrl_bijection.2513995604 |
|
|
Jun 28 04:34:11 PM PDT 24 |
Jun 28 04:34:57 PM PDT 24 |
4086171482 ps |
| T819 |
/workspace/coverage/default/7.sram_ctrl_executable.3174736927 |
|
|
Jun 28 04:33:58 PM PDT 24 |
Jun 28 04:57:14 PM PDT 24 |
16233599151 ps |
| T820 |
/workspace/coverage/default/44.sram_ctrl_alert_test.1578696762 |
|
|
Jun 28 04:36:10 PM PDT 24 |
Jun 28 04:36:11 PM PDT 24 |
17750687 ps |
| T821 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.1885841534 |
|
|
Jun 28 04:35:40 PM PDT 24 |
Jun 28 04:35:42 PM PDT 24 |
27103416 ps |
| T822 |
/workspace/coverage/default/6.sram_ctrl_executable.1805983880 |
|
|
Jun 28 04:33:53 PM PDT 24 |
Jun 28 04:49:02 PM PDT 24 |
19918090963 ps |
| T823 |
/workspace/coverage/default/47.sram_ctrl_stress_all.1235217229 |
|
|
Jun 28 04:36:17 PM PDT 24 |
Jun 28 04:52:51 PM PDT 24 |
48017023338 ps |
| T824 |
/workspace/coverage/default/43.sram_ctrl_executable.3947508105 |
|
|
Jun 28 04:35:52 PM PDT 24 |
Jun 28 05:02:31 PM PDT 24 |
51926287323 ps |
| T825 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1692594525 |
|
|
Jun 28 04:34:11 PM PDT 24 |
Jun 28 04:41:56 PM PDT 24 |
6223568042 ps |
| T826 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3709765315 |
|
|
Jun 28 04:34:08 PM PDT 24 |
Jun 28 04:34:19 PM PDT 24 |
59742414 ps |
| T827 |
/workspace/coverage/default/17.sram_ctrl_smoke.325355545 |
|
|
Jun 28 04:34:29 PM PDT 24 |
Jun 28 04:35:07 PM PDT 24 |
101321136 ps |
| T828 |
/workspace/coverage/default/27.sram_ctrl_smoke.3456750385 |
|
|
Jun 28 04:34:58 PM PDT 24 |
Jun 28 04:35:01 PM PDT 24 |
33557713 ps |
| T829 |
/workspace/coverage/default/8.sram_ctrl_smoke.1518188372 |
|
|
Jun 28 04:33:54 PM PDT 24 |
Jun 28 04:34:06 PM PDT 24 |
134082882 ps |
| T116 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.798912608 |
|
|
Jun 28 04:34:06 PM PDT 24 |
Jun 28 04:35:55 PM PDT 24 |
1439028844 ps |
| T830 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2449865550 |
|
|
Jun 28 04:34:42 PM PDT 24 |
Jun 28 04:40:31 PM PDT 24 |
14331200016 ps |
| T831 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1888018092 |
|
|
Jun 28 04:33:33 PM PDT 24 |
Jun 28 04:36:21 PM PDT 24 |
1499228712 ps |
| T832 |
/workspace/coverage/default/8.sram_ctrl_partial_access.106741377 |
|
|
Jun 28 04:34:10 PM PDT 24 |
Jun 28 04:34:28 PM PDT 24 |
751972233 ps |
| T833 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2807474015 |
|
|
Jun 28 04:35:38 PM PDT 24 |
Jun 28 04:36:06 PM PDT 24 |
3354622010 ps |
| T834 |
/workspace/coverage/default/41.sram_ctrl_smoke.918774084 |
|
|
Jun 28 04:35:49 PM PDT 24 |
Jun 28 04:35:55 PM PDT 24 |
400505427 ps |
| T835 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.2431691238 |
|
|
Jun 28 04:33:43 PM PDT 24 |
Jun 28 04:33:47 PM PDT 24 |
406510977 ps |
| T836 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.3726633739 |
|
|
Jun 28 04:33:51 PM PDT 24 |
Jun 28 04:35:40 PM PDT 24 |
123292632 ps |
| T837 |
/workspace/coverage/default/5.sram_ctrl_smoke.4080324671 |
|
|
Jun 28 04:33:39 PM PDT 24 |
Jun 28 04:33:42 PM PDT 24 |
72145221 ps |
| T838 |
/workspace/coverage/default/28.sram_ctrl_alert_test.1752281499 |
|
|
Jun 28 04:35:06 PM PDT 24 |
Jun 28 04:35:07 PM PDT 24 |
37097470 ps |
| T839 |
/workspace/coverage/default/8.sram_ctrl_alert_test.1304274232 |
|
|
Jun 28 04:34:06 PM PDT 24 |
Jun 28 04:34:14 PM PDT 24 |
13438007 ps |
| T840 |
/workspace/coverage/default/43.sram_ctrl_alert_test.2105039226 |
|
|
Jun 28 04:36:06 PM PDT 24 |
Jun 28 04:36:08 PM PDT 24 |
47537026 ps |
| T841 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.3067055926 |
|
|
Jun 28 04:36:30 PM PDT 24 |
Jun 28 04:39:08 PM PDT 24 |
6901023086 ps |
| T842 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2795214908 |
|
|
Jun 28 04:33:28 PM PDT 24 |
Jun 28 04:38:50 PM PDT 24 |
30796013024 ps |
| T843 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2104485045 |
|
|
Jun 28 04:33:35 PM PDT 24 |
Jun 28 04:37:21 PM PDT 24 |
2231733800 ps |
| T844 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.1006114635 |
|
|
Jun 28 04:35:22 PM PDT 24 |
Jun 28 04:35:25 PM PDT 24 |
101264364 ps |
| T845 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.1768643498 |
|
|
Jun 28 04:34:46 PM PDT 24 |
Jun 28 04:34:47 PM PDT 24 |
89203972 ps |
| T846 |
/workspace/coverage/default/37.sram_ctrl_stress_all.931658273 |
|
|
Jun 28 04:35:30 PM PDT 24 |
Jun 28 05:43:27 PM PDT 24 |
14025568360 ps |
| T847 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.698067797 |
|
|
Jun 28 04:36:17 PM PDT 24 |
Jun 28 04:36:22 PM PDT 24 |
68103518 ps |
| T848 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.457862480 |
|
|
Jun 28 04:34:38 PM PDT 24 |
Jun 28 04:34:51 PM PDT 24 |
3632888341 ps |
| T849 |
/workspace/coverage/default/11.sram_ctrl_executable.2051361373 |
|
|
Jun 28 04:34:16 PM PDT 24 |
Jun 28 04:48:39 PM PDT 24 |
45287433065 ps |
| T850 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.1384646512 |
|
|
Jun 28 04:36:17 PM PDT 24 |
Jun 28 04:36:24 PM PDT 24 |
1319596209 ps |
| T851 |
/workspace/coverage/default/1.sram_ctrl_executable.3331073979 |
|
|
Jun 28 04:33:41 PM PDT 24 |
Jun 28 04:41:06 PM PDT 24 |
4737575623 ps |
| T852 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.369652915 |
|
|
Jun 28 04:35:20 PM PDT 24 |
Jun 28 04:36:04 PM PDT 24 |
216962819 ps |
| T853 |
/workspace/coverage/default/23.sram_ctrl_bijection.2266731981 |
|
|
Jun 28 04:34:50 PM PDT 24 |
Jun 28 04:35:38 PM PDT 24 |
1511034416 ps |
| T854 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2182593743 |
|
|
Jun 28 04:33:52 PM PDT 24 |
Jun 28 04:36:30 PM PDT 24 |
6463342045 ps |
| T855 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.85867554 |
|
|
Jun 28 04:33:59 PM PDT 24 |
Jun 28 04:46:25 PM PDT 24 |
1902089351 ps |
| T856 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.3877691303 |
|
|
Jun 28 04:35:29 PM PDT 24 |
Jun 28 04:39:51 PM PDT 24 |
751479759 ps |
| T857 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.326455133 |
|
|
Jun 28 04:36:18 PM PDT 24 |
Jun 28 04:36:22 PM PDT 24 |
368720232 ps |
| T858 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.1904544331 |
|
|
Jun 28 04:34:04 PM PDT 24 |
Jun 28 04:51:21 PM PDT 24 |
4691276636 ps |
| T859 |
/workspace/coverage/default/11.sram_ctrl_stress_all.3703787149 |
|
|
Jun 28 04:34:16 PM PDT 24 |
Jun 28 04:50:16 PM PDT 24 |
4765795968 ps |
| T860 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.1563418165 |
|
|
Jun 28 04:34:08 PM PDT 24 |
Jun 28 04:59:14 PM PDT 24 |
8394660527 ps |
| T861 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.563958511 |
|
|
Jun 28 04:36:07 PM PDT 24 |
Jun 28 04:41:25 PM PDT 24 |
15229904353 ps |
| T862 |
/workspace/coverage/default/13.sram_ctrl_bijection.1094858644 |
|
|
Jun 28 04:34:13 PM PDT 24 |
Jun 28 04:35:13 PM PDT 24 |
857525505 ps |
| T863 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.2556923978 |
|
|
Jun 28 04:34:47 PM PDT 24 |
Jun 28 04:34:57 PM PDT 24 |
182835444 ps |
| T864 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.3747916928 |
|
|
Jun 28 04:35:07 PM PDT 24 |
Jun 28 04:49:31 PM PDT 24 |
12670453508 ps |
| T865 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2132823469 |
|
|
Jun 28 04:35:51 PM PDT 24 |
Jun 28 04:41:57 PM PDT 24 |
89255427788 ps |
| T866 |
/workspace/coverage/default/28.sram_ctrl_partial_access.253280083 |
|
|
Jun 28 04:34:58 PM PDT 24 |
Jun 28 04:35:28 PM PDT 24 |
269096169 ps |
| T867 |
/workspace/coverage/default/13.sram_ctrl_alert_test.3669404499 |
|
|
Jun 28 04:34:12 PM PDT 24 |
Jun 28 04:34:19 PM PDT 24 |
39751516 ps |
| T868 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.3684622804 |
|
|
Jun 28 04:35:13 PM PDT 24 |
Jun 28 04:35:21 PM PDT 24 |
688911040 ps |
| T869 |
/workspace/coverage/default/34.sram_ctrl_bijection.2319636748 |
|
|
Jun 28 04:35:21 PM PDT 24 |
Jun 28 04:36:23 PM PDT 24 |
2518292315 ps |
| T870 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.469467022 |
|
|
Jun 28 04:34:07 PM PDT 24 |
Jun 28 04:35:10 PM PDT 24 |
192932543 ps |
| T871 |
/workspace/coverage/default/21.sram_ctrl_smoke.247955284 |
|
|
Jun 28 04:34:39 PM PDT 24 |
Jun 28 04:35:45 PM PDT 24 |
123368749 ps |
| T872 |
/workspace/coverage/default/40.sram_ctrl_partial_access.55076623 |
|
|
Jun 28 04:35:39 PM PDT 24 |
Jun 28 04:35:58 PM PDT 24 |
1324859283 ps |
| T873 |
/workspace/coverage/default/13.sram_ctrl_smoke.2130742565 |
|
|
Jun 28 04:34:17 PM PDT 24 |
Jun 28 04:35:00 PM PDT 24 |
1601554522 ps |
| T874 |
/workspace/coverage/default/38.sram_ctrl_stress_all.413735042 |
|
|
Jun 28 04:35:29 PM PDT 24 |
Jun 28 05:00:09 PM PDT 24 |
7278609435 ps |
| T875 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.1189968926 |
|
|
Jun 28 04:35:29 PM PDT 24 |
Jun 28 04:35:31 PM PDT 24 |
37151221 ps |
| T876 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2667941933 |
|
|
Jun 28 04:36:29 PM PDT 24 |
Jun 28 04:36:38 PM PDT 24 |
721951244 ps |
| T877 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.2961211661 |
|
|
Jun 28 04:33:38 PM PDT 24 |
Jun 28 04:34:28 PM PDT 24 |
152378125 ps |
| T878 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2009474019 |
|
|
Jun 28 04:35:53 PM PDT 24 |
Jun 28 04:43:16 PM PDT 24 |
14648974324 ps |
| T879 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.1044209533 |
|
|
Jun 28 04:34:16 PM PDT 24 |
Jun 28 04:34:27 PM PDT 24 |
177005990 ps |
| T880 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.130726812 |
|
|
Jun 28 04:34:48 PM PDT 24 |
Jun 28 04:34:57 PM PDT 24 |
2317390989 ps |
| T881 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1788642108 |
|
|
Jun 28 04:35:50 PM PDT 24 |
Jun 28 04:36:27 PM PDT 24 |
1062431710 ps |
| T882 |
/workspace/coverage/default/41.sram_ctrl_executable.4048623869 |
|
|
Jun 28 04:35:50 PM PDT 24 |
Jun 28 04:53:03 PM PDT 24 |
18059958239 ps |
| T883 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.1409523355 |
|
|
Jun 28 04:34:36 PM PDT 24 |
Jun 28 04:34:46 PM PDT 24 |
142482997 ps |
| T884 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.2909385867 |
|
|
Jun 28 04:35:08 PM PDT 24 |
Jun 28 04:35:10 PM PDT 24 |
46518912 ps |
| T885 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.2773207550 |
|
|
Jun 28 04:35:09 PM PDT 24 |
Jun 28 04:35:22 PM PDT 24 |
2051825240 ps |
| T886 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3980040261 |
|
|
Jun 28 04:34:24 PM PDT 24 |
Jun 28 04:34:58 PM PDT 24 |
1130246089 ps |
| T887 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3461965962 |
|
|
Jun 28 04:33:44 PM PDT 24 |
Jun 28 04:35:29 PM PDT 24 |
606111345 ps |
| T888 |
/workspace/coverage/default/20.sram_ctrl_stress_all.1909396648 |
|
|
Jun 28 04:34:37 PM PDT 24 |
Jun 28 06:09:23 PM PDT 24 |
62527398491 ps |
| T889 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3108958049 |
|
|
Jun 28 04:34:53 PM PDT 24 |
Jun 28 04:42:20 PM PDT 24 |
66755739533 ps |
| T890 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.3724885882 |
|
|
Jun 28 04:35:12 PM PDT 24 |
Jun 28 04:35:14 PM PDT 24 |
84628236 ps |
| T891 |
/workspace/coverage/default/17.sram_ctrl_bijection.2398102282 |
|
|
Jun 28 04:34:23 PM PDT 24 |
Jun 28 04:35:03 PM PDT 24 |
3124212576 ps |
| T892 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.3915857695 |
|
|
Jun 28 04:34:14 PM PDT 24 |
Jun 28 04:34:21 PM PDT 24 |
33865421 ps |
| T893 |
/workspace/coverage/default/25.sram_ctrl_regwen.210595871 |
|
|
Jun 28 04:34:48 PM PDT 24 |
Jun 28 04:57:54 PM PDT 24 |
80336144232 ps |
| T894 |
/workspace/coverage/default/11.sram_ctrl_regwen.2877411191 |
|
|
Jun 28 04:34:05 PM PDT 24 |
Jun 28 04:48:22 PM PDT 24 |
13729874465 ps |
| T895 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.1490984269 |
|
|
Jun 28 04:35:23 PM PDT 24 |
Jun 28 04:35:25 PM PDT 24 |
49582251 ps |
| T896 |
/workspace/coverage/default/27.sram_ctrl_partial_access.3141714282 |
|
|
Jun 28 04:34:52 PM PDT 24 |
Jun 28 04:35:35 PM PDT 24 |
928301084 ps |
| T897 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.1120420773 |
|
|
Jun 28 04:34:50 PM PDT 24 |
Jun 28 04:34:54 PM PDT 24 |
196403196 ps |
| T898 |
/workspace/coverage/default/18.sram_ctrl_stress_all.3729437938 |
|
|
Jun 28 04:34:25 PM PDT 24 |
Jun 28 05:46:06 PM PDT 24 |
250904403752 ps |
| T899 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.1610935049 |
|
|
Jun 28 04:35:27 PM PDT 24 |
Jun 28 04:37:48 PM PDT 24 |
5217534684 ps |
| T900 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1606171719 |
|
|
Jun 28 04:35:40 PM PDT 24 |
Jun 28 04:42:19 PM PDT 24 |
1527383973 ps |
| T901 |
/workspace/coverage/default/25.sram_ctrl_alert_test.3663238550 |
|
|
Jun 28 04:34:49 PM PDT 24 |
Jun 28 04:34:51 PM PDT 24 |
13777194 ps |
| T902 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.441647438 |
|
|
Jun 28 04:33:38 PM PDT 24 |
Jun 28 04:41:29 PM PDT 24 |
36799864374 ps |
| T903 |
/workspace/coverage/default/32.sram_ctrl_regwen.542632735 |
|
|
Jun 28 04:35:13 PM PDT 24 |
Jun 28 04:37:52 PM PDT 24 |
6104103696 ps |
| T904 |
/workspace/coverage/default/45.sram_ctrl_smoke.1149942705 |
|
|
Jun 28 04:36:06 PM PDT 24 |
Jun 28 04:38:35 PM PDT 24 |
660856082 ps |
| T905 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.2259736745 |
|
|
Jun 28 04:33:27 PM PDT 24 |
Jun 28 04:34:17 PM PDT 24 |
110421005 ps |
| T906 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.165740835 |
|
|
Jun 28 04:35:50 PM PDT 24 |
Jun 28 04:37:00 PM PDT 24 |
571346182 ps |
| T907 |
/workspace/coverage/default/24.sram_ctrl_smoke.2164542754 |
|
|
Jun 28 04:35:03 PM PDT 24 |
Jun 28 04:35:31 PM PDT 24 |
1277813011 ps |
| T908 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.1800494529 |
|
|
Jun 28 04:35:40 PM PDT 24 |
Jun 28 04:35:46 PM PDT 24 |
446083876 ps |
| T909 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1856149610 |
|
|
Jun 28 04:34:05 PM PDT 24 |
Jun 28 04:36:06 PM PDT 24 |
534622304 ps |
| T910 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.3126284700 |
|
|
Jun 28 04:34:26 PM PDT 24 |
Jun 28 04:34:31 PM PDT 24 |
388933450 ps |
| T911 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2769547019 |
|
|
Jun 28 04:36:16 PM PDT 24 |
Jun 28 04:36:21 PM PDT 24 |
4115259567 ps |
| T912 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3131519705 |
|
|
Jun 28 04:35:05 PM PDT 24 |
Jun 28 04:35:45 PM PDT 24 |
420583991 ps |
| T913 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3573519244 |
|
|
Jun 28 04:36:08 PM PDT 24 |
Jun 28 04:47:51 PM PDT 24 |
15289927778 ps |
| T914 |
/workspace/coverage/default/45.sram_ctrl_executable.1916112606 |
|
|
Jun 28 04:36:05 PM PDT 24 |
Jun 28 04:47:42 PM PDT 24 |
18363167738 ps |
| T915 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.335453235 |
|
|
Jun 28 04:34:51 PM PDT 24 |
Jun 28 04:39:16 PM PDT 24 |
2824614494 ps |
| T916 |
/workspace/coverage/default/40.sram_ctrl_regwen.1014536582 |
|
|
Jun 28 04:35:38 PM PDT 24 |
Jun 28 04:51:43 PM PDT 24 |
9483580246 ps |
| T917 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.1734736379 |
|
|
Jun 28 04:35:11 PM PDT 24 |
Jun 28 04:40:51 PM PDT 24 |
13692376442 ps |
| T918 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.3424968741 |
|
|
Jun 28 04:35:10 PM PDT 24 |
Jun 28 04:35:16 PM PDT 24 |
123000600 ps |
| T919 |
/workspace/coverage/default/30.sram_ctrl_partial_access.2934868988 |
|
|
Jun 28 04:35:09 PM PDT 24 |
Jun 28 04:35:30 PM PDT 24 |
1089407247 ps |
| T920 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.3313227457 |
|
|
Jun 28 04:33:54 PM PDT 24 |
Jun 28 04:34:05 PM PDT 24 |
3269568134 ps |
| T921 |
/workspace/coverage/default/21.sram_ctrl_partial_access.1897968449 |
|
|
Jun 28 04:34:35 PM PDT 24 |
Jun 28 04:34:44 PM PDT 24 |
858214043 ps |
| T922 |
/workspace/coverage/default/1.sram_ctrl_smoke.341278144 |
|
|
Jun 28 04:33:30 PM PDT 24 |
Jun 28 04:33:40 PM PDT 24 |
385852647 ps |
| T923 |
/workspace/coverage/default/25.sram_ctrl_stress_all.1916398676 |
|
|
Jun 28 04:34:48 PM PDT 24 |
Jun 28 04:51:29 PM PDT 24 |
12543612685 ps |
| T924 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2756600471 |
|
|
Jun 28 04:36:08 PM PDT 24 |
Jun 28 04:40:10 PM PDT 24 |
2555316103 ps |
| T925 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3005403105 |
|
|
Jun 28 04:36:30 PM PDT 24 |
Jun 28 04:43:02 PM PDT 24 |
6367354532 ps |
| T926 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.4091259085 |
|
|
Jun 28 04:34:58 PM PDT 24 |
Jun 28 04:42:14 PM PDT 24 |
9084934958 ps |
| T927 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.319893784 |
|
|
Jun 28 04:35:12 PM PDT 24 |
Jun 28 04:35:17 PM PDT 24 |
51563548 ps |
| T928 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.610977107 |
|
|
Jun 28 04:34:26 PM PDT 24 |
Jun 28 04:38:53 PM PDT 24 |
23477803281 ps |
| T929 |
/workspace/coverage/default/39.sram_ctrl_smoke.3950561241 |
|
|
Jun 28 04:35:32 PM PDT 24 |
Jun 28 04:36:14 PM PDT 24 |
395799896 ps |
| T930 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.2001693143 |
|
|
Jun 28 04:35:32 PM PDT 24 |
Jun 28 04:38:45 PM PDT 24 |
2086066776 ps |
| T931 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.2945106889 |
|
|
Jun 28 04:33:34 PM PDT 24 |
Jun 28 04:33:36 PM PDT 24 |
30193426 ps |
| T932 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.3007630008 |
|
|
Jun 28 04:34:39 PM PDT 24 |
Jun 28 04:34:46 PM PDT 24 |
711004799 ps |
| T933 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.1569604954 |
|
|
Jun 28 04:34:57 PM PDT 24 |
Jun 28 04:35:02 PM PDT 24 |
170429298 ps |
| T934 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.3113777196 |
|
|
Jun 28 04:35:53 PM PDT 24 |
Jun 28 04:42:50 PM PDT 24 |
11568694275 ps |
| T935 |
/workspace/coverage/default/11.sram_ctrl_partial_access.1354490033 |
|
|
Jun 28 04:34:11 PM PDT 24 |
Jun 28 04:34:34 PM PDT 24 |
2228111396 ps |
| T936 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3722747897 |
|
|
Jun 28 04:34:04 PM PDT 24 |
Jun 28 04:42:47 PM PDT 24 |
1746578594 ps |
| T937 |
/workspace/coverage/default/42.sram_ctrl_stress_all.2178994431 |
|
|
Jun 28 04:35:51 PM PDT 24 |
Jun 28 04:48:31 PM PDT 24 |
3061521982 ps |
| T938 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.4063583682 |
|
|
Jun 28 04:35:41 PM PDT 24 |
Jun 28 04:39:40 PM PDT 24 |
3278145316 ps |
| T939 |
/workspace/coverage/default/0.sram_ctrl_stress_all.4153440193 |
|
|
Jun 28 04:33:37 PM PDT 24 |
Jun 28 05:04:21 PM PDT 24 |
168424941149 ps |
| T940 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1851405762 |
|
|
Jun 28 04:31:43 PM PDT 24 |
Jun 28 04:31:46 PM PDT 24 |
230187463 ps |
| T56 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3246849959 |
|
|
Jun 28 04:31:43 PM PDT 24 |
Jun 28 04:31:46 PM PDT 24 |
604260967 ps |
| T59 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3485592820 |
|
|
Jun 28 04:31:48 PM PDT 24 |
Jun 28 04:31:50 PM PDT 24 |
44904830 ps |
| T60 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3649870189 |
|
|
Jun 28 04:31:39 PM PDT 24 |
Jun 28 04:31:41 PM PDT 24 |
14650902 ps |
| T96 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3854701596 |
|
|
Jun 28 04:31:53 PM PDT 24 |
Jun 28 04:31:57 PM PDT 24 |
2731988807 ps |
| T65 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3424902495 |
|
|
Jun 28 04:31:38 PM PDT 24 |
Jun 28 04:31:40 PM PDT 24 |
17894902 ps |
| T66 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2925770072 |
|
|
Jun 28 04:31:37 PM PDT 24 |
Jun 28 04:31:40 PM PDT 24 |
163414844 ps |
| T941 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1008830585 |
|
|
Jun 28 04:31:37 PM PDT 24 |
Jun 28 04:31:44 PM PDT 24 |
153669990 ps |
| T57 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.397422359 |
|
|
Jun 28 04:31:45 PM PDT 24 |
Jun 28 04:31:49 PM PDT 24 |
766787469 ps |
| T67 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1198287009 |
|
|
Jun 28 04:31:40 PM PDT 24 |
Jun 28 04:31:43 PM PDT 24 |
447644844 ps |
| T97 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3873488739 |
|
|
Jun 28 04:31:34 PM PDT 24 |
Jun 28 04:31:36 PM PDT 24 |
17423498 ps |
| T98 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2288491190 |
|
|
Jun 28 04:31:53 PM PDT 24 |
Jun 28 04:31:56 PM PDT 24 |
236029015 ps |
| T108 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3461666069 |
|
|
Jun 28 04:32:15 PM PDT 24 |
Jun 28 04:32:17 PM PDT 24 |
71191005 ps |
| T68 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3300898651 |
|
|
Jun 28 04:31:31 PM PDT 24 |
Jun 28 04:31:36 PM PDT 24 |
549738206 ps |
| T942 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.282772442 |
|
|
Jun 28 04:31:35 PM PDT 24 |
Jun 28 04:31:38 PM PDT 24 |
60691179 ps |
| T58 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.135084817 |
|
|
Jun 28 04:31:53 PM PDT 24 |
Jun 28 04:31:56 PM PDT 24 |
661232582 ps |
| T109 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1743284638 |
|
|
Jun 28 04:31:38 PM PDT 24 |
Jun 28 04:31:40 PM PDT 24 |
12732793 ps |
| T121 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1884424003 |
|
|
Jun 28 04:31:52 PM PDT 24 |
Jun 28 04:31:54 PM PDT 24 |
125649683 ps |
| T69 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1562161927 |
|
|
Jun 28 04:31:56 PM PDT 24 |
Jun 28 04:31:58 PM PDT 24 |
35860491 ps |
| T943 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1970479921 |
|
|
Jun 28 04:31:45 PM PDT 24 |
Jun 28 04:31:49 PM PDT 24 |
80322212 ps |
| T944 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1426871035 |
|
|
Jun 28 04:31:42 PM PDT 24 |
Jun 28 04:31:46 PM PDT 24 |
25320411 ps |
| T70 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1884210374 |
|
|
Jun 28 04:31:34 PM PDT 24 |
Jun 28 04:31:37 PM PDT 24 |
32466860 ps |
| T99 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3749901287 |
|
|
Jun 28 04:31:34 PM PDT 24 |
Jun 28 04:31:35 PM PDT 24 |
17828910 ps |
| T100 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3812292252 |
|
|
Jun 28 04:31:42 PM PDT 24 |
Jun 28 04:31:50 PM PDT 24 |
494685388 ps |
| T945 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1371070711 |
|
|
Jun 28 04:32:02 PM PDT 24 |
Jun 28 04:32:04 PM PDT 24 |
36376512 ps |
| T946 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1181522442 |
|
|
Jun 28 04:31:58 PM PDT 24 |
Jun 28 04:31:59 PM PDT 24 |
21522795 ps |
| T101 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3421863569 |
|
|
Jun 28 04:31:44 PM PDT 24 |
Jun 28 04:31:46 PM PDT 24 |
95097914 ps |
| T947 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1077299068 |
|
|
Jun 28 04:31:50 PM PDT 24 |
Jun 28 04:31:51 PM PDT 24 |
77845324 ps |
| T123 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1410171506 |
|
|
Jun 28 04:31:46 PM PDT 24 |
Jun 28 04:31:49 PM PDT 24 |
142695419 ps |
| T948 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1576673741 |
|
|
Jun 28 04:32:12 PM PDT 24 |
Jun 28 04:32:14 PM PDT 24 |
31209027 ps |
| T949 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1124706154 |
|
|
Jun 28 04:31:43 PM PDT 24 |
Jun 28 04:31:50 PM PDT 24 |
161962671 ps |
| T71 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3683983505 |
|
|
Jun 28 04:31:51 PM PDT 24 |
Jun 28 04:31:52 PM PDT 24 |
14503236 ps |
| T128 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.443681925 |
|
|
Jun 28 04:31:38 PM PDT 24 |
Jun 28 04:31:42 PM PDT 24 |
1193146962 ps |
| T950 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3192680831 |
|
|
Jun 28 04:31:41 PM PDT 24 |
Jun 28 04:31:43 PM PDT 24 |
23706066 ps |
| T951 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1205616684 |
|
|
Jun 28 04:31:24 PM PDT 24 |
Jun 28 04:31:28 PM PDT 24 |
34268883 ps |
| T72 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.310877392 |
|
|
Jun 28 04:31:51 PM PDT 24 |
Jun 28 04:31:52 PM PDT 24 |
68462521 ps |
| T952 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.513417720 |
|
|
Jun 28 04:31:47 PM PDT 24 |
Jun 28 04:31:50 PM PDT 24 |
28587383 ps |
| T953 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2412602225 |
|
|
Jun 28 04:32:33 PM PDT 24 |
Jun 28 04:32:34 PM PDT 24 |
20112771 ps |
| T954 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1578656121 |
|
|
Jun 28 04:31:38 PM PDT 24 |
Jun 28 04:31:40 PM PDT 24 |
54233911 ps |
| T955 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2420057361 |
|
|
Jun 28 04:31:35 PM PDT 24 |
Jun 28 04:31:37 PM PDT 24 |
39694269 ps |
| T956 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2894854151 |
|
|
Jun 28 04:31:45 PM PDT 24 |
Jun 28 04:31:48 PM PDT 24 |
381489672 ps |
| T957 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1103644666 |
|
|
Jun 28 04:31:48 PM PDT 24 |
Jun 28 04:31:50 PM PDT 24 |
236302491 ps |
| T958 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.427513984 |
|
|
Jun 28 04:31:44 PM PDT 24 |
Jun 28 04:31:46 PM PDT 24 |
32665279 ps |
| T73 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.219062871 |
|
|
Jun 28 04:31:50 PM PDT 24 |
Jun 28 04:31:54 PM PDT 24 |
1048938581 ps |
| T959 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.4173484887 |
|
|
Jun 28 04:31:46 PM PDT 24 |
Jun 28 04:31:48 PM PDT 24 |
24273045 ps |
| T960 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.604352084 |
|
|
Jun 28 04:31:42 PM PDT 24 |
Jun 28 04:31:45 PM PDT 24 |
60146628 ps |
| T961 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2352116897 |
|
|
Jun 28 04:31:50 PM PDT 24 |
Jun 28 04:31:52 PM PDT 24 |
191217928 ps |
| T962 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1850468077 |
|
|
Jun 28 04:31:50 PM PDT 24 |
Jun 28 04:31:52 PM PDT 24 |
38857988 ps |
| T963 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.537048164 |
|
|
Jun 28 04:31:53 PM PDT 24 |
Jun 28 04:31:54 PM PDT 24 |
22070220 ps |
| T964 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1977850160 |
|
|
Jun 28 04:31:42 PM PDT 24 |
Jun 28 04:31:48 PM PDT 24 |
133977085 ps |
| T78 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3120789139 |
|
|
Jun 28 04:31:42 PM PDT 24 |
Jun 28 04:31:45 PM PDT 24 |
68719271 ps |
| T965 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2291276462 |
|
|
Jun 28 04:31:41 PM PDT 24 |
Jun 28 04:31:46 PM PDT 24 |
395712944 ps |
| T126 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3561390088 |
|
|
Jun 28 04:31:42 PM PDT 24 |
Jun 28 04:31:46 PM PDT 24 |
204226087 ps |
| T79 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1011838870 |
|
|
Jun 28 04:31:44 PM PDT 24 |
Jun 28 04:31:48 PM PDT 24 |
806708972 ps |
| T80 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3104422516 |
|
|
Jun 28 04:31:48 PM PDT 24 |
Jun 28 04:31:51 PM PDT 24 |
390001592 ps |
| T966 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1718799807 |
|
|
Jun 28 04:31:37 PM PDT 24 |
Jun 28 04:31:42 PM PDT 24 |
422858012 ps |
| T81 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2148309694 |
|
|
Jun 28 04:31:39 PM PDT 24 |
Jun 28 04:31:43 PM PDT 24 |
485565859 ps |
| T967 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1769337131 |
|
|
Jun 28 04:32:28 PM PDT 24 |
Jun 28 04:32:29 PM PDT 24 |
27802395 ps |
| T82 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1750351802 |
|
|
Jun 28 04:31:44 PM PDT 24 |
Jun 28 04:31:47 PM PDT 24 |
12251183 ps |
| T968 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3130036691 |
|
|
Jun 28 04:31:58 PM PDT 24 |
Jun 28 04:32:00 PM PDT 24 |
303076535 ps |
| T83 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1667787685 |
|
|
Jun 28 04:31:53 PM PDT 24 |
Jun 28 04:31:57 PM PDT 24 |
677928150 ps |
| T84 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1826608504 |
|
|
Jun 28 04:31:42 PM PDT 24 |
Jun 28 04:31:47 PM PDT 24 |
817154296 ps |
| T969 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.591136503 |
|
|
Jun 28 04:31:44 PM PDT 24 |
Jun 28 04:31:51 PM PDT 24 |
312013589 ps |
| T125 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1465953779 |
|
|
Jun 28 04:32:18 PM PDT 24 |
Jun 28 04:32:20 PM PDT 24 |
259384193 ps |
| T92 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4246440475 |
|
|
Jun 28 04:31:47 PM PDT 24 |
Jun 28 04:31:49 PM PDT 24 |
44001878 ps |
| T970 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3968725261 |
|
|
Jun 28 04:31:51 PM PDT 24 |
Jun 28 04:31:53 PM PDT 24 |
50130755 ps |
| T971 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.176811408 |
|
|
Jun 28 04:31:50 PM PDT 24 |
Jun 28 04:31:52 PM PDT 24 |
433232850 ps |
| T972 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.765986030 |
|
|
Jun 28 04:31:40 PM PDT 24 |
Jun 28 04:31:45 PM PDT 24 |
1564806240 ps |
| T973 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2399942690 |
|
|
Jun 28 04:31:42 PM PDT 24 |
Jun 28 04:31:46 PM PDT 24 |
61673158 ps |
| T94 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3521384855 |
|
|
Jun 28 04:31:55 PM PDT 24 |
Jun 28 04:31:57 PM PDT 24 |
40203344 ps |
| T95 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2156141731 |
|
|
Jun 28 04:31:40 PM PDT 24 |
Jun 28 04:31:43 PM PDT 24 |
47415745 ps |
| T974 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3590109792 |
|
|
Jun 28 04:32:09 PM PDT 24 |
Jun 28 04:32:10 PM PDT 24 |
58577450 ps |
| T124 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3424099965 |
|
|
Jun 28 04:31:43 PM PDT 24 |
Jun 28 04:31:47 PM PDT 24 |
178001319 ps |
| T975 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.412631881 |
|
|
Jun 28 04:32:01 PM PDT 24 |
Jun 28 04:32:03 PM PDT 24 |
259097526 ps |
| T976 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2758046781 |
|
|
Jun 28 04:31:46 PM PDT 24 |
Jun 28 04:31:49 PM PDT 24 |
428450254 ps |
| T977 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2655620616 |
|
|
Jun 28 04:31:30 PM PDT 24 |
Jun 28 04:31:35 PM PDT 24 |
76750794 ps |
| T978 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4190328181 |
|
|
Jun 28 04:31:54 PM PDT 24 |
Jun 28 04:31:56 PM PDT 24 |
14528509 ps |
| T979 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3837830077 |
|
|
Jun 28 04:31:48 PM PDT 24 |
Jun 28 04:31:51 PM PDT 24 |
148463551 ps |
| T980 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2269758265 |
|
|
Jun 28 04:31:51 PM PDT 24 |
Jun 28 04:31:52 PM PDT 24 |
31307942 ps |
| T981 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.394516871 |
|
|
Jun 28 04:31:41 PM PDT 24 |
Jun 28 04:31:44 PM PDT 24 |
37444564 ps |
| T982 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2270270852 |
|
|
Jun 28 04:31:38 PM PDT 24 |
Jun 28 04:31:44 PM PDT 24 |
141561593 ps |
| T122 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3951049647 |
|
|
Jun 28 04:31:44 PM PDT 24 |
Jun 28 04:31:47 PM PDT 24 |
109627975 ps |
| T983 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3792349584 |
|
|
Jun 28 04:31:44 PM PDT 24 |
Jun 28 04:31:49 PM PDT 24 |
63176558 ps |
| T984 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.692716373 |
|
|
Jun 28 04:31:43 PM PDT 24 |
Jun 28 04:31:49 PM PDT 24 |
83967900 ps |
| T985 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.726983166 |
|
|
Jun 28 04:31:32 PM PDT 24 |
Jun 28 04:31:34 PM PDT 24 |
105232683 ps |
| T986 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4206388143 |
|
|
Jun 28 04:31:43 PM PDT 24 |
Jun 28 04:31:49 PM PDT 24 |
25210612 ps |
| T987 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3303427169 |
|
|
Jun 28 04:31:33 PM PDT 24 |
Jun 28 04:31:36 PM PDT 24 |
178551970 ps |
| T988 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1447171288 |
|
|
Jun 28 04:31:43 PM PDT 24 |
Jun 28 04:31:49 PM PDT 24 |
88221107 ps |
| T989 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2419912141 |
|
|
Jun 28 04:31:40 PM PDT 24 |
Jun 28 04:31:43 PM PDT 24 |
33633172 ps |
| T990 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2940814765 |
|
|
Jun 28 04:31:35 PM PDT 24 |
Jun 28 04:31:39 PM PDT 24 |
172717594 ps |
| T991 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.605700276 |
|
|
Jun 28 04:31:37 PM PDT 24 |
Jun 28 04:31:40 PM PDT 24 |
67606399 ps |
| T992 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2399725769 |
|
|
Jun 28 04:31:32 PM PDT 24 |
Jun 28 04:31:35 PM PDT 24 |
90418445 ps |
| T993 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4203171730 |
|
|
Jun 28 04:31:42 PM PDT 24 |
Jun 28 04:31:46 PM PDT 24 |
60881714 ps |
| T994 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.126301651 |
|
|
Jun 28 04:31:37 PM PDT 24 |
Jun 28 04:31:40 PM PDT 24 |
680281345 ps |
| T995 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1377043598 |
|
|
Jun 28 04:31:40 PM PDT 24 |
Jun 28 04:31:42 PM PDT 24 |
62332352 ps |
| T996 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3733499964 |
|
|
Jun 28 04:31:55 PM PDT 24 |
Jun 28 04:31:57 PM PDT 24 |
84372502 ps |
| T997 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.920060349 |
|
|
Jun 28 04:31:43 PM PDT 24 |
Jun 28 04:31:46 PM PDT 24 |
209264813 ps |
| T127 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1206964341 |
|
|
Jun 28 04:32:22 PM PDT 24 |
Jun 28 04:32:25 PM PDT 24 |
546515069 ps |
| T998 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1828199842 |
|
|
Jun 28 04:31:59 PM PDT 24 |
Jun 28 04:32:03 PM PDT 24 |
1390375451 ps |
| T999 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.289626416 |
|
|
Jun 28 04:31:32 PM PDT 24 |
Jun 28 04:31:36 PM PDT 24 |
43677438 ps |
| T1000 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.771893786 |
|
|
Jun 28 04:31:45 PM PDT 24 |
Jun 28 04:31:49 PM PDT 24 |
117814659 ps |
| T1001 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1359446351 |
|
|
Jun 28 04:31:36 PM PDT 24 |
Jun 28 04:31:38 PM PDT 24 |
21500671 ps |