SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
80.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_errors_cgs_wrap[sram_ctrl_prim_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_errors_cgs_wrap[sram_ctrl_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 15 | 5 | 10 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_csr_size_err | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_instr_type_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_mem_byte_access_err | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_mem_ro_err | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_mem_wo_err | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_tl_protocol_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
cp_unmapped_err | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_write_w_instr_type_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 15 | 3 | 12 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_csr_size_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_instr_type_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_mem_byte_access_err | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_mem_ro_err | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_mem_wo_err | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_tl_protocol_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
cp_unmapped_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_write_w_instr_type_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 11430115 | 0 | T6 | 218976 | T18 | 36477 | T19 | 84386 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 5834606 | 1 | T6 | 109356 | T18 | 22271 | T19 | 42301 | ||||
auto[1] | 5595509 | 1 | T6 | 109620 | T18 | 14206 | T19 | 42085 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 11430115 | 0 | T6 | 218976 | T18 | 36477 | T19 | 84386 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 11430115 | 0 | T6 | 218976 | T18 | 36477 | T19 | 84386 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 11430115 | 0 | T6 | 218976 | T18 | 36477 | T19 | 84386 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
covered | 238603 | 1 | T18 | 8393 | T22 | 2229 | T23 | 6963 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 11430115 | 0 | T6 | 218976 | T18 | 36477 | T19 | 84386 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 5834338 | 1 | T6 | 109620 | T18 | 22599 | T19 | 42085 | ||||
auto[1] | 5595777 | 1 | T6 | 109356 | T18 | 13878 | T19 | 42301 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 125662 | 1 | T18 | 4468 | T22 | 1326 | T23 | 3416 | ||||
auto[1] | 3675 | 1 | T18 | 160 | T22 | 40 | T23 | 121 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 90976 | 1 | T18 | 3192 | T22 | 885 | T23 | 2531 | ||||
auto[1] | 38361 | 1 | T18 | 1436 | T22 | 481 | T23 | 1006 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 129337 | 0 | T18 | 4628 | T22 | 1366 | T23 | 3537 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 129337 | 0 | T18 | 4628 | T22 | 1366 | T23 | 3537 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 129337 | 0 | T18 | 4628 | T22 | 1366 | T23 | 3537 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
covered | 45027 | 1 | T18 | 1573 | T22 | 353 | T23 | 1185 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 125285 | 1 | T18 | 4512 | T22 | 1327 | T23 | 3389 | ||||
auto[1] | 4052 | 1 | T18 | 116 | T22 | 39 | T23 | 148 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 91209 | 1 | T18 | 3285 | T22 | 913 | T23 | 2460 | ||||
auto[1] | 38128 | 1 | T18 | 1343 | T22 | 453 | T23 | 1077 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |