Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14160562	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59795970

1

T1

1407

T2

4971

T3

3983

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36860827	1			T1	846		T2	2489		T3	1989
values[0x0]	17128365	1			T1	386		T2	1222		T3	963
values[0x1]	19967340	1			T1	505		T2	1260		T3	1031

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7055697	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66900835

1

T1

1562

T2

4971

T3

3983

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	262273	1			T2	17		T4	867		T9	17
valid_sources[0x01]	293682	1			T2	11		T4	849		T5	1
valid_sources[0x02]	284473	1			T2	13		T4	870		T5	3
valid_sources[0x03]	275573	1			T2	20		T4	875		T5	4
valid_sources[0x04]	254082	1			T2	11		T4	868		T5	1
valid_sources[0x05]	263621	1			T2	15		T4	949		T5	1
valid_sources[0x06]	333067	1			T2	21		T4	894		T5	2
valid_sources[0x07]	260230	1			T2	20		T4	809		T5	2
valid_sources[0x08]	345685	1			T2	21		T3	1991		T4	870
valid_sources[0x09]	279441	1			T2	23		T4	894		T5	2
valid_sources[0x0a]	253960	1			T2	20		T4	889		T5	10
valid_sources[0x0b]	338606	1			T2	19		T4	969		T5	1
valid_sources[0x0c]	297010	1			T2	18		T4	882		T5	2
valid_sources[0x0d]	286663	1			T2	20		T4	906		T9	25
valid_sources[0x0e]	292937	1			T2	18		T4	827		T5	4
valid_sources[0x0f]	262723	1			T2	16		T4	790		T5	5
valid_sources[0x10]	270769	1			T2	12		T4	928		T5	1
valid_sources[0x11]	300509	1			T1	869		T2	11		T4	832
valid_sources[0x12]	387160	1			T2	17		T4	782		T5	5
valid_sources[0x13]	267348	1			T2	23		T4	893		T5	1
valid_sources[0x14]	290475	1			T2	19		T4	864		T5	6
valid_sources[0x15]	256472	1			T2	21		T4	867		T5	7
valid_sources[0x16]	252144	1			T2	11		T4	807		T5	2
valid_sources[0x17]	269014	1			T2	16		T4	900		T5	1
valid_sources[0x18]	290990	1			T2	17		T4	929		T9	18
valid_sources[0x19]	265446	1			T2	16		T4	905		T5	3
valid_sources[0x1a]	277939	1			T2	14		T4	909		T5	7
valid_sources[0x1b]	296143	1			T2	20		T4	930		T5	10
valid_sources[0x1c]	251921	1			T2	21		T4	919		T5	1
valid_sources[0x1d]	293214	1			T2	22		T4	878		T5	2
valid_sources[0x1e]	364979	1			T2	16		T4	921		T5	6
valid_sources[0x1f]	293690	1			T2	14		T4	809		T5	2
valid_sources[0x20]	265312	1			T2	9		T4	784		T5	3
valid_sources[0x21]	272269	1			T2	21		T4	859		T5	6
valid_sources[0x22]	264975	1			T2	18		T4	858		T5	9
valid_sources[0x23]	270668	1			T2	21		T4	898		T5	1
valid_sources[0x24]	293816	1			T2	18		T4	778		T5	6
valid_sources[0x25]	310848	1			T2	21		T4	787		T5	1
valid_sources[0x26]	272329	1			T2	17		T4	908		T5	1
valid_sources[0x27]	344257	1			T2	14		T4	979		T5	1
valid_sources[0x28]	273881	1			T2	21		T4	886		T5	10
valid_sources[0x29]	268432	1			T2	15		T4	891		T9	26
valid_sources[0x2a]	276462	1			T2	12		T4	861		T5	2
valid_sources[0x2b]	316538	1			T2	34		T4	833		T5	6
valid_sources[0x2c]	257467	1			T2	22		T4	811		T5	5
valid_sources[0x2d]	253478	1			T2	16		T4	922		T5	4
valid_sources[0x2e]	274844	1			T2	15		T4	904		T5	5
valid_sources[0x2f]	279670	1			T2	29		T4	821		T5	1
valid_sources[0x30]	267851	1			T2	17		T4	781		T9	19
valid_sources[0x31]	317093	1			T2	34		T4	853		T5	3
valid_sources[0x32]	300449	1			T2	12		T4	813		T5	1
valid_sources[0x33]	266379	1			T2	21		T4	791		T5	3
valid_sources[0x34]	258263	1			T2	30		T4	868		T5	6
valid_sources[0x35]	264582	1			T2	22		T4	901		T5	6
valid_sources[0x36]	272242	1			T2	25		T4	944		T9	27
valid_sources[0x37]	273549	1			T2	28		T4	804		T5	5
valid_sources[0x38]	339768	1			T2	13		T4	985		T5	8
valid_sources[0x39]	295344	1			T2	27		T4	817		T5	3
valid_sources[0x3a]	293984	1			T2	35		T4	829		T5	2
valid_sources[0x3b]	269366	1			T2	16		T4	832		T5	2
valid_sources[0x3c]	313618	1			T2	24		T4	795		T5	4
valid_sources[0x3d]	258827	1			T2	8		T4	771		T5	7
valid_sources[0x3e]	284323	1			T2	26		T4	846		T5	4
valid_sources[0x3f]	387406	1			T2	31		T4	910		T5	1
valid_sources[0x40]	294201	1			T2	19		T4	812		T5	2
valid_sources[0x41]	262138	1			T2	12		T4	836		T5	1
valid_sources[0x42]	280285	1			T2	24		T4	812		T5	1
valid_sources[0x43]	297422	1			T2	14		T4	814		T5	2
valid_sources[0x44]	278839	1			T2	30		T4	835		T5	6
valid_sources[0x45]	266929	1			T2	16		T4	885		T5	8
valid_sources[0x46]	271612	1			T2	26		T4	807		T5	3
valid_sources[0x47]	261157	1			T2	15		T4	853		T5	7
valid_sources[0x48]	318784	1			T2	23		T4	884		T9	11
valid_sources[0x49]	275394	1			T2	21		T4	867		T5	2
valid_sources[0x4a]	275711	1			T2	22		T4	871		T5	5
valid_sources[0x4b]	259565	1			T2	19		T4	894		T5	3
valid_sources[0x4c]	390293	1			T2	18		T4	784		T9	20
valid_sources[0x4d]	267456	1			T2	15		T4	868		T5	3
valid_sources[0x4e]	284759	1			T2	21		T4	814		T5	8
valid_sources[0x4f]	325566	1			T2	15		T4	831		T5	3
valid_sources[0x50]	270207	1			T2	9		T4	831		T5	1
valid_sources[0x51]	271954	1			T2	24		T4	823		T5	3
valid_sources[0x52]	304659	1			T2	23		T4	832		T5	2
valid_sources[0x53]	328817	1			T2	25		T4	914		T5	1
valid_sources[0x54]	279880	1			T2	36		T4	897		T5	5
valid_sources[0x55]	278725	1			T2	23		T4	911		T5	1
valid_sources[0x56]	265799	1			T2	19		T4	851		T5	4
valid_sources[0x57]	301307	1			T2	20		T4	832		T5	8
valid_sources[0x58]	268741	1			T2	15		T4	876		T9	21
valid_sources[0x59]	297134	1			T2	16		T4	794		T5	4
valid_sources[0x5a]	285450	1			T2	13		T4	806		T5	6
valid_sources[0x5b]	260370	1			T2	22		T4	849		T5	4
valid_sources[0x5c]	285163	1			T2	17		T4	762		T5	3
valid_sources[0x5d]	294118	1			T2	23		T4	687		T5	1
valid_sources[0x5e]	316969	1			T2	17		T4	886		T5	2
valid_sources[0x5f]	284287	1			T2	19		T4	828		T5	5
valid_sources[0x60]	281453	1			T2	19		T4	833		T5	4
valid_sources[0x61]	279344	1			T2	27		T4	884		T9	25
valid_sources[0x62]	298921	1			T2	14		T4	941		T5	4
valid_sources[0x63]	280314	1			T2	16		T4	965		T5	4
valid_sources[0x64]	294239	1			T2	17		T4	908		T5	2
valid_sources[0x65]	260800	1			T2	18		T4	936		T5	4
valid_sources[0x66]	266529	1			T2	17		T4	963		T5	1
valid_sources[0x67]	342971	1			T2	17		T4	824		T5	1
valid_sources[0x68]	280974	1			T2	18		T4	888		T5	2
valid_sources[0x69]	270945	1			T2	20		T4	718		T5	3
valid_sources[0x6a]	265613	1			T2	24		T4	908		T5	5
valid_sources[0x6b]	303905	1			T2	27		T4	858		T5	6
valid_sources[0x6c]	270720	1			T2	21		T4	916		T5	4
valid_sources[0x6d]	325350	1			T2	21		T4	824		T5	4
valid_sources[0x6e]	253227	1			T2	18		T4	897		T5	6
valid_sources[0x6f]	288055	1			T2	18		T4	892		T5	2
valid_sources[0x70]	323818	1			T2	12		T4	838		T5	1
valid_sources[0x71]	270889	1			T2	11		T4	733		T5	4
valid_sources[0x72]	303560	1			T2	31		T4	875		T5	3
valid_sources[0x73]	318210	1			T2	19		T4	983		T5	1
valid_sources[0x74]	324560	1			T2	24		T4	878		T5	4
valid_sources[0x75]	279661	1			T2	15		T4	911		T5	1
valid_sources[0x76]	284661	1			T2	21		T4	839		T5	4
valid_sources[0x77]	250907	1			T2	25		T4	870		T5	4
valid_sources[0x78]	280966	1			T2	24		T4	826		T5	3
valid_sources[0x79]	269040	1			T2	24		T4	912		T5	5
valid_sources[0x7a]	266475	1			T2	18		T4	970		T5	1
valid_sources[0x7b]	283420	1			T2	29		T4	734		T5	2
valid_sources[0x7c]	316168	1			T2	15		T4	753		T9	19
valid_sources[0x7d]	331209	1			T2	8		T4	855		T5	3
valid_sources[0x7e]	283441	1			T2	18		T4	740		T5	4
valid_sources[0x7f]	301781	1			T2	13		T4	763		T5	5
valid_sources[0x80]	345843	1			T2	16		T4	894		T5	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29785053

1

T1

690

T2

2489

T3

1989

values[0x0]

all_enables

biggest_size

15003269

1

T1

330

T2

1222

T3

963

values[0x1]

all_enables

biggest_size

15007648

1

T1

387

T2

1260

T3

1031

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38335	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

149945

1

T2

1

T4

14

T5

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	54028	1			T6	66		T18	1439		T19	20
values[0x0]	64459	1			T3	1		T4	20		T5	2
values[0x1]	69793	1			T1	2		T2	2		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28642	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

159638

1

T2

2

T4

19

T5

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	545	1			T6	2		T22	4		T23	13
valid_sources[0x01]	609	1			T4	1		T22	10		T62	1
valid_sources[0x02]	627	1			T6	3		T44	1		T42	1
valid_sources[0x03]	618	1			T6	1		T18	1		T22	4
valid_sources[0x04]	654	1			T4	1		T6	2		T40	1
valid_sources[0x05]	854	1			T6	2		T22	5		T68	1
valid_sources[0x06]	685	1			T4	1		T18	9		T22	7
valid_sources[0x07]	718	1			T6	3		T44	1		T22	13
valid_sources[0x08]	666	1			T6	1		T18	1		T22	5
valid_sources[0x09]	686	1			T6	1		T18	2		T7	1
valid_sources[0x0a]	736	1			T22	9		T68	1		T23	18
valid_sources[0x0b]	663	1			T20	1		T22	8		T14	2
valid_sources[0x0c]	1062	1			T6	1		T7	1		T22	3
valid_sources[0x0d]	819	1			T18	143		T8	24		T22	6
valid_sources[0x0e]	884	1			T4	1		T6	1		T18	70
valid_sources[0x0f]	595	1			T6	5		T18	4		T44	1
valid_sources[0x10]	1644	1			T6	2		T18	176		T7	1
valid_sources[0x11]	880	1			T7	1		T22	12		T150	1
valid_sources[0x12]	654	1			T4	2		T22	12		T62	4
valid_sources[0x13]	504	1			T6	1		T18	1		T44	1
valid_sources[0x14]	796	1			T18	187		T22	15		T68	2
valid_sources[0x15]	677	1			T4	1		T6	1		T44	2
valid_sources[0x16]	806	1			T6	2		T22	5		T23	13
valid_sources[0x17]	685	1			T6	1		T18	149		T96	24
valid_sources[0x18]	652	1			T4	1		T6	1		T18	2
valid_sources[0x19]	909	1			T6	1		T18	2		T22	5
valid_sources[0x1a]	734	1			T6	1		T18	1		T22	6
valid_sources[0x1b]	662	1			T6	2		T18	3		T44	1
valid_sources[0x1c]	695	1			T18	6		T22	8		T62	1
valid_sources[0x1d]	573	1			T22	12		T62	2		T84	6
valid_sources[0x1e]	850	1			T6	2		T12	3		T18	125
valid_sources[0x1f]	492	1			T6	1		T18	3		T22	3
valid_sources[0x20]	601	1			T18	2		T20	1		T42	1
valid_sources[0x21]	622	1			T4	1		T40	1		T41	2
valid_sources[0x22]	906	1			T18	263		T22	5		T21	1
valid_sources[0x23]	657	1			T18	161		T44	1		T22	6
valid_sources[0x24]	1031	1			T6	2		T22	9		T23	13
valid_sources[0x25]	765	1			T18	1		T7	1		T44	1
valid_sources[0x26]	827	1			T6	2		T18	151		T22	7
valid_sources[0x27]	837	1			T6	2		T22	3		T21	1
valid_sources[0x28]	887	1			T4	1		T6	2		T18	1
valid_sources[0x29]	773	1			T44	1		T22	5		T68	1
valid_sources[0x2a]	632	1			T4	1		T22	4		T62	1
valid_sources[0x2b]	649	1			T6	1		T18	20		T44	3
valid_sources[0x2c]	637	1			T18	5		T7	1		T44	2
valid_sources[0x2d]	510	1			T10	1		T18	1		T40	1
valid_sources[0x2e]	538	1			T4	1		T44	2		T151	2
valid_sources[0x2f]	609	1			T6	1		T22	6		T62	2
valid_sources[0x30]	592	1			T7	2		T22	6		T23	22
valid_sources[0x31]	833	1			T6	3		T18	48		T22	3
valid_sources[0x32]	688	1			T7	1		T20	2		T22	8
valid_sources[0x33]	740	1			T6	3		T22	6		T62	1
valid_sources[0x34]	758	1			T6	2		T18	132		T7	1
valid_sources[0x35]	666	1			T6	3		T18	1		T7	2
valid_sources[0x36]	1278	1			T6	1		T18	168		T44	1
valid_sources[0x37]	817	1			T18	1		T7	1		T22	7
valid_sources[0x38]	558	1			T22	5		T21	2		T68	1
valid_sources[0x39]	728	1			T6	2		T22	6		T21	1
valid_sources[0x3a]	617	1			T6	2		T7	1		T22	11
valid_sources[0x3b]	807	1			T18	5		T44	1		T22	6
valid_sources[0x3c]	1143	1			T6	1		T18	8		T22	5
valid_sources[0x3d]	941	1			T18	84		T22	5		T62	1
valid_sources[0x3e]	839	1			T18	89		T95	2		T22	7
valid_sources[0x3f]	685	1			T6	1		T18	5		T22	7
valid_sources[0x40]	592	1			T6	2		T152	1		T22	5
valid_sources[0x41]	648	1			T6	2		T44	1		T22	11
valid_sources[0x42]	704	1			T6	2		T18	1		T78	1
valid_sources[0x43]	568	1			T18	1		T22	13		T84	1
valid_sources[0x44]	1119	1			T18	82		T41	1		T22	4
valid_sources[0x45]	852	1			T6	4		T18	170		T23	17
valid_sources[0x46]	556	1			T4	1		T22	8		T62	3
valid_sources[0x47]	515	1			T6	1		T22	13		T150	2
valid_sources[0x48]	634	1			T18	91		T22	7		T23	13
valid_sources[0x49]	736	1			T6	3		T18	3		T22	10
valid_sources[0x4a]	622	1			T7	1		T44	2		T20	1
valid_sources[0x4b]	697	1			T6	1		T20	1		T22	5
valid_sources[0x4c]	652	1			T6	1		T20	1		T22	4
valid_sources[0x4d]	624	1			T6	1		T38	7		T22	7
valid_sources[0x4e]	611	1			T6	4		T22	5		T62	2
valid_sources[0x4f]	1077	1			T6	4		T18	39		T22	8
valid_sources[0x50]	582	1			T6	2		T7	2		T22	2
valid_sources[0x51]	999	1			T6	1		T18	75		T22	8
valid_sources[0x52]	632	1			T6	2		T22	4		T150	1
valid_sources[0x53]	564	1			T6	4		T20	1		T22	7
valid_sources[0x54]	518	1			T6	1		T25	1		T22	5
valid_sources[0x55]	1063	1			T18	91		T22	5		T84	1
valid_sources[0x56]	844	1			T6	1		T40	1		T22	4
valid_sources[0x57]	723	1			T6	2		T18	1		T22	5
valid_sources[0x58]	611	1			T18	1		T22	8		T62	1
valid_sources[0x59]	644	1			T26	1		T22	7		T23	8
valid_sources[0x5a]	766	1			T12	1		T18	193		T7	1
valid_sources[0x5b]	901	1			T6	2		T18	3		T44	1
valid_sources[0x5c]	668	1			T22	5		T21	1		T68	1
valid_sources[0x5d]	803	1			T18	1		T22	11		T62	1
valid_sources[0x5e]	707	1			T20	1		T22	7		T62	2
valid_sources[0x5f]	572	1			T6	2		T18	8		T40	1
valid_sources[0x60]	753	1			T18	4		T22	8		T23	16
valid_sources[0x61]	1003	1			T6	1		T7	1		T22	5
valid_sources[0x62]	808	1			T22	9		T23	13		T126	5
valid_sources[0x63]	597	1			T6	2		T18	3		T7	1
valid_sources[0x64]	635	1			T6	1		T18	2		T67	1
valid_sources[0x65]	693	1			T18	5		T49	1		T22	6
valid_sources[0x66]	486	1			T4	1		T6	1		T22	9
valid_sources[0x67]	815	1			T6	5		T18	2		T22	6
valid_sources[0x68]	653	1			T2	2		T12	1		T18	1
valid_sources[0x69]	640	1			T6	4		T12	1		T18	3
valid_sources[0x6a]	884	1			T4	1		T6	3		T22	8
valid_sources[0x6b]	784	1			T6	1		T7	1		T22	5
valid_sources[0x6c]	645	1			T4	1		T40	1		T44	1
valid_sources[0x6d]	936	1			T6	2		T18	1		T7	1
valid_sources[0x6e]	607	1			T6	1		T44	1		T22	7
valid_sources[0x6f]	869	1			T18	3		T22	8		T62	1
valid_sources[0x70]	775	1			T6	1		T7	1		T22	3
valid_sources[0x71]	477	1			T6	4		T22	7		T21	1
valid_sources[0x72]	778	1			T18	37		T22	6		T21	1
valid_sources[0x73]	1204	1			T6	1		T44	2		T22	5
valid_sources[0x74]	934	1			T7	1		T22	8		T68	1
valid_sources[0x75]	661	1			T22	5		T21	2		T68	1
valid_sources[0x76]	733	1			T4	2		T22	12		T150	2
valid_sources[0x77]	797	1			T6	3		T20	1		T22	6
valid_sources[0x78]	864	1			T44	2		T22	8		T62	2
valid_sources[0x79]	541	1			T7	1		T22	4		T62	2
valid_sources[0x7a]	641	1			T6	1		T7	1		T20	1
valid_sources[0x7b]	736	1			T6	2		T18	1		T44	1
valid_sources[0x7c]	622	1			T6	3		T20	1		T95	1
valid_sources[0x7d]	495	1			T7	1		T20	1		T22	12
valid_sources[0x7e]	517	1			T6	1		T44	1		T22	4
valid_sources[0x7f]	625	1			T3	1		T6	1		T21	2
valid_sources[0x80]	661	1			T6	2		T18	92		T44	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

40603

1

T6

32

T18

1338

T19

13

values[0x0]

all_enables

biggest_size

55726

1

T4

8

T5

1

T6

38

values[0x1]

all_enables

biggest_size

53616

1

T2

1

T4

6

T6

24