Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13856737

1

T1

330

T4

19793

T5

873

full_word

54657309

1

T1

1407

T2

4971

T3

3983

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	68513706	1			T1	1737		T2	4971		T3	3983
auto[TlIntgErrCmd]	100	1			T58	3		T59	5		T125	7
auto[TlIntgErrData]	116	1			T57	8		T58	4		T59	8
auto[TlIntgErrBoth]	124	1			T57	2		T58	3		T59	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31329331

1

T1

846

T2

2489

T3

1989

auto[1]

37184715

1

T1

891

T2

2482

T3

1994

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6610777	1			T1	156		T4	9882		T5	376
auto[TlIntgErrNone]	partial	auto[1]	7245645	1			T1	174		T4	9911		T5	497
auto[TlIntgErrNone]	full_word	auto[0]	24718394	1			T1	690		T2	2489		T3	1989
auto[TlIntgErrNone]	full_word	auto[1]	29938890	1			T1	717		T2	2482		T3	1994
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T58	1		T59	3		T125	2
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T58	2		T59	2		T125	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T125	2		T128	1		T133	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T134	1		T135	1		-	-
auto[TlIntgErrData]	partial	auto[0]	64	1			T57	6		T58	1		T59	5
auto[TlIntgErrData]	partial	auto[1]	43	1			T57	2		T58	3		T59	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T136	1		T135	1		T133	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T125	1		T137	2		T127	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T57	1		T58	1		T59	2
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T57	1		T58	1		T59	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T138	1		T136	1		T127	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T58	1		T59	1		T136	1