Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg
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Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
mem_bkdr_scb 100.00 1 100 1 64 64




Group Instance : mem_bkdr_scb
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mem_bkdr_scb

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group Instance mem_bkdr_scb
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
b2b_access_types_cp 4 0 4 100.00 100 1 1 4
b2b_partial_types_cp 4 0 4 100.00 100 1 1 4
raw_hazard_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance mem_bkdr_scb
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
all_cross 32 0 32 100.00 100 1 1 0


Summary for Variable b2b_access_types_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for b2b_access_types_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 643418 1 T19 25 T39 15 T7 8
auto[1] 10794844 1 T1 846 T2 2488 T3 1984
auto[2] 552056 1 T19 41 T39 12 T7 11
auto[3] 10706816 1 T1 890 T2 2481 T3 1993



Summary for Variable b2b_partial_types_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for b2b_partial_types_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14520034 1 T1 1141 T2 4969 T3 3977
auto[1] 2184682 1 T1 265 T4 8004 T9 802
auto[2] 2207430 1 T1 269 T4 7987 T9 780
auto[3] 3784988 1 T1 61 T4 792 T9 3398



Summary for Variable raw_hazard_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for raw_hazard_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9192650 1 T1 1735 T2 4967 T3 3975
auto[1] 13504484 1 T1 1 T2 2 T3 2



Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for all_cross

Bins
raw_hazard_cpb2b_access_types_cpb2b_partial_types_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 311435 1 T19 21 T7 5 T44 825
auto[0] auto[0] auto[1] 32413 1 T19 1 T7 2 T44 76
auto[0] auto[0] auto[2] 32500 1 T19 3 T7 1 T44 92
auto[0] auto[0] auto[3] 10057 1 T39 15 T44 13 T78 316
auto[0] auto[1] auto[0] 3479831 1 T1 565 T2 2487 T3 1984
auto[0] auto[1] auto[1] 361163 1 T1 125 T4 3789 T9 414
auto[0] auto[1] auto[2] 347115 1 T1 129 T4 4176 T9 392
auto[0] auto[1] auto[3] 69355 1 T1 27 T4 402 T9 1638
auto[0] auto[2] auto[0] 271971 1 T7 9 T44 546 T78 17
auto[0] auto[2] auto[1] 28194 1 T7 1 T44 50 T78 55
auto[0] auto[2] auto[2] 28805 1 T19 39 T44 66 T20 38
auto[0] auto[2] auto[3] 8088 1 T19 2 T39 12 T7 1
auto[0] auto[3] auto[0] 3439181 1 T1 575 T2 2480 T3 1991
auto[0] auto[3] auto[1] 343476 1 T1 140 T4 4211 T9 388
auto[0] auto[3] auto[2] 359002 1 T1 140 T4 3805 T9 387
auto[0] auto[3] auto[3] 70064 1 T1 34 T4 390 T9 1756
auto[1] auto[0] auto[0] 8633 1 T44 1 T94 254 T145 3
auto[1] auto[0] auto[1] 38257 1 T94 1109 T102 676 T146 2
auto[1] auto[0] auto[2] 38204 1 T94 1186 T147 1 T102 732
auto[1] auto[0] auto[3] 171919 1 T94 5302 T102 3274 T144 3786
auto[1] auto[1] auto[0] 3505047 1 T2 1 T4 40 T11 1
auto[1] auto[1] auto[1] 684288 1 T4 2 T6 6 T18 1
auto[1] auto[1] auto[2] 688040 1 T4 3 T6 5 T18 1
auto[1] auto[1] auto[3] 1660005 1 T9 4 T77 864 T94 6006
auto[1] auto[2] auto[0] 5417 1 T94 146 T141 1 T145 5
auto[1] auto[2] auto[1] 22916 1 T94 701 T148 4 T146 3
auto[1] auto[2] auto[2] 33905 1 T94 1247 T102 631 T146 3
auto[1] auto[2] auto[3] 152760 1 T94 5833 T102 3022 T144 3307
auto[1] auto[3] auto[0] 3498519 1 T1 1 T2 1 T3 2
auto[1] auto[3] auto[1] 673975 1 T4 2 T6 3 T40 1
auto[1] auto[3] auto[2] 679859 1 T4 3 T9 1 T6 4
auto[1] auto[3] auto[3] 1642740 1 T6 1 T77 818 T94 6568

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