Line Coverage for Module :
prim_sync_reqack_data
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 0 | 0 | |
CONT_ASSIGN | 156 | 0 | 0 | |
ALWAYS | 159 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
93 |
1 |
1 |
153 |
|
unreachable |
156 |
|
unreachable |
159 |
|
unreachable |
160 |
|
unreachable |
162 |
|
unreachable |
Assert Coverage for Module :
prim_sync_reqack_data
Assertion Details
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
303807181 |
9038 |
0 |
0 |
T1 |
5562 |
2 |
0 |
0 |
T2 |
7812 |
2 |
0 |
0 |
T3 |
7760 |
2 |
0 |
0 |
T4 |
403848 |
43 |
0 |
0 |
T5 |
10875 |
1 |
0 |
0 |
T6 |
123661 |
75 |
0 |
0 |
T9 |
11799 |
1 |
0 |
0 |
T10 |
8056 |
2 |
0 |
0 |
T11 |
3864 |
2 |
0 |
0 |
T12 |
1084 |
0 |
0 |
0 |
T18 |
0 |
38 |
0 |
0 |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
303807181 |
9038 |
0 |
0 |
T1 |
5562 |
2 |
0 |
0 |
T2 |
7812 |
2 |
0 |
0 |
T3 |
7760 |
2 |
0 |
0 |
T4 |
403848 |
43 |
0 |
0 |
T5 |
10875 |
1 |
0 |
0 |
T6 |
123661 |
75 |
0 |
0 |
T9 |
11799 |
1 |
0 |
0 |
T10 |
8056 |
2 |
0 |
0 |
T11 |
3864 |
2 |
0 |
0 |
T12 |
1084 |
0 |
0 |
0 |
T18 |
0 |
38 |
0 |
0 |