Line Coverage for Module :
prim_generic_ram_1p
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 42 | 1 | 1 | 100.00 |
CONT_ASSIGN | 52 | 1 | 1 | 100.00 |
ALWAYS | 63 | 6 | 6 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
42 |
1 |
1 |
52 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
66 |
1 |
1 |
67 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
Branch Coverage for Module :
prim_generic_ram_1p
| Line No. | Total | Covered | Percent |
Branches |
|
3 |
3 |
100.00 |
IF |
63 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 63 if (req_i)
-2-: 64 if (write_i)
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T1,T2,T3 |
1 |
0 |
Covered |
T1,T2,T3 |
0 |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_generic_ram_1p
Assertion Details
DataBitsPerMaskCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
894 |
894 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
gen_wmask[0].MaskCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
303807181 |
35128136 |
0 |
0 |
T1 |
5562 |
2939 |
0 |
0 |
T2 |
7812 |
4530 |
0 |
0 |
T3 |
7760 |
4042 |
0 |
0 |
T4 |
403848 |
153364 |
0 |
0 |
T5 |
10875 |
1577 |
0 |
0 |
T6 |
123661 |
239027 |
0 |
0 |
T9 |
11799 |
3668 |
0 |
0 |
T10 |
8056 |
2989 |
0 |
0 |
T11 |
3864 |
2580 |
0 |
0 |
T12 |
1084 |
0 |
0 |
0 |
T18 |
0 |
52295 |
0 |
0 |