Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	305030638	226053	0	0
ctrl_regwen_rd_A	305030638	3080	0	0
exec_rd_A	305030638	3159	0	0
exec_regwen_rd_A	305030638	3424	0	0
readback_rd_A	305030638	1678	0	0
readback_regwen_rd_A	305030638	1573	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305030638	226053	0	0
T7	76629	0	0	0
T13	823	0	0	0
T18	203240	7615	0	0
T19	137891	0	0	0
T22	0	2157	0	0
T23	0	7144	0	0
T24	1958	0	0	0
T38	33662	0	0	0
T39	8400	0	0	0
T40	327405	0	0	0
T41	44134	0	0	0
T52	0	7219	0	0
T53	0	8428	0	0
T54	0	9516	0	0
T55	0	8064	0	0
T64	0	5415	0	0
T65	0	1347	0	0
T66	0	3995	0	0
T67	102989	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305030638	3080	0	0
T65	126941	151	0	0
T97	0	24	0	0
T107	0	241	0	0
T108	0	50	0	0
T109	0	80	0	0
T110	0	340	0	0
T111	0	290	0	0
T112	0	114	0	0
T113	0	314	0	0
T114	0	10	0	0
T115	50509	0	0	0
T116	11090	0	0	0
T117	1768	0	0	0
T118	21027	0	0	0
T119	8308	0	0	0
T120	332852	0	0	0
T121	15816	0	0	0
T122	81039	0	0	0
T123	1186	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305030638	3159	0	0
T65	126941	145	0	0
T97	0	81	0	0
T107	0	342	0	0
T108	0	54	0	0
T109	0	64	0	0
T110	0	372	0	0
T111	0	294	0	0
T112	0	74	0	0
T113	0	204	0	0
T114	0	7	0	0
T115	50509	0	0	0
T116	11090	0	0	0
T117	1768	0	0	0
T118	21027	0	0	0
T119	8308	0	0	0
T120	332852	0	0	0
T121	15816	0	0	0
T122	81039	0	0	0
T123	1186	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305030638	3424	0	0
T65	126941	130	0	0
T97	0	35	0	0
T107	0	337	0	0
T108	0	48	0	0
T109	0	92	0	0
T110	0	469	0	0
T111	0	291	0	0
T112	0	117	0	0
T113	0	348	0	0
T114	0	12	0	0
T115	50509	0	0	0
T116	11090	0	0	0
T117	1768	0	0	0
T118	21027	0	0	0
T119	8308	0	0	0
T120	332852	0	0	0
T121	15816	0	0	0
T122	81039	0	0	0
T123	1186	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305030638	1678	0	0
T65	126941	104	0	0
T107	0	244	0	0
T108	0	32	0	0
T109	0	88	0	0
T110	0	330	0	0
T111	0	295	0	0
T112	0	87	0	0
T113	0	285	0	0
T115	50509	0	0	0
T116	11090	0	0	0
T117	1768	0	0	0
T118	21027	0	0	0
T119	8308	0	0	0
T120	332852	0	0	0
T121	15816	0	0	0
T122	81039	0	0	0
T123	1186	0	0	0
T124	0	19	0	0
T125	0	3	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305030638	1573	0	0
T65	126941	78	0	0
T107	0	240	0	0
T108	0	83	0	0
T109	0	96	0	0
T110	0	309	0	0
T111	0	241	0	0
T112	0	67	0	0
T113	0	212	0	0
T114	0	8	0	0
T115	50509	0	0	0
T116	11090	0	0	0
T117	1768	0	0	0
T118	21027	0	0	0
T119	8308	0	0	0
T120	332852	0	0	0
T121	15816	0	0	0
T122	81039	0	0	0
T123	1186	0	0	0
T124	0	36	0	0