SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.90 | 100.00 | 88.89 | 100.00 | 100.00 | 70.59 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
89.00 | 100.00 | 100.00 | 100.00 | 95.00 | 50.00 | u_tlul_lc_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1788 | 1788 | 0 | 0 |
OutputsKnown_A | 607614362 | 607386198 | 0 | 0 |
gen_flops.OutputDelay_A | 303807181 | 303680711 | 0 | 2682 |
gen_no_flops.OutputDelay_A | 303807181 | 303693099 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1788 | 1788 | 0 | 0 |
T1 | 2 | 2 | 0 | 0 |
T2 | 2 | 2 | 0 | 0 |
T3 | 2 | 2 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T5 | 2 | 2 | 0 | 0 |
T6 | 2 | 2 | 0 | 0 |
T9 | 2 | 2 | 0 | 0 |
T10 | 2 | 2 | 0 | 0 |
T11 | 2 | 2 | 0 | 0 |
T12 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 607614362 | 607386198 | 0 | 0 |
T1 | 11124 | 11014 | 0 | 0 |
T2 | 15624 | 15498 | 0 | 0 |
T3 | 15520 | 15396 | 0 | 0 |
T4 | 807696 | 807562 | 0 | 0 |
T5 | 21750 | 21582 | 0 | 0 |
T6 | 247322 | 247216 | 0 | 0 |
T9 | 23598 | 23432 | 0 | 0 |
T10 | 16112 | 15948 | 0 | 0 |
T11 | 7728 | 7620 | 0 | 0 |
T12 | 2168 | 2048 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 303807181 | 303680711 | 0 | 2682 |
T1 | 5562 | 5504 | 0 | 3 |
T2 | 7812 | 7746 | 0 | 3 |
T3 | 7760 | 7695 | 0 | 3 |
T4 | 403848 | 403778 | 0 | 3 |
T5 | 10875 | 10788 | 0 | 3 |
T6 | 123661 | 123596 | 0 | 3 |
T9 | 11799 | 11713 | 0 | 3 |
T10 | 8056 | 7971 | 0 | 3 |
T11 | 3864 | 3807 | 0 | 3 |
T12 | 1084 | 1021 | 0 | 3 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 303807181 | 303693099 | 0 | 0 |
T1 | 5562 | 5507 | 0 | 0 |
T2 | 7812 | 7749 | 0 | 0 |
T3 | 7760 | 7698 | 0 | 0 |
T4 | 403848 | 403781 | 0 | 0 |
T5 | 10875 | 10791 | 0 | 0 |
T6 | 123661 | 123608 | 0 | 0 |
T9 | 11799 | 11716 | 0 | 0 |
T10 | 8056 | 7974 | 0 | 0 |
T11 | 3864 | 3810 | 0 | 0 |
T12 | 1084 | 1024 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 894 | 894 | 0 | 0 |
OutputsKnown_A | 303807181 | 303693099 | 0 | 0 |
gen_flops.OutputDelay_A | 303807181 | 303680711 | 0 | 2682 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 894 | 894 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 303807181 | 303693099 | 0 | 0 |
T1 | 5562 | 5507 | 0 | 0 |
T2 | 7812 | 7749 | 0 | 0 |
T3 | 7760 | 7698 | 0 | 0 |
T4 | 403848 | 403781 | 0 | 0 |
T5 | 10875 | 10791 | 0 | 0 |
T6 | 123661 | 123608 | 0 | 0 |
T9 | 11799 | 11716 | 0 | 0 |
T10 | 8056 | 7974 | 0 | 0 |
T11 | 3864 | 3810 | 0 | 0 |
T12 | 1084 | 1024 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 303807181 | 303680711 | 0 | 2682 |
T1 | 5562 | 5504 | 0 | 3 |
T2 | 7812 | 7746 | 0 | 3 |
T3 | 7760 | 7695 | 0 | 3 |
T4 | 403848 | 403778 | 0 | 3 |
T5 | 10875 | 10788 | 0 | 3 |
T6 | 123661 | 123596 | 0 | 3 |
T9 | 11799 | 11713 | 0 | 3 |
T10 | 8056 | 7971 | 0 | 3 |
T11 | 3864 | 3807 | 0 | 3 |
T12 | 1084 | 1021 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 894 | 894 | 0 | 0 |
OutputsKnown_A | 303807181 | 303693099 | 0 | 0 |
gen_no_flops.OutputDelay_A | 303807181 | 303693099 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 894 | 894 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 303807181 | 303693099 | 0 | 0 |
T1 | 5562 | 5507 | 0 | 0 |
T2 | 7812 | 7749 | 0 | 0 |
T3 | 7760 | 7698 | 0 | 0 |
T4 | 403848 | 403781 | 0 | 0 |
T5 | 10875 | 10791 | 0 | 0 |
T6 | 123661 | 123608 | 0 | 0 |
T9 | 11799 | 11716 | 0 | 0 |
T10 | 8056 | 7974 | 0 | 0 |
T11 | 3864 | 3810 | 0 | 0 |
T12 | 1084 | 1024 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 303807181 | 303693099 | 0 | 0 |
T1 | 5562 | 5507 | 0 | 0 |
T2 | 7812 | 7749 | 0 | 0 |
T3 | 7760 | 7698 | 0 | 0 |
T4 | 403848 | 403781 | 0 | 0 |
T5 | 10875 | 10791 | 0 | 0 |
T6 | 123661 | 123608 | 0 | 0 |
T9 | 11799 | 11716 | 0 | 0 |
T10 | 8056 | 7974 | 0 | 0 |
T11 | 3864 | 3810 | 0 | 0 |
T12 | 1084 | 1024 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |