| T800 |
/workspace/coverage/default/37.sram_ctrl_smoke.1195627148 |
|
|
Jun 29 06:56:17 PM PDT 24 |
Jun 29 06:56:32 PM PDT 24 |
155743215 ps |
| T801 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.2600408129 |
|
|
Jun 29 06:55:25 PM PDT 24 |
Jun 29 06:55:31 PM PDT 24 |
3283242476 ps |
| T802 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.1349923677 |
|
|
Jun 29 06:54:38 PM PDT 24 |
Jun 29 06:54:50 PM PDT 24 |
2304370344 ps |
| T803 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.4110821910 |
|
|
Jun 29 06:54:57 PM PDT 24 |
Jun 29 07:14:58 PM PDT 24 |
56417183580 ps |
| T804 |
/workspace/coverage/default/1.sram_ctrl_bijection.1532302020 |
|
|
Jun 29 06:53:52 PM PDT 24 |
Jun 29 06:55:08 PM PDT 24 |
3653427901 ps |
| T805 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.3167242517 |
|
|
Jun 29 06:53:51 PM PDT 24 |
Jun 29 06:53:57 PM PDT 24 |
76234145 ps |
| T806 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3207868405 |
|
|
Jun 29 06:56:19 PM PDT 24 |
Jun 29 07:03:19 PM PDT 24 |
61291181385 ps |
| T807 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2687831056 |
|
|
Jun 29 06:54:05 PM PDT 24 |
Jun 29 06:59:09 PM PDT 24 |
6297285632 ps |
| T808 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.2018834090 |
|
|
Jun 29 06:54:41 PM PDT 24 |
Jun 29 06:58:45 PM PDT 24 |
821747120 ps |
| T809 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.2522968146 |
|
|
Jun 29 06:54:04 PM PDT 24 |
Jun 29 06:54:09 PM PDT 24 |
283878589 ps |
| T810 |
/workspace/coverage/default/43.sram_ctrl_partial_access.3124938449 |
|
|
Jun 29 06:56:56 PM PDT 24 |
Jun 29 06:57:11 PM PDT 24 |
333374498 ps |
| T811 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3250007966 |
|
|
Jun 29 06:54:10 PM PDT 24 |
Jun 29 06:54:19 PM PDT 24 |
594681346 ps |
| T27 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.1861179601 |
|
|
Jun 29 06:54:03 PM PDT 24 |
Jun 29 06:54:06 PM PDT 24 |
904743684 ps |
| T812 |
/workspace/coverage/default/9.sram_ctrl_smoke.4041261154 |
|
|
Jun 29 06:54:11 PM PDT 24 |
Jun 29 06:54:14 PM PDT 24 |
49631410 ps |
| T113 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1500534694 |
|
|
Jun 29 06:55:46 PM PDT 24 |
Jun 29 06:57:07 PM PDT 24 |
1350927118 ps |
| T813 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.624935947 |
|
|
Jun 29 06:56:26 PM PDT 24 |
Jun 29 06:56:36 PM PDT 24 |
181910630 ps |
| T814 |
/workspace/coverage/default/35.sram_ctrl_alert_test.1423746169 |
|
|
Jun 29 06:56:09 PM PDT 24 |
Jun 29 06:56:10 PM PDT 24 |
34319543 ps |
| T815 |
/workspace/coverage/default/12.sram_ctrl_alert_test.3510073140 |
|
|
Jun 29 06:54:29 PM PDT 24 |
Jun 29 06:54:31 PM PDT 24 |
14516297 ps |
| T816 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.1542688563 |
|
|
Jun 29 06:54:37 PM PDT 24 |
Jun 29 06:54:46 PM PDT 24 |
2685640104 ps |
| T817 |
/workspace/coverage/default/47.sram_ctrl_bijection.2218242251 |
|
|
Jun 29 06:57:16 PM PDT 24 |
Jun 29 06:58:17 PM PDT 24 |
6451650415 ps |
| T818 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.2794433525 |
|
|
Jun 29 06:54:11 PM PDT 24 |
Jun 29 06:54:17 PM PDT 24 |
234656151 ps |
| T819 |
/workspace/coverage/default/44.sram_ctrl_executable.4225727170 |
|
|
Jun 29 06:57:01 PM PDT 24 |
Jun 29 07:11:33 PM PDT 24 |
9054040536 ps |
| T820 |
/workspace/coverage/default/21.sram_ctrl_smoke.4016425337 |
|
|
Jun 29 06:54:57 PM PDT 24 |
Jun 29 06:55:15 PM PDT 24 |
743314318 ps |
| T821 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.2761331257 |
|
|
Jun 29 06:55:47 PM PDT 24 |
Jun 29 06:55:48 PM PDT 24 |
27755593 ps |
| T822 |
/workspace/coverage/default/5.sram_ctrl_regwen.2439150591 |
|
|
Jun 29 06:54:09 PM PDT 24 |
Jun 29 07:02:11 PM PDT 24 |
2042873013 ps |
| T823 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.2730518969 |
|
|
Jun 29 06:55:46 PM PDT 24 |
Jun 29 06:55:48 PM PDT 24 |
222640781 ps |
| T824 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.3238272625 |
|
|
Jun 29 06:56:04 PM PDT 24 |
Jun 29 07:25:20 PM PDT 24 |
15020932996 ps |
| T825 |
/workspace/coverage/default/36.sram_ctrl_smoke.1508009510 |
|
|
Jun 29 06:56:11 PM PDT 24 |
Jun 29 06:56:19 PM PDT 24 |
2049552835 ps |
| T826 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.3243065297 |
|
|
Jun 29 06:57:23 PM PDT 24 |
Jun 29 06:59:07 PM PDT 24 |
124714697 ps |
| T827 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1340174749 |
|
|
Jun 29 06:54:19 PM PDT 24 |
Jun 29 06:54:25 PM PDT 24 |
159073084 ps |
| T828 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.1944467806 |
|
|
Jun 29 06:57:23 PM PDT 24 |
Jun 29 06:57:51 PM PDT 24 |
187449762 ps |
| T85 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.1641907851 |
|
|
Jun 29 06:54:18 PM PDT 24 |
Jun 29 06:54:22 PM PDT 24 |
500133902 ps |
| T829 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.954206893 |
|
|
Jun 29 06:54:56 PM PDT 24 |
Jun 29 07:03:08 PM PDT 24 |
18678210741 ps |
| T830 |
/workspace/coverage/default/17.sram_ctrl_executable.1210103036 |
|
|
Jun 29 06:54:38 PM PDT 24 |
Jun 29 07:01:57 PM PDT 24 |
36926483626 ps |
| T831 |
/workspace/coverage/default/42.sram_ctrl_regwen.1690057673 |
|
|
Jun 29 06:56:45 PM PDT 24 |
Jun 29 07:09:17 PM PDT 24 |
17862022357 ps |
| T832 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.3980083522 |
|
|
Jun 29 06:54:11 PM PDT 24 |
Jun 29 06:55:36 PM PDT 24 |
1377864759 ps |
| T833 |
/workspace/coverage/default/19.sram_ctrl_smoke.3804915530 |
|
|
Jun 29 06:54:46 PM PDT 24 |
Jun 29 06:54:57 PM PDT 24 |
333299521 ps |
| T834 |
/workspace/coverage/default/21.sram_ctrl_regwen.3447313759 |
|
|
Jun 29 06:54:57 PM PDT 24 |
Jun 29 06:56:46 PM PDT 24 |
463251776 ps |
| T835 |
/workspace/coverage/default/48.sram_ctrl_alert_test.1568213115 |
|
|
Jun 29 06:57:30 PM PDT 24 |
Jun 29 06:57:31 PM PDT 24 |
16729424 ps |
| T836 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.2620825044 |
|
|
Jun 29 06:55:09 PM PDT 24 |
Jun 29 06:59:37 PM PDT 24 |
27257032025 ps |
| T837 |
/workspace/coverage/default/42.sram_ctrl_smoke.1607471260 |
|
|
Jun 29 06:56:44 PM PDT 24 |
Jun 29 06:56:55 PM PDT 24 |
1102289510 ps |
| T838 |
/workspace/coverage/default/37.sram_ctrl_regwen.2182790641 |
|
|
Jun 29 06:56:19 PM PDT 24 |
Jun 29 07:11:15 PM PDT 24 |
12232121662 ps |
| T839 |
/workspace/coverage/default/15.sram_ctrl_smoke.1670733154 |
|
|
Jun 29 06:54:36 PM PDT 24 |
Jun 29 06:54:38 PM PDT 24 |
125814761 ps |
| T840 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.2355755156 |
|
|
Jun 29 06:53:58 PM PDT 24 |
Jun 29 06:54:06 PM PDT 24 |
802132566 ps |
| T841 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1497678149 |
|
|
Jun 29 06:57:21 PM PDT 24 |
Jun 29 07:03:16 PM PDT 24 |
15601502685 ps |
| T842 |
/workspace/coverage/default/3.sram_ctrl_bijection.3184032423 |
|
|
Jun 29 06:53:56 PM PDT 24 |
Jun 29 06:55:02 PM PDT 24 |
4354151032 ps |
| T843 |
/workspace/coverage/default/22.sram_ctrl_executable.3021031243 |
|
|
Jun 29 06:54:59 PM PDT 24 |
Jun 29 06:58:15 PM PDT 24 |
3026121891 ps |
| T844 |
/workspace/coverage/default/31.sram_ctrl_alert_test.2193307710 |
|
|
Jun 29 06:55:48 PM PDT 24 |
Jun 29 06:55:49 PM PDT 24 |
31565242 ps |
| T845 |
/workspace/coverage/default/10.sram_ctrl_alert_test.1588711568 |
|
|
Jun 29 06:54:20 PM PDT 24 |
Jun 29 06:54:22 PM PDT 24 |
34992094 ps |
| T846 |
/workspace/coverage/default/19.sram_ctrl_stress_all.3893145302 |
|
|
Jun 29 06:54:44 PM PDT 24 |
Jun 29 07:45:14 PM PDT 24 |
87665243575 ps |
| T847 |
/workspace/coverage/default/36.sram_ctrl_stress_all.865505889 |
|
|
Jun 29 06:56:19 PM PDT 24 |
Jun 29 07:36:53 PM PDT 24 |
627848625750 ps |
| T28 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.3502748131 |
|
|
Jun 29 06:53:48 PM PDT 24 |
Jun 29 06:53:51 PM PDT 24 |
338736521 ps |
| T848 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.2789705716 |
|
|
Jun 29 06:54:39 PM PDT 24 |
Jun 29 06:54:46 PM PDT 24 |
1024247088 ps |
| T849 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.900702775 |
|
|
Jun 29 06:53:57 PM PDT 24 |
Jun 29 07:20:50 PM PDT 24 |
58601817461 ps |
| T850 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1716482007 |
|
|
Jun 29 06:57:14 PM PDT 24 |
Jun 29 06:57:18 PM PDT 24 |
118522242 ps |
| T851 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.285694384 |
|
|
Jun 29 06:54:28 PM PDT 24 |
Jun 29 06:54:29 PM PDT 24 |
48162550 ps |
| T852 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.688660295 |
|
|
Jun 29 06:53:51 PM PDT 24 |
Jun 29 06:54:59 PM PDT 24 |
134208001 ps |
| T853 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.1541063565 |
|
|
Jun 29 06:55:16 PM PDT 24 |
Jun 29 06:55:23 PM PDT 24 |
1011757042 ps |
| T854 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3981475992 |
|
|
Jun 29 06:55:11 PM PDT 24 |
Jun 29 06:55:59 PM PDT 24 |
554981716 ps |
| T855 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.3683059101 |
|
|
Jun 29 06:54:18 PM PDT 24 |
Jun 29 06:54:20 PM PDT 24 |
91470388 ps |
| T856 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.942530276 |
|
|
Jun 29 06:57:15 PM PDT 24 |
Jun 29 07:11:05 PM PDT 24 |
65414863758 ps |
| T857 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.3697232561 |
|
|
Jun 29 06:57:30 PM PDT 24 |
Jun 29 06:58:15 PM PDT 24 |
110756532 ps |
| T858 |
/workspace/coverage/default/22.sram_ctrl_regwen.4017834639 |
|
|
Jun 29 06:55:01 PM PDT 24 |
Jun 29 07:05:20 PM PDT 24 |
5040425190 ps |
| T859 |
/workspace/coverage/default/44.sram_ctrl_smoke.3383173247 |
|
|
Jun 29 06:57:02 PM PDT 24 |
Jun 29 06:57:11 PM PDT 24 |
68757023 ps |
| T860 |
/workspace/coverage/default/30.sram_ctrl_bijection.229421543 |
|
|
Jun 29 06:55:39 PM PDT 24 |
Jun 29 06:56:08 PM PDT 24 |
1719315443 ps |
| T861 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.3986806274 |
|
|
Jun 29 06:54:56 PM PDT 24 |
Jun 29 07:01:24 PM PDT 24 |
5070622260 ps |
| T862 |
/workspace/coverage/default/21.sram_ctrl_executable.577632870 |
|
|
Jun 29 06:54:55 PM PDT 24 |
Jun 29 07:19:55 PM PDT 24 |
79730699330 ps |
| T863 |
/workspace/coverage/default/17.sram_ctrl_alert_test.1176982763 |
|
|
Jun 29 06:54:42 PM PDT 24 |
Jun 29 06:54:43 PM PDT 24 |
34818632 ps |
| T864 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.3112522343 |
|
|
Jun 29 06:55:48 PM PDT 24 |
Jun 29 06:55:55 PM PDT 24 |
714793563 ps |
| T865 |
/workspace/coverage/default/44.sram_ctrl_stress_all.3790829301 |
|
|
Jun 29 06:57:02 PM PDT 24 |
Jun 29 09:03:51 PM PDT 24 |
417053124628 ps |
| T866 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.4285716432 |
|
|
Jun 29 06:56:17 PM PDT 24 |
Jun 29 07:13:02 PM PDT 24 |
3763285558 ps |
| T867 |
/workspace/coverage/default/48.sram_ctrl_partial_access.1695086634 |
|
|
Jun 29 06:57:21 PM PDT 24 |
Jun 29 06:57:40 PM PDT 24 |
5434260924 ps |
| T868 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2985728125 |
|
|
Jun 29 06:57:29 PM PDT 24 |
Jun 29 06:57:37 PM PDT 24 |
102194925 ps |
| T869 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.4261480172 |
|
|
Jun 29 06:57:23 PM PDT 24 |
Jun 29 06:57:30 PM PDT 24 |
1901369878 ps |
| T870 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.995109300 |
|
|
Jun 29 06:56:44 PM PDT 24 |
Jun 29 07:04:16 PM PDT 24 |
22131801006 ps |
| T871 |
/workspace/coverage/default/14.sram_ctrl_partial_access.448296411 |
|
|
Jun 29 06:54:37 PM PDT 24 |
Jun 29 06:55:18 PM PDT 24 |
3495313921 ps |
| T872 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.833432758 |
|
|
Jun 29 06:54:35 PM PDT 24 |
Jun 29 06:54:36 PM PDT 24 |
43423123 ps |
| T873 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.2359108394 |
|
|
Jun 29 06:54:44 PM PDT 24 |
Jun 29 06:54:48 PM PDT 24 |
537607256 ps |
| T874 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.2842932122 |
|
|
Jun 29 06:54:37 PM PDT 24 |
Jun 29 06:56:54 PM PDT 24 |
5230101864 ps |
| T875 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.1022904118 |
|
|
Jun 29 06:55:48 PM PDT 24 |
Jun 29 06:56:00 PM PDT 24 |
453848046 ps |
| T876 |
/workspace/coverage/default/22.sram_ctrl_alert_test.2080577668 |
|
|
Jun 29 06:55:02 PM PDT 24 |
Jun 29 06:55:03 PM PDT 24 |
21601231 ps |
| T877 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.1473041457 |
|
|
Jun 29 06:54:08 PM PDT 24 |
Jun 29 06:54:16 PM PDT 24 |
537205385 ps |
| T878 |
/workspace/coverage/default/42.sram_ctrl_partial_access.342535241 |
|
|
Jun 29 06:56:44 PM PDT 24 |
Jun 29 06:58:15 PM PDT 24 |
2381123737 ps |
| T879 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.1785104728 |
|
|
Jun 29 06:54:50 PM PDT 24 |
Jun 29 06:54:55 PM PDT 24 |
138062851 ps |
| T880 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.3470701150 |
|
|
Jun 29 06:56:52 PM PDT 24 |
Jun 29 06:57:01 PM PDT 24 |
548499296 ps |
| T881 |
/workspace/coverage/default/33.sram_ctrl_smoke.2496782852 |
|
|
Jun 29 06:55:57 PM PDT 24 |
Jun 29 06:56:07 PM PDT 24 |
157404936 ps |
| T882 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.3178437068 |
|
|
Jun 29 06:55:00 PM PDT 24 |
Jun 29 06:55:07 PM PDT 24 |
327346674 ps |
| T883 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.1785094709 |
|
|
Jun 29 06:55:24 PM PDT 24 |
Jun 29 07:00:15 PM PDT 24 |
12189851942 ps |
| T884 |
/workspace/coverage/default/20.sram_ctrl_executable.1506230516 |
|
|
Jun 29 06:54:57 PM PDT 24 |
Jun 29 07:10:34 PM PDT 24 |
9201327920 ps |
| T885 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.3251614694 |
|
|
Jun 29 06:57:37 PM PDT 24 |
Jun 29 06:57:48 PM PDT 24 |
1316469938 ps |
| T886 |
/workspace/coverage/default/15.sram_ctrl_bijection.2812690935 |
|
|
Jun 29 06:54:35 PM PDT 24 |
Jun 29 06:55:25 PM PDT 24 |
4442450606 ps |
| T887 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.2162231816 |
|
|
Jun 29 06:54:45 PM PDT 24 |
Jun 29 06:57:08 PM PDT 24 |
1937014667 ps |
| T888 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.4292212401 |
|
|
Jun 29 06:54:54 PM PDT 24 |
Jun 29 06:57:51 PM PDT 24 |
7147947420 ps |
| T889 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.3931825385 |
|
|
Jun 29 06:56:18 PM PDT 24 |
Jun 29 06:56:25 PM PDT 24 |
435554363 ps |
| T890 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.3678493090 |
|
|
Jun 29 06:54:04 PM PDT 24 |
Jun 29 06:54:10 PM PDT 24 |
163022249 ps |
| T891 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.649875644 |
|
|
Jun 29 06:56:34 PM PDT 24 |
Jun 29 07:43:50 PM PDT 24 |
8532271637 ps |
| T892 |
/workspace/coverage/default/4.sram_ctrl_bijection.3159084264 |
|
|
Jun 29 06:54:10 PM PDT 24 |
Jun 29 06:55:26 PM PDT 24 |
4589113864 ps |
| T893 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.3631423114 |
|
|
Jun 29 06:54:40 PM PDT 24 |
Jun 29 06:55:08 PM PDT 24 |
511614447 ps |
| T894 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.314549331 |
|
|
Jun 29 06:57:17 PM PDT 24 |
Jun 29 06:57:18 PM PDT 24 |
347455783 ps |
| T895 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.3536600422 |
|
|
Jun 29 06:55:31 PM PDT 24 |
Jun 29 06:55:32 PM PDT 24 |
30020683 ps |
| T896 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.860641054 |
|
|
Jun 29 06:54:03 PM PDT 24 |
Jun 29 07:00:23 PM PDT 24 |
56156119744 ps |
| T897 |
/workspace/coverage/default/37.sram_ctrl_partial_access.1510130228 |
|
|
Jun 29 06:56:18 PM PDT 24 |
Jun 29 06:56:31 PM PDT 24 |
1392495482 ps |
| T898 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.938199549 |
|
|
Jun 29 06:56:44 PM PDT 24 |
Jun 29 06:56:51 PM PDT 24 |
2217235844 ps |
| T899 |
/workspace/coverage/default/1.sram_ctrl_regwen.2848850462 |
|
|
Jun 29 06:53:49 PM PDT 24 |
Jun 29 07:11:30 PM PDT 24 |
36252048421 ps |
| T900 |
/workspace/coverage/default/24.sram_ctrl_partial_access.1869013217 |
|
|
Jun 29 06:55:07 PM PDT 24 |
Jun 29 06:55:19 PM PDT 24 |
1252818859 ps |
| T901 |
/workspace/coverage/default/28.sram_ctrl_smoke.1812893785 |
|
|
Jun 29 06:55:25 PM PDT 24 |
Jun 29 06:55:38 PM PDT 24 |
929137731 ps |
| T902 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.1007468833 |
|
|
Jun 29 06:54:29 PM PDT 24 |
Jun 29 06:54:30 PM PDT 24 |
27205964 ps |
| T903 |
/workspace/coverage/default/4.sram_ctrl_alert_test.42041938 |
|
|
Jun 29 06:54:03 PM PDT 24 |
Jun 29 06:54:04 PM PDT 24 |
41601020 ps |
| T904 |
/workspace/coverage/default/19.sram_ctrl_regwen.552572817 |
|
|
Jun 29 06:54:46 PM PDT 24 |
Jun 29 07:09:58 PM PDT 24 |
2096135093 ps |
| T905 |
/workspace/coverage/default/46.sram_ctrl_regwen.1049002679 |
|
|
Jun 29 06:57:23 PM PDT 24 |
Jun 29 07:10:14 PM PDT 24 |
8683572688 ps |
| T906 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.99848175 |
|
|
Jun 29 06:54:31 PM PDT 24 |
Jun 29 07:00:21 PM PDT 24 |
4630454385 ps |
| T907 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.2983538668 |
|
|
Jun 29 06:56:18 PM PDT 24 |
Jun 29 06:56:26 PM PDT 24 |
2091690589 ps |
| T908 |
/workspace/coverage/default/46.sram_ctrl_stress_all.3457760050 |
|
|
Jun 29 06:57:15 PM PDT 24 |
Jun 29 08:05:15 PM PDT 24 |
28839524622 ps |
| T909 |
/workspace/coverage/default/4.sram_ctrl_stress_all.1895396527 |
|
|
Jun 29 06:54:06 PM PDT 24 |
Jun 29 07:13:27 PM PDT 24 |
13012331966 ps |
| T910 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.1024394912 |
|
|
Jun 29 06:57:29 PM PDT 24 |
Jun 29 06:58:31 PM PDT 24 |
422691037 ps |
| T911 |
/workspace/coverage/default/26.sram_ctrl_regwen.969203539 |
|
|
Jun 29 06:55:17 PM PDT 24 |
Jun 29 07:31:42 PM PDT 24 |
20074600807 ps |
| T912 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.2251481999 |
|
|
Jun 29 06:53:58 PM PDT 24 |
Jun 29 06:54:00 PM PDT 24 |
76049374 ps |
| T913 |
/workspace/coverage/default/13.sram_ctrl_executable.1124466654 |
|
|
Jun 29 06:54:34 PM PDT 24 |
Jun 29 07:05:28 PM PDT 24 |
12243286055 ps |
| T914 |
/workspace/coverage/default/41.sram_ctrl_partial_access.2198913198 |
|
|
Jun 29 06:56:48 PM PDT 24 |
Jun 29 06:56:54 PM PDT 24 |
252804726 ps |
| T915 |
/workspace/coverage/default/8.sram_ctrl_alert_test.1322509938 |
|
|
Jun 29 06:54:13 PM PDT 24 |
Jun 29 06:54:14 PM PDT 24 |
13628158 ps |
| T916 |
/workspace/coverage/default/32.sram_ctrl_alert_test.3738423127 |
|
|
Jun 29 06:55:54 PM PDT 24 |
Jun 29 06:55:56 PM PDT 24 |
12966707 ps |
| T917 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2306719750 |
|
|
Jun 29 06:53:48 PM PDT 24 |
Jun 29 07:15:18 PM PDT 24 |
20704815349 ps |
| T918 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.3541109904 |
|
|
Jun 29 06:54:20 PM PDT 24 |
Jun 29 06:54:39 PM PDT 24 |
152253560 ps |
| T919 |
/workspace/coverage/default/16.sram_ctrl_stress_all.1044254996 |
|
|
Jun 29 06:54:39 PM PDT 24 |
Jun 29 07:23:25 PM PDT 24 |
22407830639 ps |
| T920 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.1562792817 |
|
|
Jun 29 06:55:28 PM PDT 24 |
Jun 29 07:01:23 PM PDT 24 |
4710522911 ps |
| T921 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.2330701874 |
|
|
Jun 29 06:55:18 PM PDT 24 |
Jun 29 07:07:49 PM PDT 24 |
11935518110 ps |
| T922 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2706479381 |
|
|
Jun 29 06:57:14 PM PDT 24 |
Jun 29 06:57:15 PM PDT 24 |
168706286 ps |
| T923 |
/workspace/coverage/default/4.sram_ctrl_regwen.388076257 |
|
|
Jun 29 06:54:07 PM PDT 24 |
Jun 29 07:21:50 PM PDT 24 |
4389457873 ps |
| T924 |
/workspace/coverage/default/8.sram_ctrl_stress_all.2210111315 |
|
|
Jun 29 06:54:13 PM PDT 24 |
Jun 29 07:56:49 PM PDT 24 |
192530138927 ps |
| T925 |
/workspace/coverage/default/34.sram_ctrl_regwen.4224861318 |
|
|
Jun 29 06:56:02 PM PDT 24 |
Jun 29 06:56:50 PM PDT 24 |
8087495792 ps |
| T926 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3373552632 |
|
|
Jun 29 06:54:38 PM PDT 24 |
Jun 29 07:01:05 PM PDT 24 |
21209807713 ps |
| T927 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.911911417 |
|
|
Jun 29 06:54:17 PM PDT 24 |
Jun 29 06:54:25 PM PDT 24 |
278162322 ps |
| T928 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.978953819 |
|
|
Jun 29 06:54:37 PM PDT 24 |
Jun 29 06:56:30 PM PDT 24 |
534019148 ps |
| T929 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.2487307816 |
|
|
Jun 29 06:54:49 PM PDT 24 |
Jun 29 06:54:57 PM PDT 24 |
569463599 ps |
| T930 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.4208571248 |
|
|
Jun 29 06:54:59 PM PDT 24 |
Jun 29 06:55:00 PM PDT 24 |
31431066 ps |
| T931 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.1425943313 |
|
|
Jun 29 06:56:45 PM PDT 24 |
Jun 29 06:56:52 PM PDT 24 |
689573345 ps |
| T932 |
/workspace/coverage/default/6.sram_ctrl_stress_all.901628524 |
|
|
Jun 29 06:54:09 PM PDT 24 |
Jun 29 07:21:40 PM PDT 24 |
37031846816 ps |
| T933 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.3411663875 |
|
|
Jun 29 06:54:37 PM PDT 24 |
Jun 29 06:57:40 PM PDT 24 |
3515747157 ps |
| T934 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.952429682 |
|
|
Jun 29 06:56:11 PM PDT 24 |
Jun 29 06:58:29 PM PDT 24 |
650381257 ps |
| T935 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.3183853378 |
|
|
Jun 29 06:57:01 PM PDT 24 |
Jun 29 06:57:02 PM PDT 24 |
49237203 ps |
| T936 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.3024021925 |
|
|
Jun 29 06:56:18 PM PDT 24 |
Jun 29 06:56:24 PM PDT 24 |
132214034 ps |
| T937 |
/workspace/coverage/default/6.sram_ctrl_partial_access.1371145785 |
|
|
Jun 29 06:54:07 PM PDT 24 |
Jun 29 06:54:22 PM PDT 24 |
693948840 ps |
| T938 |
/workspace/coverage/default/17.sram_ctrl_smoke.1825080795 |
|
|
Jun 29 06:54:35 PM PDT 24 |
Jun 29 06:57:15 PM PDT 24 |
1290735375 ps |
| T939 |
/workspace/coverage/default/29.sram_ctrl_stress_all.2182811842 |
|
|
Jun 29 06:55:33 PM PDT 24 |
Jun 29 08:00:43 PM PDT 24 |
22777844403 ps |
| T60 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2062005024 |
|
|
Jun 29 06:47:58 PM PDT 24 |
Jun 29 06:48:02 PM PDT 24 |
1461181095 ps |
| T61 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.365572770 |
|
|
Jun 29 06:47:51 PM PDT 24 |
Jun 29 06:47:53 PM PDT 24 |
1066178635 ps |
| T940 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3639363540 |
|
|
Jun 29 06:47:50 PM PDT 24 |
Jun 29 06:47:53 PM PDT 24 |
25974896 ps |
| T57 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2834786935 |
|
|
Jun 29 06:47:59 PM PDT 24 |
Jun 29 06:48:01 PM PDT 24 |
333992166 ps |
| T941 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.54108934 |
|
|
Jun 29 06:48:04 PM PDT 24 |
Jun 29 06:48:08 PM PDT 24 |
149307547 ps |
| T58 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2116815508 |
|
|
Jun 29 06:47:57 PM PDT 24 |
Jun 29 06:47:59 PM PDT 24 |
174276369 ps |
| T114 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.263353950 |
|
|
Jun 29 06:47:53 PM PDT 24 |
Jun 29 06:47:56 PM PDT 24 |
158305998 ps |
| T942 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1178885480 |
|
|
Jun 29 06:47:53 PM PDT 24 |
Jun 29 06:47:55 PM PDT 24 |
55238555 ps |
| T943 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1823244480 |
|
|
Jun 29 06:47:55 PM PDT 24 |
Jun 29 06:47:57 PM PDT 24 |
34563521 ps |
| T944 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3297757229 |
|
|
Jun 29 06:47:51 PM PDT 24 |
Jun 29 06:47:53 PM PDT 24 |
137044499 ps |
| T59 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2069955798 |
|
|
Jun 29 06:47:59 PM PDT 24 |
Jun 29 06:48:02 PM PDT 24 |
181270622 ps |
| T945 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1720430549 |
|
|
Jun 29 06:47:53 PM PDT 24 |
Jun 29 06:47:57 PM PDT 24 |
31486931 ps |
| T946 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2894786410 |
|
|
Jun 29 06:47:53 PM PDT 24 |
Jun 29 06:47:56 PM PDT 24 |
119164589 ps |
| T97 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4212921268 |
|
|
Jun 29 06:47:58 PM PDT 24 |
Jun 29 06:47:59 PM PDT 24 |
77844352 ps |
| T947 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2382534130 |
|
|
Jun 29 06:47:54 PM PDT 24 |
Jun 29 06:47:57 PM PDT 24 |
142116307 ps |
| T69 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2164600520 |
|
|
Jun 29 06:47:45 PM PDT 24 |
Jun 29 06:47:48 PM PDT 24 |
718889184 ps |
| T98 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3358798550 |
|
|
Jun 29 06:47:38 PM PDT 24 |
Jun 29 06:47:43 PM PDT 24 |
821818125 ps |
| T99 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3240191387 |
|
|
Jun 29 06:47:53 PM PDT 24 |
Jun 29 06:47:55 PM PDT 24 |
58662198 ps |
| T70 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4188968834 |
|
|
Jun 29 06:47:53 PM PDT 24 |
Jun 29 06:47:55 PM PDT 24 |
15052024 ps |
| T948 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.812563373 |
|
|
Jun 29 06:47:38 PM PDT 24 |
Jun 29 06:47:40 PM PDT 24 |
69431520 ps |
| T124 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2010819222 |
|
|
Jun 29 06:47:37 PM PDT 24 |
Jun 29 06:47:42 PM PDT 24 |
449326947 ps |
| T125 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2541057396 |
|
|
Jun 29 06:47:38 PM PDT 24 |
Jun 29 06:47:42 PM PDT 24 |
188660438 ps |
| T949 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1746338315 |
|
|
Jun 29 06:47:51 PM PDT 24 |
Jun 29 06:47:52 PM PDT 24 |
24593508 ps |
| T100 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2327528019 |
|
|
Jun 29 06:48:07 PM PDT 24 |
Jun 29 06:48:08 PM PDT 24 |
33463791 ps |
| T71 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.618600037 |
|
|
Jun 29 06:47:42 PM PDT 24 |
Jun 29 06:47:43 PM PDT 24 |
54927367 ps |
| T950 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4178686975 |
|
|
Jun 29 06:48:05 PM PDT 24 |
Jun 29 06:48:07 PM PDT 24 |
36187934 ps |
| T129 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1969417901 |
|
|
Jun 29 06:47:55 PM PDT 24 |
Jun 29 06:47:57 PM PDT 24 |
130184085 ps |
| T106 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3212330023 |
|
|
Jun 29 06:47:38 PM PDT 24 |
Jun 29 06:47:40 PM PDT 24 |
36483706 ps |
| T72 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4129893358 |
|
|
Jun 29 06:47:59 PM PDT 24 |
Jun 29 06:48:03 PM PDT 24 |
1946126069 ps |
| T951 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.4108416468 |
|
|
Jun 29 06:47:38 PM PDT 24 |
Jun 29 06:47:40 PM PDT 24 |
178467312 ps |
| T101 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.4177098207 |
|
|
Jun 29 06:47:48 PM PDT 24 |
Jun 29 06:47:50 PM PDT 24 |
208775494 ps |
| T138 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4239978627 |
|
|
Jun 29 06:47:46 PM PDT 24 |
Jun 29 06:47:48 PM PDT 24 |
159703048 ps |
| T73 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.626295742 |
|
|
Jun 29 06:47:46 PM PDT 24 |
Jun 29 06:47:47 PM PDT 24 |
35442443 ps |
| T74 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3223778553 |
|
|
Jun 29 06:47:39 PM PDT 24 |
Jun 29 06:47:42 PM PDT 24 |
21874296 ps |
| T75 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1939832302 |
|
|
Jun 29 06:47:54 PM PDT 24 |
Jun 29 06:47:56 PM PDT 24 |
15084577 ps |
| T130 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4259620235 |
|
|
Jun 29 06:47:44 PM PDT 24 |
Jun 29 06:47:46 PM PDT 24 |
727505173 ps |
| T952 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3826495440 |
|
|
Jun 29 06:47:53 PM PDT 24 |
Jun 29 06:47:57 PM PDT 24 |
72772800 ps |
| T953 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3933549440 |
|
|
Jun 29 06:48:04 PM PDT 24 |
Jun 29 06:48:07 PM PDT 24 |
47538772 ps |
| T76 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1132377778 |
|
|
Jun 29 06:47:54 PM PDT 24 |
Jun 29 06:47:58 PM PDT 24 |
451463454 ps |
| T79 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.264113247 |
|
|
Jun 29 06:47:39 PM PDT 24 |
Jun 29 06:47:42 PM PDT 24 |
18003867 ps |
| T136 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2411084930 |
|
|
Jun 29 06:47:47 PM PDT 24 |
Jun 29 06:47:50 PM PDT 24 |
503519376 ps |
| T80 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3811320762 |
|
|
Jun 29 06:47:45 PM PDT 24 |
Jun 29 06:47:47 PM PDT 24 |
14012968 ps |
| T81 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.4189731313 |
|
|
Jun 29 06:47:38 PM PDT 24 |
Jun 29 06:47:41 PM PDT 24 |
34949796 ps |
| T954 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3877419406 |
|
|
Jun 29 06:47:48 PM PDT 24 |
Jun 29 06:47:50 PM PDT 24 |
59123761 ps |
| T955 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.673476377 |
|
|
Jun 29 06:48:09 PM PDT 24 |
Jun 29 06:48:10 PM PDT 24 |
18169439 ps |
| T86 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.4218564932 |
|
|
Jun 29 06:47:45 PM PDT 24 |
Jun 29 06:47:49 PM PDT 24 |
1559974594 ps |
| T956 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2853168908 |
|
|
Jun 29 06:47:44 PM PDT 24 |
Jun 29 06:47:48 PM PDT 24 |
293918538 ps |
| T957 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1969002231 |
|
|
Jun 29 06:47:46 PM PDT 24 |
Jun 29 06:47:48 PM PDT 24 |
21968836 ps |
| T958 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1978329152 |
|
|
Jun 29 06:47:47 PM PDT 24 |
Jun 29 06:47:48 PM PDT 24 |
55337202 ps |
| T87 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3726415696 |
|
|
Jun 29 06:48:02 PM PDT 24 |
Jun 29 06:48:05 PM PDT 24 |
774970313 ps |
| T959 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3841981364 |
|
|
Jun 29 06:47:40 PM PDT 24 |
Jun 29 06:47:43 PM PDT 24 |
28236444 ps |
| T960 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.205753265 |
|
|
Jun 29 06:47:46 PM PDT 24 |
Jun 29 06:47:47 PM PDT 24 |
28847629 ps |
| T961 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.601343889 |
|
|
Jun 29 06:47:58 PM PDT 24 |
Jun 29 06:48:02 PM PDT 24 |
111064677 ps |
| T962 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3903378160 |
|
|
Jun 29 06:48:06 PM PDT 24 |
Jun 29 06:48:08 PM PDT 24 |
240205221 ps |
| T963 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.588410389 |
|
|
Jun 29 06:47:58 PM PDT 24 |
Jun 29 06:48:00 PM PDT 24 |
22333915 ps |
| T88 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2939245846 |
|
|
Jun 29 06:47:46 PM PDT 24 |
Jun 29 06:47:49 PM PDT 24 |
1007343764 ps |
| T964 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1363661085 |
|
|
Jun 29 06:47:40 PM PDT 24 |
Jun 29 06:47:43 PM PDT 24 |
353134966 ps |
| T137 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2865772181 |
|
|
Jun 29 06:47:58 PM PDT 24 |
Jun 29 06:48:01 PM PDT 24 |
572700779 ps |
| T965 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1199228203 |
|
|
Jun 29 06:47:38 PM PDT 24 |
Jun 29 06:47:41 PM PDT 24 |
37831091 ps |
| T966 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.922351413 |
|
|
Jun 29 06:48:03 PM PDT 24 |
Jun 29 06:48:04 PM PDT 24 |
78887695 ps |
| T967 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2866380691 |
|
|
Jun 29 06:47:42 PM PDT 24 |
Jun 29 06:47:43 PM PDT 24 |
43563152 ps |
| T968 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.737695089 |
|
|
Jun 29 06:47:59 PM PDT 24 |
Jun 29 06:48:00 PM PDT 24 |
33286875 ps |
| T969 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2893274546 |
|
|
Jun 29 06:47:53 PM PDT 24 |
Jun 29 06:47:55 PM PDT 24 |
13759358 ps |
| T89 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1225657204 |
|
|
Jun 29 06:47:39 PM PDT 24 |
Jun 29 06:47:44 PM PDT 24 |
1618090004 ps |
| T970 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.35303073 |
|
|
Jun 29 06:47:37 PM PDT 24 |
Jun 29 06:47:40 PM PDT 24 |
59763888 ps |
| T90 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1124044558 |
|
|
Jun 29 06:47:39 PM PDT 24 |
Jun 29 06:47:44 PM PDT 24 |
1600702328 ps |
| T971 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.851031110 |
|
|
Jun 29 06:47:57 PM PDT 24 |
Jun 29 06:47:59 PM PDT 24 |
164271057 ps |
| T972 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.783660049 |
|
|
Jun 29 06:47:39 PM PDT 24 |
Jun 29 06:47:41 PM PDT 24 |
14460995 ps |
| T973 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2554444308 |
|
|
Jun 29 06:47:49 PM PDT 24 |
Jun 29 06:47:50 PM PDT 24 |
45016277 ps |
| T974 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.672818131 |
|
|
Jun 29 06:47:40 PM PDT 24 |
Jun 29 06:47:42 PM PDT 24 |
20805033 ps |
| T91 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3990491551 |
|
|
Jun 29 06:47:39 PM PDT 24 |
Jun 29 06:47:43 PM PDT 24 |
251761017 ps |
| T975 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1331922112 |
|
|
Jun 29 06:47:45 PM PDT 24 |
Jun 29 06:47:46 PM PDT 24 |
38776609 ps |
| T976 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3140832713 |
|
|
Jun 29 06:47:55 PM PDT 24 |
Jun 29 06:47:57 PM PDT 24 |
93147800 ps |
| T977 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1193374682 |
|
|
Jun 29 06:47:59 PM PDT 24 |
Jun 29 06:48:01 PM PDT 24 |
148562401 ps |
| T978 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4165849533 |
|
|
Jun 29 06:48:06 PM PDT 24 |
Jun 29 06:48:10 PM PDT 24 |
441932527 ps |
| T979 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1220894059 |
|
|
Jun 29 06:47:58 PM PDT 24 |
Jun 29 06:48:00 PM PDT 24 |
122975701 ps |
| T980 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.355923344 |
|
|
Jun 29 06:48:01 PM PDT 24 |
Jun 29 06:48:02 PM PDT 24 |
39618890 ps |
| T92 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3680586099 |
|
|
Jun 29 06:47:57 PM PDT 24 |
Jun 29 06:47:58 PM PDT 24 |
28045650 ps |
| T981 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2560581341 |
|
|
Jun 29 06:48:09 PM PDT 24 |
Jun 29 06:48:10 PM PDT 24 |
40033238 ps |
| T982 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.317677268 |
|
|
Jun 29 06:47:45 PM PDT 24 |
Jun 29 06:47:46 PM PDT 24 |
102523770 ps |
| T93 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3761538738 |
|
|
Jun 29 06:47:55 PM PDT 24 |
Jun 29 06:47:58 PM PDT 24 |
1412752401 ps |
| T983 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2275881932 |
|
|
Jun 29 06:47:56 PM PDT 24 |
Jun 29 06:47:57 PM PDT 24 |
33111919 ps |
| T984 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3355826170 |
|
|
Jun 29 06:48:05 PM PDT 24 |
Jun 29 06:48:07 PM PDT 24 |
30626439 ps |
| T985 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.4190809164 |
|
|
Jun 29 06:47:40 PM PDT 24 |
Jun 29 06:47:43 PM PDT 24 |
16418180 ps |
| T986 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.386289808 |
|
|
Jun 29 06:47:59 PM PDT 24 |
Jun 29 06:48:01 PM PDT 24 |
65531110 ps |
| T987 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2207471530 |
|
|
Jun 29 06:47:49 PM PDT 24 |
Jun 29 06:47:50 PM PDT 24 |
66293560 ps |
| T988 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.618325946 |
|
|
Jun 29 06:47:38 PM PDT 24 |
Jun 29 06:47:41 PM PDT 24 |
44553508 ps |
| T127 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2996453657 |
|
|
Jun 29 06:47:39 PM PDT 24 |
Jun 29 06:47:42 PM PDT 24 |
96407905 ps |
| T989 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2150231028 |
|
|
Jun 29 06:47:56 PM PDT 24 |
Jun 29 06:47:57 PM PDT 24 |
135365565 ps |
| T990 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1494692587 |
|
|
Jun 29 06:48:01 PM PDT 24 |
Jun 29 06:48:03 PM PDT 24 |
245413667 ps |
| T991 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.964264399 |
|
|
Jun 29 06:47:48 PM PDT 24 |
Jun 29 06:47:49 PM PDT 24 |
16802122 ps |
| T992 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.231500881 |
|
|
Jun 29 06:48:04 PM PDT 24 |
Jun 29 06:48:07 PM PDT 24 |
153630600 ps |
| T993 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1064264692 |
|
|
Jun 29 06:47:39 PM PDT 24 |
Jun 29 06:47:43 PM PDT 24 |
78164686 ps |
| T131 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.44411554 |
|
|
Jun 29 06:47:50 PM PDT 24 |
Jun 29 06:47:53 PM PDT 24 |
479731251 ps |
| T994 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1380066782 |
|
|
Jun 29 06:47:39 PM PDT 24 |
Jun 29 06:47:43 PM PDT 24 |
55650417 ps |
| T995 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.831767022 |
|
|
Jun 29 06:48:00 PM PDT 24 |
Jun 29 06:48:04 PM PDT 24 |
6041246519 ps |
| T996 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1976219999 |
|
|
Jun 29 06:47:53 PM PDT 24 |
Jun 29 06:47:57 PM PDT 24 |
409834495 ps |
| T997 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2709725209 |
|
|
Jun 29 06:48:03 PM PDT 24 |
Jun 29 06:48:08 PM PDT 24 |
116574118 ps |
| T998 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2934281453 |
|
|
Jun 29 06:47:40 PM PDT 24 |
Jun 29 06:47:42 PM PDT 24 |
22091946 ps |
| T999 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3320126100 |
|
|
Jun 29 06:48:07 PM PDT 24 |
Jun 29 06:48:08 PM PDT 24 |
42058839 ps |
| T1000 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2137090052 |
|
|
Jun 29 06:47:45 PM PDT 24 |
Jun 29 06:47:47 PM PDT 24 |
33186643 ps |
| T1001 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2777533135 |
|
|
Jun 29 06:47:50 PM PDT 24 |
Jun 29 06:47:54 PM PDT 24 |
3829898792 ps |
| T1002 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2996426174 |
|
|
Jun 29 06:47:59 PM PDT 24 |
Jun 29 06:48:02 PM PDT 24 |
35943363 ps |
| T1003 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1250218261 |
|
|
Jun 29 06:47:58 PM PDT 24 |
Jun 29 06:48:00 PM PDT 24 |
127050726 ps |
| T134 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1533335673 |
|
|
Jun 29 06:48:07 PM PDT 24 |
Jun 29 06:48:10 PM PDT 24 |
321200585 ps |
| T128 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.638545297 |
|
|
Jun 29 06:47:59 PM PDT 24 |
Jun 29 06:48:02 PM PDT 24 |
915352592 ps |