Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Total test records in report: 1026

T1004	/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.18304854	Jun 29 06:48:04 PM PDT 24	Jun 29 06:48:05 PM PDT 24	142735710 ps
T1005	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3073774426	Jun 29 06:47:46 PM PDT 24	Jun 29 06:47:48 PM PDT 24	47454745 ps
T1006	/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3114143243	Jun 29 06:47:48 PM PDT 24	Jun 29 06:47:50 PM PDT 24	24882140 ps
T135	/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3564635106	Jun 29 06:47:39 PM PDT 24	Jun 29 06:47:44 PM PDT 24	478233273 ps
T1007	/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2445787622	Jun 29 06:48:01 PM PDT 24	Jun 29 06:48:02 PM PDT 24	50626854 ps
T1008	/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.857967076	Jun 29 06:48:02 PM PDT 24	Jun 29 06:48:05 PM PDT 24	357900373 ps
T1009	/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2857666635	Jun 29 06:47:58 PM PDT 24	Jun 29 06:47:59 PM PDT 24	34792198 ps
T1010	/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.848077527	Jun 29 06:48:05 PM PDT 24	Jun 29 06:48:06 PM PDT 24	22093128 ps
T1011	/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1710751434	Jun 29 06:47:46 PM PDT 24	Jun 29 06:47:48 PM PDT 24	16648949 ps
T1012	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2577043021	Jun 29 06:47:44 PM PDT 24	Jun 29 06:47:45 PM PDT 24	79019510 ps
T132	/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3724184887	Jun 29 06:48:03 PM PDT 24	Jun 29 06:48:06 PM PDT 24	430067024 ps
T1013	/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3942926392	Jun 29 06:47:58 PM PDT 24	Jun 29 06:48:00 PM PDT 24	19208528 ps
T1014	/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3242124972	Jun 29 06:47:47 PM PDT 24	Jun 29 06:47:50 PM PDT 24	89119509 ps
T1015	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3689814593	Jun 29 06:47:42 PM PDT 24	Jun 29 06:47:43 PM PDT 24	12397018 ps
T133	/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1299221378	Jun 29 06:47:53 PM PDT 24	Jun 29 06:47:56 PM PDT 24	493318177 ps
T1016	/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1177348780	Jun 29 06:47:53 PM PDT 24	Jun 29 06:47:54 PM PDT 24	17696202 ps
T1017	/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1045816066	Jun 29 06:47:50 PM PDT 24	Jun 29 06:47:54 PM PDT 24	128588504 ps
T1018	/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1597000463	Jun 29 06:47:58 PM PDT 24	Jun 29 06:48:03 PM PDT 24	220061755 ps
T1019	/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.741590102	Jun 29 06:47:45 PM PDT 24	Jun 29 06:47:48 PM PDT 24	783235604 ps
T1020	/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2438485929	Jun 29 06:48:07 PM PDT 24	Jun 29 06:48:10 PM PDT 24	65070663 ps
T1021	/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3114636268	Jun 29 06:47:51 PM PDT 24	Jun 29 06:47:54 PM PDT 24	427471974 ps
T1022	/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.287045939	Jun 29 06:48:03 PM PDT 24	Jun 29 06:48:04 PM PDT 24	42773832 ps
T1023	/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1705770161	Jun 29 06:47:55 PM PDT 24	Jun 29 06:47:58 PM PDT 24	217004838 ps
T1024	/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.764335857	Jun 29 06:47:53 PM PDT 24	Jun 29 06:47:58 PM PDT 24	91717406 ps
T1025	/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3902691672	Jun 29 06:47:58 PM PDT 24	Jun 29 06:47:59 PM PDT 24	38190485 ps
T1026	/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1581269223	Jun 29 06:48:02 PM PDT 24	Jun 29 06:48:04 PM PDT 24	104286751 ps

Test location	/workspace/coverage/default/10.sram_ctrl_stress_all.546993413
Short name	T6
Test name
Test status
Simulation time	12748289475 ps
CPU time	5152.27 seconds
Started	Jun 29 06:54:19 PM PDT 24
Finished	Jun 29 08:20:13 PM PDT 24
Peak memory	382972 kb
Host	smart-2b38725b-a93e-4d6a-b136-e4eb253ae08c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546993413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.sram_ctrl_stress_all.546993413
Directory	/workspace/10.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.4158077964
Short name	T22
Test name
Test status
Simulation time	2077499281 ps
CPU time	15.18 seconds
Started	Jun 29 06:54:06 PM PDT 24
Finished	Jun 29 06:54:22 PM PDT 24
Peak memory	211108 kb
Host	smart-dd74066b-f42d-408e-b92e-d9ea82f9984d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4158077964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.4158077964
Directory	/workspace/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.sram_ctrl_regwen.1793628881
Short name	T19
Test name
Test status
Simulation time	55156740863 ps
CPU time	1239.58 seconds
Started	Jun 29 06:55:01 PM PDT 24
Finished	Jun 29 07:15:41 PM PDT 24
Peak memory	374740 kb
Host	smart-de878c22-5516-4052-8339-42d72cfaa467
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793628881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.1793628881
Directory	/workspace/23.sram_ctrl_regwen/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2069955798
Short name	T59
Test name
Test status
Simulation time	181270622 ps
CPU time	2.37 seconds
Started	Jun 29 06:47:59 PM PDT 24
Finished	Jun 29 06:48:02 PM PDT 24
Peak memory	210340 kb
Host	smart-665e1bcb-7740-4a87-bf92-4c7f75b7159b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069955798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 17.sram_ctrl_tl_intg_err.2069955798
Directory	/workspace/17.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.sram_ctrl_sec_cm.3502748131
Short name	T28
Test name
Test status
Simulation time	338736521 ps
CPU time	1.84 seconds
Started	Jun 29 06:53:48 PM PDT 24
Finished	Jun 29 06:53:51 PM PDT 24
Peak memory	221760 kb
Host	smart-e037bb55-83c1-4ac7-bda0-fd9108bec121
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502748131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.3502748131
Directory	/workspace/0.sram_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/20.sram_ctrl_alert_test.1094048884
Short name	T12
Test name
Test status
Simulation time	120589079 ps
CPU time	0.68 seconds
Started	Jun 29 06:55:00 PM PDT 24
Finished	Jun 29 06:55:01 PM PDT 24
Peak memory	202648 kb
Host	smart-7faca014-2426-489f-b8a8-25de14c3d972
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094048884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.1094048884
Directory	/workspace/20.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.2604385251
Short name	T94
Test name
Test status
Simulation time	17792562930 ps
CPU time	223.27 seconds
Started	Jun 29 06:54:08 PM PDT 24
Finished	Jun 29 06:57:51 PM PDT 24
Peak memory	202908 kb
Host	smart-d15890c9-95a8-4600-97df-3923aeb9b07c
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604385251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_partial_access_b2b.2604385251
Directory	/workspace/2.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.365572770
Short name	T61
Test name
Test status
Simulation time	1066178635 ps
CPU time	1.87 seconds
Started	Jun 29 06:47:51 PM PDT 24
Finished	Jun 29 06:47:53 PM PDT 24
Peak memory	202068 kb
Host	smart-58d5beef-7fab-4f67-9d6a-ec6c59e78772
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365572770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.365572770
Directory	/workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/default/32.sram_ctrl_access_during_key_req.3049289504
Short name	T4
Test name
Test status
Simulation time	4038509104 ps
CPU time	1342.37 seconds
Started	Jun 29 06:55:45 PM PDT 24
Finished	Jun 29 07:18:07 PM PDT 24
Peak memory	374376 kb
Host	smart-352243c6-80bf-47d8-b694-2804dc6f0b01
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049289504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 32.sram_ctrl_access_during_key_req.3049289504
Directory	/workspace/32.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3730606094
Short name	T110
Test name
Test status
Simulation time	1709110604 ps
CPU time	45.99 seconds
Started	Jun 29 06:54:38 PM PDT 24
Finished	Jun 29 06:55:25 PM PDT 24
Peak memory	211244 kb
Host	smart-bf2ed252-c9a2-43f1-b85e-3b8490430b39
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3730606094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.3730606094
Directory	/workspace/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.sram_ctrl_ram_cfg.1668688754
Short name	T204
Test name
Test status
Simulation time	74668852 ps
CPU time	0.75 seconds
Started	Jun 29 06:54:28 PM PDT 24
Finished	Jun 29 06:54:30 PM PDT 24
Peak memory	202880 kb
Host	smart-8ace8a35-97cc-4600-bc09-caf82e0bb0bf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668688754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.1668688754
Directory	/workspace/12.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/24.sram_ctrl_lc_escalation.1945133230
Short name	T8
Test name
Test status
Simulation time	2988991491 ps
CPU time	8.59 seconds
Started	Jun 29 06:55:09 PM PDT 24
Finished	Jun 29 06:55:18 PM PDT 24
Peak memory	202912 kb
Host	smart-29240df5-1bf2-4407-baea-c293ff204379
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945133230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es calation.1945133230
Directory	/workspace/24.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2541057396
Short name	T125
Test name
Test status
Simulation time	188660438 ps
CPU time	2.34 seconds
Started	Jun 29 06:47:38 PM PDT 24
Finished	Jun 29 06:47:42 PM PDT 24
Peak memory	210436 kb
Host	smart-68ed8214-f059-49ce-8399-00e97e9e4442
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541057396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.sram_ctrl_tl_intg_err.2541057396
Directory	/workspace/2.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3564635106
Short name	T135
Test name
Test status
Simulation time	478233273 ps
CPU time	2.79 seconds
Started	Jun 29 06:47:39 PM PDT 24
Finished	Jun 29 06:47:44 PM PDT 24
Peak memory	212592 kb
Host	smart-dec52397-5468-4f3f-af0f-a6d6aff8da7d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564635106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.sram_ctrl_tl_intg_err.3564635106
Directory	/workspace/1.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2670209303
Short name	T23
Test name
Test status
Simulation time	1189897963 ps
CPU time	293.72 seconds
Started	Jun 29 06:54:12 PM PDT 24
Finished	Jun 29 06:59:06 PM PDT 24
Peak memory	375644 kb
Host	smart-76d33d70-a306-4e5b-bc95-5fe7813bd210
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2670209303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.2670209303
Directory	/workspace/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2996453657
Short name	T127
Test name
Test status
Simulation time	96407905 ps
CPU time	1.49 seconds
Started	Jun 29 06:47:39 PM PDT 24
Finished	Jun 29 06:47:42 PM PDT 24
Peak memory	202220 kb
Host	smart-ac6568e5-28f0-44b8-a44a-6207f1049ccb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996453657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.sram_ctrl_tl_intg_err.2996453657
Directory	/workspace/0.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3724184887
Short name	T132
Test name
Test status
Simulation time	430067024 ps
CPU time	2.17 seconds
Started	Jun 29 06:48:03 PM PDT 24
Finished	Jun 29 06:48:06 PM PDT 24
Peak memory	210400 kb
Host	smart-1deae783-378b-4fe6-8ee9-8e6dd09c7bd9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724184887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 16.sram_ctrl_tl_intg_err.3724184887
Directory	/workspace/16.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3223778553
Short name	T74
Test name
Test status
Simulation time	21874296 ps
CPU time	0.74 seconds
Started	Jun 29 06:47:39 PM PDT 24
Finished	Jun 29 06:47:42 PM PDT 24
Peak memory	201920 kb
Host	smart-6f81f0b8-0f55-4e95-81b7-6617a0449a5d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223778553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_aliasing.3223778553
Directory	/workspace/0.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.812563373
Short name	T948
Test name
Test status
Simulation time	69431520 ps
CPU time	1.4 seconds
Started	Jun 29 06:47:38 PM PDT 24
Finished	Jun 29 06:47:40 PM PDT 24
Peak memory	202100 kb
Host	smart-ad40d5e3-136b-4a31-832c-04cc4fd91ebd
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812563373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bit_bash.812563373
Directory	/workspace/0.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3212330023
Short name	T106
Test name
Test status
Simulation time	36483706 ps
CPU time	0.72 seconds
Started	Jun 29 06:47:38 PM PDT 24
Finished	Jun 29 06:47:40 PM PDT 24
Peak memory	201920 kb
Host	smart-aeb87a02-d16c-49bc-a7ba-11b21e5ba3c0
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212330023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_hw_reset.3212330023
Directory	/workspace/0.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.4108416468
Short name	T951
Test name
Test status
Simulation time	178467312 ps
CPU time	0.88 seconds
Started	Jun 29 06:47:38 PM PDT 24
Finished	Jun 29 06:47:40 PM PDT 24
Peak memory	202088 kb
Host	smart-78bf93ea-4751-401f-8c3f-9adb6654cd54
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108416468 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.4108416468
Directory	/workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2934281453
Short name	T998
Test name
Test status
Simulation time	22091946 ps
CPU time	0.65 seconds
Started	Jun 29 06:47:40 PM PDT 24
Finished	Jun 29 06:47:42 PM PDT 24
Peak memory	201436 kb
Host	smart-a6343c0e-8a11-4e87-9061-175187795a14
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934281453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_csr_rw.2934281453
Directory	/workspace/0.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3358798550
Short name	T98
Test name
Test status
Simulation time	821818125 ps
CPU time	3.18 seconds
Started	Jun 29 06:47:38 PM PDT 24
Finished	Jun 29 06:47:43 PM PDT 24
Peak memory	202344 kb
Host	smart-6cc77fe1-4951-4b17-a604-ed7c2a4b944a
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358798550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.3358798550
Directory	/workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.618600037
Short name	T71
Test name
Test status
Simulation time	54927367 ps
CPU time	0.71 seconds
Started	Jun 29 06:47:42 PM PDT 24
Finished	Jun 29 06:47:43 PM PDT 24
Peak memory	201732 kb
Host	smart-7f6dc34c-8281-452a-b4d4-6fe11a5adda9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618600037 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.618600037
Directory	/workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1064264692
Short name	T993
Test name
Test status
Simulation time	78164686 ps
CPU time	2.58 seconds
Started	Jun 29 06:47:39 PM PDT 24
Finished	Jun 29 06:47:43 PM PDT 24
Peak memory	210456 kb
Host	smart-b07f2ead-3ab7-41f3-9b28-655f25f38663
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064264692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 0.sram_ctrl_tl_errors.1064264692
Directory	/workspace/0.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.264113247
Short name	T79
Test name
Test status
Simulation time	18003867 ps
CPU time	0.73 seconds
Started	Jun 29 06:47:39 PM PDT 24
Finished	Jun 29 06:47:42 PM PDT 24
Peak memory	201924 kb
Host	smart-051c7732-f202-4824-bf4d-8bb53522e918
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264113247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_aliasing.264113247
Directory	/workspace/1.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1363661085
Short name	T964
Test name
Test status
Simulation time	353134966 ps
CPU time	1.34 seconds
Started	Jun 29 06:47:40 PM PDT 24
Finished	Jun 29 06:47:43 PM PDT 24
Peak memory	202040 kb
Host	smart-e4070729-ce29-4b34-b7ee-8c6f84eb413c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363661085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_bit_bash.1363661085
Directory	/workspace/1.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1199228203
Short name	T965
Test name
Test status
Simulation time	37831091 ps
CPU time	0.67 seconds
Started	Jun 29 06:47:38 PM PDT 24
Finished	Jun 29 06:47:41 PM PDT 24
Peak memory	201864 kb
Host	smart-7c9a5b27-bfa2-4273-8db0-a23940f4909e
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199228203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_hw_reset.1199228203
Directory	/workspace/1.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3841981364
Short name	T959
Test name
Test status
Simulation time	28236444 ps
CPU time	1.08 seconds
Started	Jun 29 06:47:40 PM PDT 24
Finished	Jun 29 06:47:43 PM PDT 24
Peak memory	210272 kb
Host	smart-81a30f7f-1bcb-4019-adb0-6b3744449434
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841981364 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.3841981364
Directory	/workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3689814593
Short name	T1015
Test name
Test status
Simulation time	12397018 ps
CPU time	0.74 seconds
Started	Jun 29 06:47:42 PM PDT 24
Finished	Jun 29 06:47:43 PM PDT 24
Peak memory	201936 kb
Host	smart-f9ac0830-bd3a-4593-ae41-17a376e05d14
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689814593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_csr_rw.3689814593
Directory	/workspace/1.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3990491551
Short name	T91
Test name
Test status
Simulation time	251761017 ps
CPU time	1.99 seconds
Started	Jun 29 06:47:39 PM PDT 24
Finished	Jun 29 06:47:43 PM PDT 24
Peak memory	202060 kb
Host	smart-2f353f99-b7cd-4a3b-a2c4-bb5a9a448d93
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990491551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.3990491551
Directory	/workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.783660049
Short name	T972
Test name
Test status
Simulation time	14460995 ps
CPU time	0.71 seconds
Started	Jun 29 06:47:39 PM PDT 24
Finished	Jun 29 06:47:41 PM PDT 24
Peak memory	201996 kb
Host	smart-9e613b85-69bb-478a-b4b3-9755cd6ec560
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783660049 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.783660049
Directory	/workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1380066782
Short name	T994
Test name
Test status
Simulation time	55650417 ps
CPU time	2.15 seconds
Started	Jun 29 06:47:39 PM PDT 24
Finished	Jun 29 06:47:43 PM PDT 24
Peak memory	202200 kb
Host	smart-65c4d0c8-b4a3-47c4-80e5-585d4cf7216f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380066782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 1.sram_ctrl_tl_errors.1380066782
Directory	/workspace/1.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3140832713
Short name	T976
Test name
Test status
Simulation time	93147800 ps
CPU time	1.14 seconds
Started	Jun 29 06:47:55 PM PDT 24
Finished	Jun 29 06:47:57 PM PDT 24
Peak memory	211304 kb
Host	smart-518e6558-123c-49aa-bf4c-0d19ca9562aa
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140832713 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.3140832713
Directory	/workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1746338315
Short name	T949
Test name
Test status
Simulation time	24593508 ps
CPU time	0.67 seconds
Started	Jun 29 06:47:51 PM PDT 24
Finished	Jun 29 06:47:52 PM PDT 24
Peak memory	201920 kb
Host	smart-8ffe14ab-03d6-4b3c-90f3-ffcf63be60d3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746338315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_csr_rw.1746338315
Directory	/workspace/10.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2893274546
Short name	T969
Test name
Test status
Simulation time	13759358 ps
CPU time	0.69 seconds
Started	Jun 29 06:47:53 PM PDT 24
Finished	Jun 29 06:47:55 PM PDT 24
Peak memory	202024 kb
Host	smart-f8ed6cb2-280b-4b06-8196-9bd213b95ae1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893274546 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.2893274546
Directory	/workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2894786410
Short name	T946
Test name
Test status
Simulation time	119164589 ps
CPU time	2.77 seconds
Started	Jun 29 06:47:53 PM PDT 24
Finished	Jun 29 06:47:56 PM PDT 24
Peak memory	202276 kb
Host	smart-1203e79d-daa1-4105-997e-afcfa5244cf7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894786410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 10.sram_ctrl_tl_errors.2894786410
Directory	/workspace/10.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1299221378
Short name	T133
Test name
Test status
Simulation time	493318177 ps
CPU time	2.21 seconds
Started	Jun 29 06:47:53 PM PDT 24
Finished	Jun 29 06:47:56 PM PDT 24
Peak memory	210556 kb
Host	smart-750ac341-9853-496f-b2fe-5678d72563a0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299221378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 10.sram_ctrl_tl_intg_err.1299221378
Directory	/workspace/10.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1178885480
Short name	T942
Test name
Test status
Simulation time	55238555 ps
CPU time	1.26 seconds
Started	Jun 29 06:47:53 PM PDT 24
Finished	Jun 29 06:47:55 PM PDT 24
Peak memory	210280 kb
Host	smart-83e9b849-c34b-44aa-a78f-a6c18004f522
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178885480 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.1178885480
Directory	/workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4188968834
Short name	T70
Test name
Test status
Simulation time	15052024 ps
CPU time	0.65 seconds
Started	Jun 29 06:47:53 PM PDT 24
Finished	Jun 29 06:47:55 PM PDT 24
Peak memory	201924 kb
Host	smart-32f27e9c-ddb6-4bf9-98ce-354db219a050
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188968834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_csr_rw.4188968834
Directory	/workspace/11.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1132377778
Short name	T76
Test name
Test status
Simulation time	451463454 ps
CPU time	3.25 seconds
Started	Jun 29 06:47:54 PM PDT 24
Finished	Jun 29 06:47:58 PM PDT 24
Peak memory	202268 kb
Host	smart-2b4c2e73-ef97-426a-989e-121c3cbaec3a
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132377778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.1132377778
Directory	/workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2275881932
Short name	T983
Test name
Test status
Simulation time	33111919 ps
CPU time	0.74 seconds
Started	Jun 29 06:47:56 PM PDT 24
Finished	Jun 29 06:47:57 PM PDT 24
Peak memory	201980 kb
Host	smart-f74d5264-6705-4955-a91e-1b09fe504f80
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275881932 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.2275881932
Directory	/workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.764335857
Short name	T1024
Test name
Test status
Simulation time	91717406 ps
CPU time	4.03 seconds
Started	Jun 29 06:47:53 PM PDT 24
Finished	Jun 29 06:47:58 PM PDT 24
Peak memory	210372 kb
Host	smart-93091786-4af3-4666-ad59-40b63b731963
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764335857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.764335857
Directory	/workspace/11.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1969417901
Short name	T129
Test name
Test status
Simulation time	130184085 ps
CPU time	1.38 seconds
Started	Jun 29 06:47:55 PM PDT 24
Finished	Jun 29 06:47:57 PM PDT 24
Peak memory	202168 kb
Host	smart-66c131ef-a184-4ee7-8b98-4ceff3603a95
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969417901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 11.sram_ctrl_tl_intg_err.1969417901
Directory	/workspace/11.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4178686975
Short name	T950
Test name
Test status
Simulation time	36187934 ps
CPU time	2.1 seconds
Started	Jun 29 06:48:05 PM PDT 24
Finished	Jun 29 06:48:07 PM PDT 24
Peak memory	211324 kb
Host	smart-bfefd2df-d20b-4864-96fb-323859f44f6d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178686975 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.4178686975
Directory	/workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1939832302
Short name	T75
Test name
Test status
Simulation time	15084577 ps
CPU time	0.67 seconds
Started	Jun 29 06:47:54 PM PDT 24
Finished	Jun 29 06:47:56 PM PDT 24
Peak memory	201432 kb
Host	smart-b90ec59d-7112-4f9a-9b3a-d1e9a0ca5cbf
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939832302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_csr_rw.1939832302
Directory	/workspace/12.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2777533135
Short name	T1001
Test name
Test status
Simulation time	3829898792 ps
CPU time	2.43 seconds
Started	Jun 29 06:47:50 PM PDT 24
Finished	Jun 29 06:47:54 PM PDT 24
Peak memory	202196 kb
Host	smart-73dae797-18cd-4d88-96bf-bcc7ef487883
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777533135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.2777533135
Directory	/workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.848077527
Short name	T1010
Test name
Test status
Simulation time	22093128 ps
CPU time	0.8 seconds
Started	Jun 29 06:48:05 PM PDT 24
Finished	Jun 29 06:48:06 PM PDT 24
Peak memory	201824 kb
Host	smart-5c584c9e-ccb6-47d6-a782-1baf2d06a781
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848077527 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.848077527
Directory	/workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.601343889
Short name	T961
Test name
Test status
Simulation time	111064677 ps
CPU time	3.62 seconds
Started	Jun 29 06:47:58 PM PDT 24
Finished	Jun 29 06:48:02 PM PDT 24
Peak memory	202100 kb
Host	smart-4ecf289a-1f99-4df9-ac04-fb2b7bb44b93
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601343889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.601343889
Directory	/workspace/12.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1705770161
Short name	T1023
Test name
Test status
Simulation time	217004838 ps
CPU time	2.27 seconds
Started	Jun 29 06:47:55 PM PDT 24
Finished	Jun 29 06:47:58 PM PDT 24
Peak memory	210368 kb
Host	smart-d8fc7144-1f59-4fd3-b965-c3a0001f6457
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705770161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 12.sram_ctrl_tl_intg_err.1705770161
Directory	/workspace/12.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.386289808
Short name	T986
Test name
Test status
Simulation time	65531110 ps
CPU time	1.29 seconds
Started	Jun 29 06:47:59 PM PDT 24
Finished	Jun 29 06:48:01 PM PDT 24
Peak memory	210244 kb
Host	smart-0089db0e-52cf-4a32-a4c0-f472259bbde5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386289808 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.386289808
Directory	/workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2445787622
Short name	T1007
Test name
Test status
Simulation time	50626854 ps
CPU time	0.67 seconds
Started	Jun 29 06:48:01 PM PDT 24
Finished	Jun 29 06:48:02 PM PDT 24
Peak memory	201864 kb
Host	smart-252c1616-5af3-4019-a267-aaace37f743c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445787622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_csr_rw.2445787622
Directory	/workspace/13.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4129893358
Short name	T72
Test name
Test status
Simulation time	1946126069 ps
CPU time	3.53 seconds
Started	Jun 29 06:47:59 PM PDT 24
Finished	Jun 29 06:48:03 PM PDT 24
Peak memory	202288 kb
Host	smart-b3f26e58-00b3-4abe-8263-a7a85a4d7b3b
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129893358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.4129893358
Directory	/workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3942926392
Short name	T1013
Test name
Test status
Simulation time	19208528 ps
CPU time	0.75 seconds
Started	Jun 29 06:47:58 PM PDT 24
Finished	Jun 29 06:48:00 PM PDT 24
Peak memory	201996 kb
Host	smart-f7e6af65-0615-4f51-8bb0-790a643f60cf
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942926392 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.3942926392
Directory	/workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1597000463
Short name	T1018
Test name
Test status
Simulation time	220061755 ps
CPU time	4.03 seconds
Started	Jun 29 06:47:58 PM PDT 24
Finished	Jun 29 06:48:03 PM PDT 24
Peak memory	202232 kb
Host	smart-4614aad0-081b-489d-8b60-384f0d72cd8d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597000463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 13.sram_ctrl_tl_errors.1597000463
Directory	/workspace/13.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2834786935
Short name	T57
Test name
Test status
Simulation time	333992166 ps
CPU time	1.56 seconds
Started	Jun 29 06:47:59 PM PDT 24
Finished	Jun 29 06:48:01 PM PDT 24
Peak memory	202176 kb
Host	smart-5f5bcd42-bd5e-4734-9a6d-7ffa89ed87e2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834786935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 13.sram_ctrl_tl_intg_err.2834786935
Directory	/workspace/13.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1193374682
Short name	T977
Test name
Test status
Simulation time	148562401 ps
CPU time	1.3 seconds
Started	Jun 29 06:47:59 PM PDT 24
Finished	Jun 29 06:48:01 PM PDT 24
Peak memory	210288 kb
Host	smart-8618a0a8-46a6-4258-bee9-d7a384d9abc1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193374682 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.1193374682
Directory	/workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.588410389
Short name	T963
Test name
Test status
Simulation time	22333915 ps
CPU time	0.7 seconds
Started	Jun 29 06:47:58 PM PDT 24
Finished	Jun 29 06:48:00 PM PDT 24
Peak memory	201920 kb
Host	smart-30caad29-f489-4441-87f7-9daf0ea2f88f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588410389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 14.sram_ctrl_csr_rw.588410389
Directory	/workspace/14.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3726415696
Short name	T87
Test name
Test status
Simulation time	774970313 ps
CPU time	2.12 seconds
Started	Jun 29 06:48:02 PM PDT 24
Finished	Jun 29 06:48:05 PM PDT 24
Peak memory	202104 kb
Host	smart-76cbbf04-aa8a-4143-923e-981c16525389
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726415696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.3726415696
Directory	/workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.18304854
Short name	T1004
Test name
Test status
Simulation time	142735710 ps
CPU time	0.77 seconds
Started	Jun 29 06:48:04 PM PDT 24
Finished	Jun 29 06:48:05 PM PDT 24
Peak memory	201956 kb
Host	smart-29f6a833-849f-4297-b4ad-14b824b51b54
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18304854 -assert nopostproc +UVM_TESTNAME=sram_ctr l_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.18304854
Directory	/workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.54108934
Short name	T941
Test name
Test status
Simulation time	149307547 ps
CPU time	4.14 seconds
Started	Jun 29 06:48:04 PM PDT 24
Finished	Jun 29 06:48:08 PM PDT 24
Peak memory	202148 kb
Host	smart-fda53c05-0b5e-468a-95fd-9f1de1fa7920
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54108934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST _SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_errors.54108934
Directory	/workspace/14.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.638545297
Short name	T128
Test name
Test status
Simulation time	915352592 ps
CPU time	2.32 seconds
Started	Jun 29 06:47:59 PM PDT 24
Finished	Jun 29 06:48:02 PM PDT 24
Peak memory	210372 kb
Host	smart-d04f9f23-190f-4a13-93db-153faf7294e6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638545297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 14.sram_ctrl_tl_intg_err.638545297
Directory	/workspace/14.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1581269223
Short name	T1026
Test name
Test status
Simulation time	104286751 ps
CPU time	1.62 seconds
Started	Jun 29 06:48:02 PM PDT 24
Finished	Jun 29 06:48:04 PM PDT 24
Peak memory	210492 kb
Host	smart-83cb5527-173f-413c-b0a5-c0013ebd952b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581269223 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.1581269223
Directory	/workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.355923344
Short name	T980
Test name
Test status
Simulation time	39618890 ps
CPU time	0.64 seconds
Started	Jun 29 06:48:01 PM PDT 24
Finished	Jun 29 06:48:02 PM PDT 24
Peak memory	201328 kb
Host	smart-a3b292e7-6a39-4909-b477-a7e217181551
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355923344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 15.sram_ctrl_csr_rw.355923344
Directory	/workspace/15.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.831767022
Short name	T995
Test name
Test status
Simulation time	6041246519 ps
CPU time	3.15 seconds
Started	Jun 29 06:48:00 PM PDT 24
Finished	Jun 29 06:48:04 PM PDT 24
Peak memory	202352 kb
Host	smart-a3f4bc8b-eda5-43dc-b304-3e5085a5ef33
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831767022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.831767022
Directory	/workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2857666635
Short name	T1009
Test name
Test status
Simulation time	34792198 ps
CPU time	0.76 seconds
Started	Jun 29 06:47:58 PM PDT 24
Finished	Jun 29 06:47:59 PM PDT 24
Peak memory	201968 kb
Host	smart-b8c6effc-4815-4159-865d-c0cc575693f7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857666635 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.2857666635
Directory	/workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1250218261
Short name	T1003
Test name
Test status
Simulation time	127050726 ps
CPU time	2.27 seconds
Started	Jun 29 06:47:58 PM PDT 24
Finished	Jun 29 06:48:00 PM PDT 24
Peak memory	202252 kb
Host	smart-48ec2ee3-165d-4582-91d0-316585351445
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250218261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 15.sram_ctrl_tl_errors.1250218261
Directory	/workspace/15.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.857967076
Short name	T1008
Test name
Test status
Simulation time	357900373 ps
CPU time	2.47 seconds
Started	Jun 29 06:48:02 PM PDT 24
Finished	Jun 29 06:48:05 PM PDT 24
Peak memory	210372 kb
Host	smart-7bde38f6-53e4-40df-9263-2ac4560c6a76
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857967076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 15.sram_ctrl_tl_intg_err.857967076
Directory	/workspace/15.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2996426174
Short name	T1002
Test name
Test status
Simulation time	35943363 ps
CPU time	2.04 seconds
Started	Jun 29 06:47:59 PM PDT 24
Finished	Jun 29 06:48:02 PM PDT 24
Peak memory	210456 kb
Host	smart-6e8ea0e7-5e6d-4c8f-9ea1-5bb8b2822db9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996426174 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.2996426174
Directory	/workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.737695089
Short name	T968
Test name
Test status
Simulation time	33286875 ps
CPU time	0.69 seconds
Started	Jun 29 06:47:59 PM PDT 24
Finished	Jun 29 06:48:00 PM PDT 24
Peak memory	201848 kb
Host	smart-842c1bb4-7554-4244-8608-e401f3c2632a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737695089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 16.sram_ctrl_csr_rw.737695089
Directory	/workspace/16.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2062005024
Short name	T60
Test name
Test status
Simulation time	1461181095 ps
CPU time	3.34 seconds
Started	Jun 29 06:47:58 PM PDT 24
Finished	Jun 29 06:48:02 PM PDT 24
Peak memory	202296 kb
Host	smart-b2240f68-fee2-4084-b9f7-e0ea22ae06bd
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062005024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.2062005024
Directory	/workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4212921268
Short name	T97
Test name
Test status
Simulation time	77844352 ps
CPU time	0.75 seconds
Started	Jun 29 06:47:58 PM PDT 24
Finished	Jun 29 06:47:59 PM PDT 24
Peak memory	202020 kb
Host	smart-603969cf-8a8a-427e-8d6c-d6ff40d597cf
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212921268 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.4212921268
Directory	/workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2709725209
Short name	T997
Test name
Test status
Simulation time	116574118 ps
CPU time	4.24 seconds
Started	Jun 29 06:48:03 PM PDT 24
Finished	Jun 29 06:48:08 PM PDT 24
Peak memory	210364 kb
Host	smart-5733a1ff-ba05-4b70-a97b-65e266a57f32
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709725209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 16.sram_ctrl_tl_errors.2709725209
Directory	/workspace/16.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1220894059
Short name	T979
Test name
Test status
Simulation time	122975701 ps
CPU time	1.16 seconds
Started	Jun 29 06:47:58 PM PDT 24
Finished	Jun 29 06:48:00 PM PDT 24
Peak memory	210284 kb
Host	smart-ea8937e8-2778-43e0-b818-4bdb4adb0a23
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220894059 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.1220894059
Directory	/workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.287045939
Short name	T1022
Test name
Test status
Simulation time	42773832 ps
CPU time	0.66 seconds
Started	Jun 29 06:48:03 PM PDT 24
Finished	Jun 29 06:48:04 PM PDT 24
Peak memory	201948 kb
Host	smart-bbeb7f84-fa94-45b0-bf6c-d8882cd386e7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287045939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 17.sram_ctrl_csr_rw.287045939
Directory	/workspace/17.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.922351413
Short name	T966
Test name
Test status
Simulation time	78887695 ps
CPU time	0.77 seconds
Started	Jun 29 06:48:03 PM PDT 24
Finished	Jun 29 06:48:04 PM PDT 24
Peak memory	201988 kb
Host	smart-4496cd1c-add5-488e-bf2a-0190b3805916
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922351413 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.922351413
Directory	/workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.231500881
Short name	T992
Test name
Test status
Simulation time	153630600 ps
CPU time	2.88 seconds
Started	Jun 29 06:48:04 PM PDT 24
Finished	Jun 29 06:48:07 PM PDT 24
Peak memory	202272 kb
Host	smart-b1d2de49-d80a-4004-ac58-e3c806f090a7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231500881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.231500881
Directory	/workspace/17.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3355826170
Short name	T984
Test name
Test status
Simulation time	30626439 ps
CPU time	0.83 seconds
Started	Jun 29 06:48:05 PM PDT 24
Finished	Jun 29 06:48:07 PM PDT 24
Peak memory	202044 kb
Host	smart-3a065c49-a8f6-4c0e-a374-0f3a6339ab2a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355826170 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.3355826170
Directory	/workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3320126100
Short name	T999
Test name
Test status
Simulation time	42058839 ps
CPU time	0.69 seconds
Started	Jun 29 06:48:07 PM PDT 24
Finished	Jun 29 06:48:08 PM PDT 24
Peak memory	201908 kb
Host	smart-9984e97e-0bae-4648-a5bc-d58d7d3e5364
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320126100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_csr_rw.3320126100
Directory	/workspace/18.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1494692587
Short name	T990
Test name
Test status
Simulation time	245413667 ps
CPU time	2.07 seconds
Started	Jun 29 06:48:01 PM PDT 24
Finished	Jun 29 06:48:03 PM PDT 24
Peak memory	202060 kb
Host	smart-12243796-af35-4f82-997d-5544e940597c
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494692587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.1494692587
Directory	/workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2327528019
Short name	T100
Test name
Test status
Simulation time	33463791 ps
CPU time	0.73 seconds
Started	Jun 29 06:48:07 PM PDT 24
Finished	Jun 29 06:48:08 PM PDT 24
Peak memory	201844 kb
Host	smart-5f2b25bf-a579-410a-a5f7-fe29f85a4e52
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327528019 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.2327528019
Directory	/workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3933549440
Short name	T953
Test name
Test status
Simulation time	47538772 ps
CPU time	2.34 seconds
Started	Jun 29 06:48:04 PM PDT 24
Finished	Jun 29 06:48:07 PM PDT 24
Peak memory	210424 kb
Host	smart-d1befb82-4d1f-480e-9013-393552f13774
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933549440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 18.sram_ctrl_tl_errors.3933549440
Directory	/workspace/18.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1533335673
Short name	T134
Test name
Test status
Simulation time	321200585 ps
CPU time	2.62 seconds
Started	Jun 29 06:48:07 PM PDT 24
Finished	Jun 29 06:48:10 PM PDT 24
Peak memory	210416 kb
Host	smart-a8d7709b-0923-4084-b76f-fe805e640f76
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533335673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 18.sram_ctrl_tl_intg_err.1533335673
Directory	/workspace/18.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.673476377
Short name	T955
Test name
Test status
Simulation time	18169439 ps
CPU time	0.63 seconds
Started	Jun 29 06:48:09 PM PDT 24
Finished	Jun 29 06:48:10 PM PDT 24
Peak memory	201876 kb
Host	smart-7d4c39c7-513e-4191-ba2f-68dc383148c2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673476377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 19.sram_ctrl_csr_rw.673476377
Directory	/workspace/19.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4165849533
Short name	T978
Test name
Test status
Simulation time	441932527 ps
CPU time	3.28 seconds
Started	Jun 29 06:48:06 PM PDT 24
Finished	Jun 29 06:48:10 PM PDT 24
Peak memory	202292 kb
Host	smart-55bbd121-2e2e-48c3-a362-70a0627c4045
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165849533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.4165849533
Directory	/workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2560581341
Short name	T981
Test name
Test status
Simulation time	40033238 ps
CPU time	0.78 seconds
Started	Jun 29 06:48:09 PM PDT 24
Finished	Jun 29 06:48:10 PM PDT 24
Peak memory	202020 kb
Host	smart-7fdc4042-289d-4c1e-9637-227bb2bd655f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560581341 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.2560581341
Directory	/workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2438485929
Short name	T1020
Test name
Test status
Simulation time	65070663 ps
CPU time	1.98 seconds
Started	Jun 29 06:48:07 PM PDT 24
Finished	Jun 29 06:48:10 PM PDT 24
Peak memory	202196 kb
Host	smart-8cbbb06f-d23f-4468-ba5b-93a02414192e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438485929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 19.sram_ctrl_tl_errors.2438485929
Directory	/workspace/19.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3903378160
Short name	T962
Test name
Test status
Simulation time	240205221 ps
CPU time	1.59 seconds
Started	Jun 29 06:48:06 PM PDT 24
Finished	Jun 29 06:48:08 PM PDT 24
Peak memory	210400 kb
Host	smart-654e5b0e-f9fe-470e-9018-3112143b7623
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903378160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 19.sram_ctrl_tl_intg_err.3903378160
Directory	/workspace/19.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.4189731313
Short name	T81
Test name
Test status
Simulation time	34949796 ps
CPU time	0.66 seconds
Started	Jun 29 06:47:38 PM PDT 24
Finished	Jun 29 06:47:41 PM PDT 24
Peak memory	201880 kb
Host	smart-cd65b893-9dfc-4ff1-822f-aa530b46603b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189731313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_aliasing.4189731313
Directory	/workspace/2.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.618325946
Short name	T988
Test name
Test status
Simulation time	44553508 ps
CPU time	1.78 seconds
Started	Jun 29 06:47:38 PM PDT 24
Finished	Jun 29 06:47:41 PM PDT 24
Peak memory	202100 kb
Host	smart-d08b6541-71ec-4698-a086-b976518d8fda
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618325946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bit_bash.618325946
Directory	/workspace/2.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2866380691
Short name	T967
Test name
Test status
Simulation time	43563152 ps
CPU time	0.7 seconds
Started	Jun 29 06:47:42 PM PDT 24
Finished	Jun 29 06:47:43 PM PDT 24
Peak memory	201392 kb
Host	smart-b366899f-c483-40ae-90f1-9f1989fa8162
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866380691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_hw_reset.2866380691
Directory	/workspace/2.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.35303073
Short name	T970
Test name
Test status
Simulation time	59763888 ps
CPU time	1.72 seconds
Started	Jun 29 06:47:37 PM PDT 24
Finished	Jun 29 06:47:40 PM PDT 24
Peak memory	210376 kb
Host	smart-9dafa294-9df6-4253-b8b9-ffb3727d0736
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35303073 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.35303073
Directory	/workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.4190809164
Short name	T985
Test name
Test status
Simulation time	16418180 ps
CPU time	0.68 seconds
Started	Jun 29 06:47:40 PM PDT 24
Finished	Jun 29 06:47:43 PM PDT 24
Peak memory	201960 kb
Host	smart-fa0de9c6-a88a-47b6-a7ee-47d69fc2b181
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190809164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_csr_rw.4190809164
Directory	/workspace/2.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1225657204
Short name	T89
Test name
Test status
Simulation time	1618090004 ps
CPU time	3.53 seconds
Started	Jun 29 06:47:39 PM PDT 24
Finished	Jun 29 06:47:44 PM PDT 24
Peak memory	202300 kb
Host	smart-a2475c7b-c1f4-497c-9ce3-280f846887ae
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225657204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.1225657204
Directory	/workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.672818131
Short name	T974
Test name
Test status
Simulation time	20805033 ps
CPU time	0.73 seconds
Started	Jun 29 06:47:40 PM PDT 24
Finished	Jun 29 06:47:42 PM PDT 24
Peak memory	201980 kb
Host	smart-2ff0637d-188b-4458-b21d-556247f5f39b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672818131 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.672818131
Directory	/workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2010819222
Short name	T124
Test name
Test status
Simulation time	449326947 ps
CPU time	3.9 seconds
Started	Jun 29 06:47:37 PM PDT 24
Finished	Jun 29 06:47:42 PM PDT 24
Peak memory	210444 kb
Host	smart-c65ccb97-a838-4385-9c7c-ac613d857747
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010819222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 2.sram_ctrl_tl_errors.2010819222
Directory	/workspace/2.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.626295742
Short name	T73
Test name
Test status
Simulation time	35442443 ps
CPU time	0.78 seconds
Started	Jun 29 06:47:46 PM PDT 24
Finished	Jun 29 06:47:47 PM PDT 24
Peak memory	201880 kb
Host	smart-e1efd3e1-40e1-412d-bc7a-b20300ae9e08
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626295742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_aliasing.626295742
Directory	/workspace/3.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2164600520
Short name	T69
Test name
Test status
Simulation time	718889184 ps
CPU time	2.35 seconds
Started	Jun 29 06:47:45 PM PDT 24
Finished	Jun 29 06:47:48 PM PDT 24
Peak memory	202072 kb
Host	smart-2058de24-1888-4df2-b690-fbee8fe64b70
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164600520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_bit_bash.2164600520
Directory	/workspace/3.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2577043021
Short name	T1012
Test name
Test status
Simulation time	79019510 ps
CPU time	0.65 seconds
Started	Jun 29 06:47:44 PM PDT 24
Finished	Jun 29 06:47:45 PM PDT 24
Peak memory	201928 kb
Host	smart-662a7d31-3260-40b4-b470-1f8ac31bb770
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577043021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_hw_reset.2577043021
Directory	/workspace/3.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.964264399
Short name	T991
Test name
Test status
Simulation time	16802122 ps
CPU time	0.7 seconds
Started	Jun 29 06:47:48 PM PDT 24
Finished	Jun 29 06:47:49 PM PDT 24
Peak memory	201880 kb
Host	smart-91cd7163-349e-4b51-9e47-1a6fd52cb5fb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964264399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.sram_ctrl_csr_rw.964264399
Directory	/workspace/3.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1124044558
Short name	T90
Test name
Test status
Simulation time	1600702328 ps
CPU time	3.19 seconds
Started	Jun 29 06:47:39 PM PDT 24
Finished	Jun 29 06:47:44 PM PDT 24
Peak memory	202328 kb
Host	smart-256b96ff-68a0-4797-a3b5-e3a4f75eea64
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124044558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.1124044558
Directory	/workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3114143243
Short name	T1006
Test name
Test status
Simulation time	24882140 ps
CPU time	0.66 seconds
Started	Jun 29 06:47:48 PM PDT 24
Finished	Jun 29 06:47:50 PM PDT 24
Peak memory	202020 kb
Host	smart-35d54486-1b93-498b-8b09-d981c37feefc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114143243 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.3114143243
Directory	/workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3877419406
Short name	T954
Test name
Test status
Simulation time	59123761 ps
CPU time	1.86 seconds
Started	Jun 29 06:47:48 PM PDT 24
Finished	Jun 29 06:47:50 PM PDT 24
Peak memory	202160 kb
Host	smart-081acbc8-785b-4964-a1f6-5b7d76764450
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877419406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 3.sram_ctrl_tl_errors.3877419406
Directory	/workspace/3.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4239978627
Short name	T138
Test name
Test status
Simulation time	159703048 ps
CPU time	1.63 seconds
Started	Jun 29 06:47:46 PM PDT 24
Finished	Jun 29 06:47:48 PM PDT 24
Peak memory	202176 kb
Host	smart-67dd677d-17e5-412b-b8b0-afd886868958
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239978627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.sram_ctrl_tl_intg_err.4239978627
Directory	/workspace/3.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2207471530
Short name	T987
Test name
Test status
Simulation time	66293560 ps
CPU time	0.71 seconds
Started	Jun 29 06:47:49 PM PDT 24
Finished	Jun 29 06:47:50 PM PDT 24
Peak memory	201908 kb
Host	smart-206a3841-d306-4eb0-8e0e-15bacb97c6e9
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207471530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_aliasing.2207471530
Directory	/workspace/4.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.317677268
Short name	T982
Test name
Test status
Simulation time	102523770 ps
CPU time	1.21 seconds
Started	Jun 29 06:47:45 PM PDT 24
Finished	Jun 29 06:47:46 PM PDT 24
Peak memory	202088 kb
Host	smart-73dc27d8-597b-4f9b-93a8-b45803e3a6e6
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317677268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_bit_bash.317677268
Directory	/workspace/4.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1978329152
Short name	T958
Test name
Test status
Simulation time	55337202 ps
CPU time	0.63 seconds
Started	Jun 29 06:47:47 PM PDT 24
Finished	Jun 29 06:47:48 PM PDT 24
Peak memory	201952 kb
Host	smart-c6f7c2a8-a0dd-4feb-8a74-4724e1687bdb
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978329152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_hw_reset.1978329152
Directory	/workspace/4.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3073774426
Short name	T1005
Test name
Test status
Simulation time	47454745 ps
CPU time	1.71 seconds
Started	Jun 29 06:47:46 PM PDT 24
Finished	Jun 29 06:47:48 PM PDT 24
Peak memory	210488 kb
Host	smart-339a6ed5-8f3b-408b-b9c7-401dd44966ca
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073774426 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.3073774426
Directory	/workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3811320762
Short name	T80
Test name
Test status
Simulation time	14012968 ps
CPU time	0.65 seconds
Started	Jun 29 06:47:45 PM PDT 24
Finished	Jun 29 06:47:47 PM PDT 24
Peak memory	201932 kb
Host	smart-5014e75f-5e8f-4f13-bef3-8bc0dd570a60
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811320762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_csr_rw.3811320762
Directory	/workspace/4.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.4218564932
Short name	T86
Test name
Test status
Simulation time	1559974594 ps
CPU time	3.13 seconds
Started	Jun 29 06:47:45 PM PDT 24
Finished	Jun 29 06:47:49 PM PDT 24
Peak memory	202224 kb
Host	smart-765c40dd-a7dd-4ac8-ad3f-dc23a323036d
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218564932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.4218564932
Directory	/workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1710751434
Short name	T1011
Test name
Test status
Simulation time	16648949 ps
CPU time	0.71 seconds
Started	Jun 29 06:47:46 PM PDT 24
Finished	Jun 29 06:47:48 PM PDT 24
Peak memory	201948 kb
Host	smart-6bdee44b-3698-4554-8919-fd7b65db76ab
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710751434 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.1710751434
Directory	/workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3639363540
Short name	T940
Test name
Test status
Simulation time	25974896 ps
CPU time	2.23 seconds
Started	Jun 29 06:47:50 PM PDT 24
Finished	Jun 29 06:47:53 PM PDT 24
Peak memory	202244 kb
Host	smart-bdfd93ce-f226-42d0-9a5b-6af057082da4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639363540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 4.sram_ctrl_tl_errors.3639363540
Directory	/workspace/4.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2411084930
Short name	T136
Test name
Test status
Simulation time	503519376 ps
CPU time	2.71 seconds
Started	Jun 29 06:47:47 PM PDT 24
Finished	Jun 29 06:47:50 PM PDT 24
Peak memory	210344 kb
Host	smart-56cdbbd6-d947-4ccd-8799-05f29abe3eef
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411084930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.sram_ctrl_tl_intg_err.2411084930
Directory	/workspace/4.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3242124972
Short name	T1014
Test name
Test status
Simulation time	89119509 ps
CPU time	1.98 seconds
Started	Jun 29 06:47:47 PM PDT 24
Finished	Jun 29 06:47:50 PM PDT 24
Peak memory	210424 kb
Host	smart-cc507155-f86f-42f4-84ff-35a9a8902ca6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242124972 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.3242124972
Directory	/workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.205753265
Short name	T960
Test name
Test status
Simulation time	28847629 ps
CPU time	0.73 seconds
Started	Jun 29 06:47:46 PM PDT 24
Finished	Jun 29 06:47:47 PM PDT 24
Peak memory	201900 kb
Host	smart-f875463b-03cf-4e86-9e63-e9695cf11c56
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205753265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 5.sram_ctrl_csr_rw.205753265
Directory	/workspace/5.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2939245846
Short name	T88
Test name
Test status
Simulation time	1007343764 ps
CPU time	2.15 seconds
Started	Jun 29 06:47:46 PM PDT 24
Finished	Jun 29 06:47:49 PM PDT 24
Peak memory	202104 kb
Host	smart-d9ccdbe7-3b84-41c8-ae11-ddcd83d52184
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939245846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.2939245846
Directory	/workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2137090052
Short name	T1000
Test name
Test status
Simulation time	33186643 ps
CPU time	0.78 seconds
Started	Jun 29 06:47:45 PM PDT 24
Finished	Jun 29 06:47:47 PM PDT 24
Peak memory	201984 kb
Host	smart-f0ce7cf7-ae9f-42da-935e-36f2a4c21294
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137090052 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.2137090052
Directory	/workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2853168908
Short name	T956
Test name
Test status
Simulation time	293918538 ps
CPU time	4.56 seconds
Started	Jun 29 06:47:44 PM PDT 24
Finished	Jun 29 06:47:48 PM PDT 24
Peak memory	210412 kb
Host	smart-b6ee2c5d-7224-43ef-9503-0a2a7d0774b9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853168908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 5.sram_ctrl_tl_errors.2853168908
Directory	/workspace/5.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.741590102
Short name	T1019
Test name
Test status
Simulation time	783235604 ps
CPU time	2.2 seconds
Started	Jun 29 06:47:45 PM PDT 24
Finished	Jun 29 06:47:48 PM PDT 24
Peak memory	210336 kb
Host	smart-5bcd35e7-8e64-403d-8364-056be6e8ecf5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741590102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 5.sram_ctrl_tl_intg_err.741590102
Directory	/workspace/5.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.263353950
Short name	T114
Test name
Test status
Simulation time	158305998 ps
CPU time	1.54 seconds
Started	Jun 29 06:47:53 PM PDT 24
Finished	Jun 29 06:47:56 PM PDT 24
Peak memory	210444 kb
Host	smart-c8517150-c9b4-46c4-a725-2465e882eb91
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263353950 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.263353950
Directory	/workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2554444308
Short name	T973
Test name
Test status
Simulation time	45016277 ps
CPU time	0.72 seconds
Started	Jun 29 06:47:49 PM PDT 24
Finished	Jun 29 06:47:50 PM PDT 24
Peak memory	201444 kb
Host	smart-3ef99d64-c0e7-4c54-b8c7-c228df44f9b5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554444308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_csr_rw.2554444308
Directory	/workspace/6.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.4177098207
Short name	T101
Test name
Test status
Simulation time	208775494 ps
CPU time	1.95 seconds
Started	Jun 29 06:47:48 PM PDT 24
Finished	Jun 29 06:47:50 PM PDT 24
Peak memory	202016 kb
Host	smart-9b0bf6d4-07a9-48da-8ff5-1adf9185364c
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177098207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.4177098207
Directory	/workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1331922112
Short name	T975
Test name
Test status
Simulation time	38776609 ps
CPU time	0.77 seconds
Started	Jun 29 06:47:45 PM PDT 24
Finished	Jun 29 06:47:46 PM PDT 24
Peak memory	202024 kb
Host	smart-806e32d8-38f8-4d54-8973-fb9637f6dbba
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331922112 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.1331922112
Directory	/workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1969002231
Short name	T957
Test name
Test status
Simulation time	21968836 ps
CPU time	1.55 seconds
Started	Jun 29 06:47:46 PM PDT 24
Finished	Jun 29 06:47:48 PM PDT 24
Peak memory	202244 kb
Host	smart-86d2f836-e3cd-4dc9-9df5-c33e16249f8b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969002231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 6.sram_ctrl_tl_errors.1969002231
Directory	/workspace/6.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4259620235
Short name	T130
Test name
Test status
Simulation time	727505173 ps
CPU time	2.45 seconds
Started	Jun 29 06:47:44 PM PDT 24
Finished	Jun 29 06:47:46 PM PDT 24
Peak memory	202224 kb
Host	smart-aabf17cb-0794-4c16-991a-f730a8eea27f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259620235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 6.sram_ctrl_tl_intg_err.4259620235
Directory	/workspace/6.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2382534130
Short name	T947
Test name
Test status
Simulation time	142116307 ps
CPU time	1.81 seconds
Started	Jun 29 06:47:54 PM PDT 24
Finished	Jun 29 06:47:57 PM PDT 24
Peak memory	210448 kb
Host	smart-0f536c2d-1ace-44c1-94d8-d86370069d01
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382534130 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.2382534130
Directory	/workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3902691672
Short name	T1025
Test name
Test status
Simulation time	38190485 ps
CPU time	0.67 seconds
Started	Jun 29 06:47:58 PM PDT 24
Finished	Jun 29 06:47:59 PM PDT 24
Peak memory	201840 kb
Host	smart-e7107974-9e2c-4819-b975-a3d118c11d1f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902691672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_csr_rw.3902691672
Directory	/workspace/7.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3114636268
Short name	T1021
Test name
Test status
Simulation time	427471974 ps
CPU time	2.96 seconds
Started	Jun 29 06:47:51 PM PDT 24
Finished	Jun 29 06:47:54 PM PDT 24
Peak memory	202344 kb
Host	smart-9b025066-6e24-4ab2-b53a-aaca93e9b3c4
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114636268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.3114636268
Directory	/workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1177348780
Short name	T1016
Test name
Test status
Simulation time	17696202 ps
CPU time	0.7 seconds
Started	Jun 29 06:47:53 PM PDT 24
Finished	Jun 29 06:47:54 PM PDT 24
Peak memory	201696 kb
Host	smart-f78f61f0-c87b-44b5-a6d2-0009a14e72a7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177348780 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.1177348780
Directory	/workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3826495440
Short name	T952
Test name
Test status
Simulation time	72772800 ps
CPU time	3.64 seconds
Started	Jun 29 06:47:53 PM PDT 24
Finished	Jun 29 06:47:57 PM PDT 24
Peak memory	202224 kb
Host	smart-2aff12bd-f7bc-48a4-baec-cf64a60d332d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826495440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 7.sram_ctrl_tl_errors.3826495440
Directory	/workspace/7.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2116815508
Short name	T58
Test name
Test status
Simulation time	174276369 ps
CPU time	1.46 seconds
Started	Jun 29 06:47:57 PM PDT 24
Finished	Jun 29 06:47:59 PM PDT 24
Peak memory	210380 kb
Host	smart-7274be14-7e2e-4a70-9ba3-1f46902c12bd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116815508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 7.sram_ctrl_tl_intg_err.2116815508
Directory	/workspace/7.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3297757229
Short name	T944
Test name
Test status
Simulation time	137044499 ps
CPU time	1.01 seconds
Started	Jun 29 06:47:51 PM PDT 24
Finished	Jun 29 06:47:53 PM PDT 24
Peak memory	202148 kb
Host	smart-43339f03-a89f-4e48-acb6-b4c0626c6fe5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297757229 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.3297757229
Directory	/workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1823244480
Short name	T943
Test name
Test status
Simulation time	34563521 ps
CPU time	0.69 seconds
Started	Jun 29 06:47:55 PM PDT 24
Finished	Jun 29 06:47:57 PM PDT 24
Peak memory	201648 kb
Host	smart-b94fe101-fe95-4119-bff2-aff66f794a24
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823244480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_csr_rw.1823244480
Directory	/workspace/8.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3761538738
Short name	T93
Test name
Test status
Simulation time	1412752401 ps
CPU time	2.27 seconds
Started	Jun 29 06:47:55 PM PDT 24
Finished	Jun 29 06:47:58 PM PDT 24
Peak memory	202148 kb
Host	smart-a6f927e0-6107-4d8e-a1bc-000a38b80c43
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761538738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.3761538738
Directory	/workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2150231028
Short name	T989
Test name
Test status
Simulation time	135365565 ps
CPU time	0.79 seconds
Started	Jun 29 06:47:56 PM PDT 24
Finished	Jun 29 06:47:57 PM PDT 24
Peak memory	201920 kb
Host	smart-ef5778c1-7ef3-4d09-9c03-2724219b5206
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150231028 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.2150231028
Directory	/workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1045816066
Short name	T1017
Test name
Test status
Simulation time	128588504 ps
CPU time	3.82 seconds
Started	Jun 29 06:47:50 PM PDT 24
Finished	Jun 29 06:47:54 PM PDT 24
Peak memory	210452 kb
Host	smart-3fa69917-d94a-4441-acd5-c8bb9beb11bc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045816066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 8.sram_ctrl_tl_errors.1045816066
Directory	/workspace/8.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2865772181
Short name	T137
Test name
Test status
Simulation time	572700779 ps
CPU time	2.1 seconds
Started	Jun 29 06:47:58 PM PDT 24
Finished	Jun 29 06:48:01 PM PDT 24
Peak memory	210284 kb
Host	smart-163c8d92-7112-4225-8738-79dfe3a6e58e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865772181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 8.sram_ctrl_tl_intg_err.2865772181
Directory	/workspace/8.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.851031110
Short name	T971
Test name
Test status
Simulation time	164271057 ps
CPU time	1.39 seconds
Started	Jun 29 06:47:57 PM PDT 24
Finished	Jun 29 06:47:59 PM PDT 24
Peak memory	210472 kb
Host	smart-774536ad-560c-4a47-8e39-a454080e4286
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851031110 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.851031110
Directory	/workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3680586099
Short name	T92
Test name
Test status
Simulation time	28045650 ps
CPU time	0.68 seconds
Started	Jun 29 06:47:57 PM PDT 24
Finished	Jun 29 06:47:58 PM PDT 24
Peak memory	201376 kb
Host	smart-089cc136-c546-4f73-bb15-fcce40d4aff5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680586099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_csr_rw.3680586099
Directory	/workspace/9.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1976219999
Short name	T996
Test name
Test status
Simulation time	409834495 ps
CPU time	3.01 seconds
Started	Jun 29 06:47:53 PM PDT 24
Finished	Jun 29 06:47:57 PM PDT 24
Peak memory	202280 kb
Host	smart-570c59f7-4c5c-4bab-ba23-bde20b091d68
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976219999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.1976219999
Directory	/workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3240191387
Short name	T99
Test name
Test status
Simulation time	58662198 ps
CPU time	0.75 seconds
Started	Jun 29 06:47:53 PM PDT 24
Finished	Jun 29 06:47:55 PM PDT 24
Peak memory	201944 kb
Host	smart-935eedb8-45c7-433e-aad5-e6c97e3de5da
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240191387 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.3240191387
Directory	/workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1720430549
Short name	T945
Test name
Test status
Simulation time	31486931 ps
CPU time	2.41 seconds
Started	Jun 29 06:47:53 PM PDT 24
Finished	Jun 29 06:47:57 PM PDT 24
Peak memory	202248 kb
Host	smart-9ae37e95-33b3-4149-813f-2f9f8389f696
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720430549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 9.sram_ctrl_tl_errors.1720430549
Directory	/workspace/9.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.44411554
Short name	T131
Test name
Test status
Simulation time	479731251 ps
CPU time	2.09 seconds
Started	Jun 29 06:47:50 PM PDT 24
Finished	Jun 29 06:47:53 PM PDT 24
Peak memory	210372 kb
Host	smart-f34dcd35-f087-4828-a596-ad4473e3be8c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44411554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_te st +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 9.sram_ctrl_tl_intg_err.44411554
Directory	/workspace/9.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3262379994
Short name	T766
Test name
Test status
Simulation time	2228632918 ps
CPU time	250.61 seconds
Started	Jun 29 06:53:51 PM PDT 24
Finished	Jun 29 06:58:03 PM PDT 24
Peak memory	336224 kb
Host	smart-40feb40e-9636-4d91-ac6b-b67d8018e36d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262379994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_access_during_key_req.3262379994
Directory	/workspace/0.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/0.sram_ctrl_alert_test.3272540093
Short name	T416
Test name
Test status
Simulation time	91149160 ps
CPU time	0.69 seconds
Started	Jun 29 06:53:49 PM PDT 24
Finished	Jun 29 06:53:51 PM PDT 24
Peak memory	202604 kb
Host	smart-6e82a676-8c43-41f8-a871-00b3e4a160d0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272540093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.3272540093
Directory	/workspace/0.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/0.sram_ctrl_bijection.40862584
Short name	T485
Test name
Test status
Simulation time	3769303419 ps
CPU time	43.26 seconds
Started	Jun 29 06:53:57 PM PDT 24
Finished	Jun 29 06:54:41 PM PDT 24
Peak memory	202916 kb
Host	smart-490c0a68-4dab-4e5a-a614-6db206e245ab
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40862584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.40862584
Directory	/workspace/0.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/0.sram_ctrl_executable.883275303
Short name	T688
Test name
Test status
Simulation time	14736862586 ps
CPU time	1288.49 seconds
Started	Jun 29 06:53:53 PM PDT 24
Finished	Jun 29 07:15:22 PM PDT 24
Peak memory	374300 kb
Host	smart-9aa11353-b60c-4084-9bbf-c931e2338ba2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883275303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable .883275303
Directory	/workspace/0.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/0.sram_ctrl_lc_escalation.413639770
Short name	T159
Test name
Test status
Simulation time	3123536449 ps
CPU time	6.79 seconds
Started	Jun 29 06:53:52 PM PDT 24
Finished	Jun 29 06:54:00 PM PDT 24
Peak memory	202960 kb
Host	smart-12f73925-1bab-47d4-8776-c3906af747b1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413639770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esca lation.413639770
Directory	/workspace/0.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/0.sram_ctrl_max_throughput.2087304940
Short name	T2
Test name
Test status
Simulation time	289363960 ps
CPU time	23.7 seconds
Started	Jun 29 06:53:56 PM PDT 24
Finished	Jun 29 06:54:21 PM PDT 24
Peak memory	284552 kb
Host	smart-b9a2fc7e-c2e3-4b18-8ddf-8703759fb9fe
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087304940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_max_throughput.2087304940
Directory	/workspace/0.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/0.sram_ctrl_mem_partial_access.3167242517
Short name	T805
Test name
Test status
Simulation time	76234145 ps
CPU time	4.49 seconds
Started	Jun 29 06:53:51 PM PDT 24
Finished	Jun 29 06:53:57 PM PDT 24
Peak memory	211048 kb
Host	smart-05bce36a-95d6-4c2e-ac7d-9cd24adeb516
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167242517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_mem_partial_access.3167242517
Directory	/workspace/0.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/0.sram_ctrl_mem_walk.2041793869
Short name	T373
Test name
Test status
Simulation time	4112671439 ps
CPU time	6.52 seconds
Started	Jun 29 06:53:53 PM PDT 24
Finished	Jun 29 06:54:01 PM PDT 24
Peak memory	211240 kb
Host	smart-6ea1ed90-4836-47e8-b724-0945bcf8521a
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041793869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl _mem_walk.2041793869
Directory	/workspace/0.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/0.sram_ctrl_multiple_keys.1153934251
Short name	T781
Test name
Test status
Simulation time	19241436781 ps
CPU time	1235.42 seconds
Started	Jun 29 06:53:49 PM PDT 24
Finished	Jun 29 07:14:25 PM PDT 24
Peak memory	366432 kb
Host	smart-7b858cac-9f08-4919-b6a3-5880489966a0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153934251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip le_keys.1153934251
Directory	/workspace/0.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/0.sram_ctrl_partial_access.1862531658
Short name	T78
Test name
Test status
Simulation time	291060052 ps
CPU time	15.1 seconds
Started	Jun 29 06:53:48 PM PDT 24
Finished	Jun 29 06:54:04 PM PDT 24
Peak memory	253852 kb
Host	smart-98fd69c0-03ad-4e64-b928-bba1b228f014
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862531658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s ram_ctrl_partial_access.1862531658
Directory	/workspace/0.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3141232135
Short name	T489
Test name
Test status
Simulation time	9485421798 ps
CPU time	257.66 seconds
Started	Jun 29 06:53:56 PM PDT 24
Finished	Jun 29 06:58:15 PM PDT 24
Peak memory	202948 kb
Host	smart-d75adc60-e6fe-43e0-9661-3013b8626221
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141232135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.sram_ctrl_partial_access_b2b.3141232135
Directory	/workspace/0.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/0.sram_ctrl_ram_cfg.2247802310
Short name	T25
Test name
Test status
Simulation time	31417593 ps
CPU time	0.78 seconds
Started	Jun 29 06:53:49 PM PDT 24
Finished	Jun 29 06:53:51 PM PDT 24
Peak memory	202880 kb
Host	smart-76a5ce40-2f42-4b51-97eb-cee9b3a1f7a4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247802310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.2247802310
Directory	/workspace/0.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/0.sram_ctrl_regwen.1004881179
Short name	T650
Test name
Test status
Simulation time	17157438178 ps
CPU time	972.97 seconds
Started	Jun 29 06:53:54 PM PDT 24
Finished	Jun 29 07:10:08 PM PDT 24
Peak memory	365396 kb
Host	smart-49b8b048-83aa-4469-8e46-c28d00b851f1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004881179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.1004881179
Directory	/workspace/0.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/0.sram_ctrl_smoke.1092483658
Short name	T428
Test name
Test status
Simulation time	1458420000 ps
CPU time	6.84 seconds
Started	Jun 29 06:53:51 PM PDT 24
Finished	Jun 29 06:53:58 PM PDT 24
Peak memory	202812 kb
Host	smart-2eeb8ce0-eddf-4237-830a-abf33c860ff6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092483658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.1092483658
Directory	/workspace/0.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/0.sram_ctrl_stress_all.1677064392
Short name	T542
Test name
Test status
Simulation time	6876535421 ps
CPU time	2036.76 seconds
Started	Jun 29 06:53:51 PM PDT 24
Finished	Jun 29 07:27:49 PM PDT 24
Peak memory	363704 kb
Host	smart-310de892-0af1-4a4d-97cb-af78aceccf74
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677064392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.sram_ctrl_stress_all.1677064392
Directory	/workspace/0.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3381760489
Short name	T46
Test name
Test status
Simulation time	1710557002 ps
CPU time	37.63 seconds
Started	Jun 29 06:53:50 PM PDT 24
Finished	Jun 29 06:54:28 PM PDT 24
Peak memory	250288 kb
Host	smart-66e7aafe-a8ab-4fc4-87eb-00bb7ed35f0f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3381760489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.3381760489
Directory	/workspace/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.sram_ctrl_stress_pipeline.445598644
Short name	T77
Test name
Test status
Simulation time	3612024060 ps
CPU time	357.1 seconds
Started	Jun 29 06:53:49 PM PDT 24
Finished	Jun 29 06:59:47 PM PDT 24
Peak memory	202924 kb
Host	smart-9457c372-ca18-400f-8b77-05e772583da8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445598644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. sram_ctrl_stress_pipeline.445598644
Directory	/workspace/0.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3519283028
Short name	T415
Test name
Test status
Simulation time	105702851 ps
CPU time	28.11 seconds
Started	Jun 29 06:53:54 PM PDT 24
Finished	Jun 29 06:54:23 PM PDT 24
Peak memory	290716 kb
Host	smart-cff84d47-dd08-4a06-83ae-975055fbd17f
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519283028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.3519283028
Directory	/workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2306719750
Short name	T917
Test name
Test status
Simulation time	20704815349 ps
CPU time	1288.93 seconds
Started	Jun 29 06:53:48 PM PDT 24
Finished	Jun 29 07:15:18 PM PDT 24
Peak memory	369464 kb
Host	smart-ce4c72b6-455f-4d08-9d5a-6b02a2b99fde
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306719750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_access_during_key_req.2306719750
Directory	/workspace/1.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/1.sram_ctrl_alert_test.197678559
Short name	T214
Test name
Test status
Simulation time	11594273 ps
CPU time	0.64 seconds
Started	Jun 29 06:53:53 PM PDT 24
Finished	Jun 29 06:53:55 PM PDT 24
Peak memory	202672 kb
Host	smart-548d7051-4faf-422d-9660-759793b65eb4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197678559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.197678559
Directory	/workspace/1.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.sram_ctrl_bijection.1532302020
Short name	T804
Test name
Test status
Simulation time	3653427901 ps
CPU time	74.89 seconds
Started	Jun 29 06:53:52 PM PDT 24
Finished	Jun 29 06:55:08 PM PDT 24
Peak memory	202956 kb
Host	smart-660b732b-3911-4bd7-b003-fe04e826b519
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532302020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection. 1532302020
Directory	/workspace/1.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/1.sram_ctrl_executable.1193122018
Short name	T442
Test name
Test status
Simulation time	26054952117 ps
CPU time	1039.39 seconds
Started	Jun 29 06:53:54 PM PDT 24
Finished	Jun 29 07:11:14 PM PDT 24
Peak memory	371636 kb
Host	smart-ffe5107a-3c58-44c8-aca0-d6bb00dc95e1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193122018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl e.1193122018
Directory	/workspace/1.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/1.sram_ctrl_lc_escalation.1503338124
Short name	T379
Test name
Test status
Simulation time	2039613413 ps
CPU time	7.43 seconds
Started	Jun 29 06:53:51 PM PDT 24
Finished	Jun 29 06:54:00 PM PDT 24
Peak memory	202728 kb
Host	smart-0227badf-2a70-41e8-8da5-b04e6f9f5552
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503338124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc alation.1503338124
Directory	/workspace/1.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/1.sram_ctrl_max_throughput.2083004877
Short name	T638
Test name
Test status
Simulation time	83074157 ps
CPU time	28.24 seconds
Started	Jun 29 06:53:47 PM PDT 24
Finished	Jun 29 06:54:16 PM PDT 24
Peak memory	279904 kb
Host	smart-89b2b481-7907-41d7-a52d-c660bccc6045
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083004877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_max_throughput.2083004877
Directory	/workspace/1.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/1.sram_ctrl_mem_partial_access.2704113532
Short name	T83
Test name
Test status
Simulation time	161214938 ps
CPU time	2.52 seconds
Started	Jun 29 06:53:51 PM PDT 24
Finished	Jun 29 06:53:54 PM PDT 24
Peak memory	211020 kb
Host	smart-195b4302-6564-4a57-b098-0490cd3b715b
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704113532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_mem_partial_access.2704113532
Directory	/workspace/1.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/1.sram_ctrl_mem_walk.3534898313
Short name	T232
Test name
Test status
Simulation time	332665718 ps
CPU time	5.84 seconds
Started	Jun 29 06:53:50 PM PDT 24
Finished	Jun 29 06:53:56 PM PDT 24
Peak memory	202904 kb
Host	smart-60b0f9e0-148f-4c49-8c5f-f888a7c7c8c5
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534898313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl _mem_walk.3534898313
Directory	/workspace/1.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/1.sram_ctrl_multiple_keys.4058796228
Short name	T40
Test name
Test status
Simulation time	3410609469 ps
CPU time	1483.36 seconds
Started	Jun 29 06:53:57 PM PDT 24
Finished	Jun 29 07:18:41 PM PDT 24
Peak memory	368648 kb
Host	smart-87f7b699-570d-4d23-9cc1-559dafe954f8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058796228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip le_keys.4058796228
Directory	/workspace/1.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/1.sram_ctrl_partial_access.278939811
Short name	T35
Test name
Test status
Simulation time	225091959 ps
CPU time	4.77 seconds
Started	Jun 29 06:53:52 PM PDT 24
Finished	Jun 29 06:53:58 PM PDT 24
Peak memory	202824 kb
Host	smart-f7d37e11-5bb1-4f1f-a2df-05a122ea57f1
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278939811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sr am_ctrl_partial_access.278939811
Directory	/workspace/1.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.199503791
Short name	T279
Test name
Test status
Simulation time	12161665201 ps
CPU time	469.86 seconds
Started	Jun 29 06:53:48 PM PDT 24
Finished	Jun 29 07:01:38 PM PDT 24
Peak memory	202896 kb
Host	smart-ef582c81-2229-46e9-a6ea-9f989369dedd
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199503791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.sram_ctrl_partial_access_b2b.199503791
Directory	/workspace/1.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/1.sram_ctrl_ram_cfg.2445707418
Short name	T26
Test name
Test status
Simulation time	26139842 ps
CPU time	0.77 seconds
Started	Jun 29 06:53:56 PM PDT 24
Finished	Jun 29 06:53:58 PM PDT 24
Peak memory	202856 kb
Host	smart-f602e2e8-686b-4141-99a3-e94dff000db9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445707418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.2445707418
Directory	/workspace/1.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/1.sram_ctrl_regwen.2848850462
Short name	T899
Test name
Test status
Simulation time	36252048421 ps
CPU time	1059.35 seconds
Started	Jun 29 06:53:49 PM PDT 24
Finished	Jun 29 07:11:30 PM PDT 24
Peak memory	366100 kb
Host	smart-d988c9ec-3983-45e9-a5fe-475ca55e35c0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848850462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.2848850462
Directory	/workspace/1.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/1.sram_ctrl_sec_cm.1812326399
Short name	T16
Test name
Test status
Simulation time	148013669 ps
CPU time	2.03 seconds
Started	Jun 29 06:53:54 PM PDT 24
Finished	Jun 29 06:53:57 PM PDT 24
Peak memory	221884 kb
Host	smart-1ff6089f-b512-4a84-bff8-048f3a4e2c77
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812326399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.1812326399
Directory	/workspace/1.sram_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/1.sram_ctrl_smoke.4022549998
Short name	T540
Test name
Test status
Simulation time	376315510 ps
CPU time	31.76 seconds
Started	Jun 29 06:53:47 PM PDT 24
Finished	Jun 29 06:54:19 PM PDT 24
Peak memory	289872 kb
Host	smart-fe1c0355-fe3d-4587-8d31-3f3580911c2c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022549998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.4022549998
Directory	/workspace/1.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.sram_ctrl_stress_all.1446514310
Short name	T488
Test name
Test status
Simulation time	183004794454 ps
CPU time	2897.64 seconds
Started	Jun 29 06:53:46 PM PDT 24
Finished	Jun 29 07:42:05 PM PDT 24
Peak memory	370592 kb
Host	smart-d7919447-d8ec-4666-aa99-80f93486c00b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446514310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.sram_ctrl_stress_all.1446514310
Directory	/workspace/1.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2036564987
Short name	T111
Test name
Test status
Simulation time	1017106835 ps
CPU time	29.94 seconds
Started	Jun 29 06:53:48 PM PDT 24
Finished	Jun 29 06:54:18 PM PDT 24
Peak memory	211208 kb
Host	smart-fcbbd03f-b809-45ee-b31f-132b772885cc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2036564987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.2036564987
Directory	/workspace/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.sram_ctrl_stress_pipeline.347922442
Short name	T667
Test name
Test status
Simulation time	1791450462 ps
CPU time	181.36 seconds
Started	Jun 29 06:53:53 PM PDT 24
Finished	Jun 29 06:56:56 PM PDT 24
Peak memory	202772 kb
Host	smart-d377e9b7-ec9d-41d3-bff0-f555ed7e1c37
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347922442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. sram_ctrl_stress_pipeline.347922442
Directory	/workspace/1.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.688660295
Short name	T852
Test name
Test status
Simulation time	134208001 ps
CPU time	66.75 seconds
Started	Jun 29 06:53:51 PM PDT 24
Finished	Jun 29 06:54:59 PM PDT 24
Peak memory	321344 kb
Host	smart-3c4333e6-e2fc-434d-bd70-be1f086e7870
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688660295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_throughput_w_partial_write.688660295
Directory	/workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3991334540
Short name	T569
Test name
Test status
Simulation time	13660676592 ps
CPU time	1034.99 seconds
Started	Jun 29 06:54:21 PM PDT 24
Finished	Jun 29 07:11:37 PM PDT 24
Peak memory	373796 kb
Host	smart-431eb6cd-b9bd-457a-986b-f461dd379f0e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991334540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_access_during_key_req.3991334540
Directory	/workspace/10.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/10.sram_ctrl_alert_test.1588711568
Short name	T845
Test name
Test status
Simulation time	34992094 ps
CPU time	0.66 seconds
Started	Jun 29 06:54:20 PM PDT 24
Finished	Jun 29 06:54:22 PM PDT 24
Peak memory	202632 kb
Host	smart-e78619a0-f5e8-47ec-9975-4bc5790888eb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588711568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.1588711568
Directory	/workspace/10.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.sram_ctrl_bijection.3039723853
Short name	T456
Test name
Test status
Simulation time	38608372917 ps
CPU time	97.3 seconds
Started	Jun 29 06:54:21 PM PDT 24
Finished	Jun 29 06:55:59 PM PDT 24
Peak memory	202924 kb
Host	smart-5efa93fa-da45-4a82-b476-35c0cbf9180c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039723853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection .3039723853
Directory	/workspace/10.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/10.sram_ctrl_executable.2813942281
Short name	T699
Test name
Test status
Simulation time	5486234204 ps
CPU time	1167.51 seconds
Started	Jun 29 06:54:18 PM PDT 24
Finished	Jun 29 07:13:47 PM PDT 24
Peak memory	374720 kb
Host	smart-9f18cd9d-b8b1-4340-8d84-03220463b3f9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813942281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab le.2813942281
Directory	/workspace/10.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/10.sram_ctrl_lc_escalation.1741388574
Short name	T249
Test name
Test status
Simulation time	274089068 ps
CPU time	3.19 seconds
Started	Jun 29 06:54:18 PM PDT 24
Finished	Jun 29 06:54:22 PM PDT 24
Peak memory	202868 kb
Host	smart-0337f603-eb65-4a56-8767-1a13d1cfa42f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741388574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es calation.1741388574
Directory	/workspace/10.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/10.sram_ctrl_max_throughput.3541109904
Short name	T918
Test name
Test status
Simulation time	152253560 ps
CPU time	17.39 seconds
Started	Jun 29 06:54:20 PM PDT 24
Finished	Jun 29 06:54:39 PM PDT 24
Peak memory	273384 kb
Host	smart-fa4aa2fd-051e-4381-9a40-d1f6b31526ea
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541109904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_max_throughput.3541109904
Directory	/workspace/10.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/10.sram_ctrl_mem_partial_access.113247838
Short name	T763
Test name
Test status
Simulation time	90414862 ps
CPU time	5.18 seconds
Started	Jun 29 06:54:22 PM PDT 24
Finished	Jun 29 06:54:28 PM PDT 24
Peak memory	211032 kb
Host	smart-e59ba84b-5919-4bcf-817e-f326993bc895
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113247838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10 .sram_ctrl_mem_partial_access.113247838
Directory	/workspace/10.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/10.sram_ctrl_mem_walk.67140141
Short name	T470
Test name
Test status
Simulation time	498293238 ps
CPU time	8.92 seconds
Started	Jun 29 06:54:20 PM PDT 24
Finished	Jun 29 06:54:29 PM PDT 24
Peak memory	211088 kb
Host	smart-a09878d2-40dd-4451-b13c-2f13db469308
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67140141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ mem_walk.67140141
Directory	/workspace/10.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/10.sram_ctrl_multiple_keys.2376121670
Short name	T598
Test name
Test status
Simulation time	5073922469 ps
CPU time	221.31 seconds
Started	Jun 29 06:54:23 PM PDT 24
Finished	Jun 29 06:58:05 PM PDT 24
Peak memory	361300 kb
Host	smart-405df198-8200-49ae-a916-f819d2df8d7b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376121670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi ple_keys.2376121670
Directory	/workspace/10.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/10.sram_ctrl_partial_access.1883236674
Short name	T189
Test name
Test status
Simulation time	523665246 ps
CPU time	39.14 seconds
Started	Jun 29 06:54:21 PM PDT 24
Finished	Jun 29 06:55:01 PM PDT 24
Peak memory	292604 kb
Host	smart-ade4eff0-d65f-4324-b81c-f87b83ebe36e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883236674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10. sram_ctrl_partial_access.1883236674
Directory	/workspace/10.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3785895963
Short name	T334
Test name
Test status
Simulation time	11742350357 ps
CPU time	211.57 seconds
Started	Jun 29 06:54:20 PM PDT 24
Finished	Jun 29 06:57:53 PM PDT 24
Peak memory	202900 kb
Host	smart-4fbc6330-0dcc-4556-8710-ea9598f70c38
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785895963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.sram_ctrl_partial_access_b2b.3785895963
Directory	/workspace/10.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/10.sram_ctrl_ram_cfg.4166874794
Short name	T315
Test name
Test status
Simulation time	97678323 ps
CPU time	0.76 seconds
Started	Jun 29 06:54:20 PM PDT 24
Finished	Jun 29 06:54:22 PM PDT 24
Peak memory	202864 kb
Host	smart-c86a9bce-0b11-44b8-ad51-4f5db9e18d33
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166874794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.4166874794
Directory	/workspace/10.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/10.sram_ctrl_regwen.1684186026
Short name	T771
Test name
Test status
Simulation time	19212278591 ps
CPU time	262.59 seconds
Started	Jun 29 06:54:22 PM PDT 24
Finished	Jun 29 06:58:45 PM PDT 24
Peak memory	312460 kb
Host	smart-973138b9-329c-43ea-b592-e112c47010a3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684186026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.1684186026
Directory	/workspace/10.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/10.sram_ctrl_smoke.2928929674
Short name	T626
Test name
Test status
Simulation time	499233434 ps
CPU time	48.74 seconds
Started	Jun 29 06:54:22 PM PDT 24
Finished	Jun 29 06:55:11 PM PDT 24
Peak memory	299760 kb
Host	smart-fcadd9f3-a95a-494a-b341-6bad1a843b16
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928929674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.2928929674
Directory	/workspace/10.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1185142747
Short name	T539
Test name
Test status
Simulation time	3522930271 ps
CPU time	71.82 seconds
Started	Jun 29 06:54:18 PM PDT 24
Finished	Jun 29 06:55:31 PM PDT 24
Peak memory	282800 kb
Host	smart-0b5b0f32-3a83-4606-af50-72949bd90203
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1185142747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.1185142747
Directory	/workspace/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.sram_ctrl_stress_pipeline.1748785484
Short name	T521
Test name
Test status
Simulation time	14554899266 ps
CPU time	345 seconds
Started	Jun 29 06:54:19 PM PDT 24
Finished	Jun 29 07:00:05 PM PDT 24
Peak memory	202912 kb
Host	smart-547bd1dd-254e-4b94-9415-6e45737437ce
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748785484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_stress_pipeline.1748785484
Directory	/workspace/10.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1448346444
Short name	T796
Test name
Test status
Simulation time	70139315 ps
CPU time	6.81 seconds
Started	Jun 29 06:54:19 PM PDT 24
Finished	Jun 29 06:54:27 PM PDT 24
Peak memory	235584 kb
Host	smart-4ddf6bbb-1903-42e5-89ce-8462a69a5823
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448346444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.1448346444
Directory	/workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1429438895
Short name	T181
Test name
Test status
Simulation time	1012296396 ps
CPU time	196.91 seconds
Started	Jun 29 06:54:17 PM PDT 24
Finished	Jun 29 06:57:35 PM PDT 24
Peak memory	348684 kb
Host	smart-15eb9366-39c2-4bd8-9a97-868189f71d5f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429438895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_access_during_key_req.1429438895
Directory	/workspace/11.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/11.sram_ctrl_alert_test.1428918291
Short name	T225
Test name
Test status
Simulation time	11929650 ps
CPU time	0.71 seconds
Started	Jun 29 06:54:20 PM PDT 24
Finished	Jun 29 06:54:22 PM PDT 24
Peak memory	202628 kb
Host	smart-0c01e232-0e76-40da-b860-2831e6fdd6ac
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428918291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.1428918291
Directory	/workspace/11.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.sram_ctrl_bijection.195419761
Short name	T775
Test name
Test status
Simulation time	1526030909 ps
CPU time	30.35 seconds
Started	Jun 29 06:54:19 PM PDT 24
Finished	Jun 29 06:54:50 PM PDT 24
Peak memory	202744 kb
Host	smart-f2b26639-072e-4c89-b1df-d06e701d2848
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195419761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection. 195419761
Directory	/workspace/11.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/11.sram_ctrl_executable.2085629889
Short name	T141
Test name
Test status
Simulation time	50717601763 ps
CPU time	1057.52 seconds
Started	Jun 29 06:54:18 PM PDT 24
Finished	Jun 29 07:11:57 PM PDT 24
Peak memory	375816 kb
Host	smart-aaf39255-ce13-4c15-8cf1-41777a2e1031
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085629889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab le.2085629889
Directory	/workspace/11.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/11.sram_ctrl_lc_escalation.1700281877
Short name	T366
Test name
Test status
Simulation time	923741966 ps
CPU time	1.72 seconds
Started	Jun 29 06:54:20 PM PDT 24
Finished	Jun 29 06:54:23 PM PDT 24
Peak memory	213876 kb
Host	smart-96bfcdf3-4ed2-413b-8e9a-81bf0db36c5c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700281877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es calation.1700281877
Directory	/workspace/11.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/11.sram_ctrl_max_throughput.1516748104
Short name	T119
Test name
Test status
Simulation time	85669404 ps
CPU time	17.4 seconds
Started	Jun 29 06:54:31 PM PDT 24
Finished	Jun 29 06:54:49 PM PDT 24
Peak memory	268164 kb
Host	smart-e27ba479-ec5e-4f86-a6c3-7151cbfc680e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516748104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_max_throughput.1516748104
Directory	/workspace/11.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/11.sram_ctrl_mem_partial_access.1641907851
Short name	T85
Test name
Test status
Simulation time	500133902 ps
CPU time	3.1 seconds
Started	Jun 29 06:54:18 PM PDT 24
Finished	Jun 29 06:54:22 PM PDT 24
Peak memory	211068 kb
Host	smart-e5338223-24d5-4528-82f5-1dff8cb219e6
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641907851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_mem_partial_access.1641907851
Directory	/workspace/11.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/11.sram_ctrl_mem_walk.4069803672
Short name	T234
Test name
Test status
Simulation time	446819445 ps
CPU time	10.2 seconds
Started	Jun 29 06:54:20 PM PDT 24
Finished	Jun 29 06:54:31 PM PDT 24
Peak memory	202888 kb
Host	smart-ebaf3cc1-8f00-4b12-b3f3-80edeb3d4b9d
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069803672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr l_mem_walk.4069803672
Directory	/workspace/11.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/11.sram_ctrl_multiple_keys.3354829449
Short name	T445
Test name
Test status
Simulation time	17542011379 ps
CPU time	1361.29 seconds
Started	Jun 29 06:54:20 PM PDT 24
Finished	Jun 29 07:17:02 PM PDT 24
Peak memory	375504 kb
Host	smart-6f27f14b-344d-4912-83b5-08c97d292cb2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354829449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi ple_keys.3354829449
Directory	/workspace/11.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/11.sram_ctrl_partial_access.1723522817
Short name	T400
Test name
Test status
Simulation time	1332473736 ps
CPU time	99.63 seconds
Started	Jun 29 06:54:19 PM PDT 24
Finished	Jun 29 06:55:59 PM PDT 24
Peak memory	347740 kb
Host	smart-12ae0d7b-5162-4a24-af68-7ccca058d992
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723522817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11. sram_ctrl_partial_access.1723522817
Directory	/workspace/11.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1233409600
Short name	T777
Test name
Test status
Simulation time	8412329788 ps
CPU time	201.76 seconds
Started	Jun 29 06:54:20 PM PDT 24
Finished	Jun 29 06:57:43 PM PDT 24
Peak memory	202972 kb
Host	smart-23c07e61-a835-4124-9f7a-7570edc89c79
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233409600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_partial_access_b2b.1233409600
Directory	/workspace/11.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/11.sram_ctrl_ram_cfg.3683059101
Short name	T855
Test name
Test status
Simulation time	91470388 ps
CPU time	0.73 seconds
Started	Jun 29 06:54:18 PM PDT 24
Finished	Jun 29 06:54:20 PM PDT 24
Peak memory	202860 kb
Host	smart-a3a4e6b5-877c-44ed-bdc8-1523e0f8d0ab
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683059101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.3683059101
Directory	/workspace/11.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/11.sram_ctrl_regwen.773517465
Short name	T385
Test name
Test status
Simulation time	9439770914 ps
CPU time	808.66 seconds
Started	Jun 29 06:54:20 PM PDT 24
Finished	Jun 29 07:07:50 PM PDT 24
Peak memory	365504 kb
Host	smart-fd75e623-f031-4d28-9a16-4e30c028ded2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773517465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.773517465
Directory	/workspace/11.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/11.sram_ctrl_smoke.800851348
Short name	T118
Test name
Test status
Simulation time	438068564 ps
CPU time	13.53 seconds
Started	Jun 29 06:54:18 PM PDT 24
Finished	Jun 29 06:54:32 PM PDT 24
Peak memory	202828 kb
Host	smart-a93fb4b9-654d-430a-81b5-eb1bdc648a15
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800851348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.800851348
Directory	/workspace/11.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.sram_ctrl_stress_all.509301272
Short name	T150
Test name
Test status
Simulation time	8571512926 ps
CPU time	155.17 seconds
Started	Jun 29 06:54:20 PM PDT 24
Finished	Jun 29 06:56:56 PM PDT 24
Peak memory	249316 kb
Host	smart-78b06641-8d73-48b5-8d9f-5f909b27d0f9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509301272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_stress_all.509301272
Directory	/workspace/11.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/11.sram_ctrl_stress_pipeline.387570120
Short name	T494
Test name
Test status
Simulation time	2562398880 ps
CPU time	186.2 seconds
Started	Jun 29 06:54:21 PM PDT 24
Finished	Jun 29 06:57:28 PM PDT 24
Peak memory	202984 kb
Host	smart-21e9170c-00aa-42ea-8767-3df854dfbc32
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387570120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11 .sram_ctrl_stress_pipeline.387570120
Directory	/workspace/11.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.911911417
Short name	T927
Test name
Test status
Simulation time	278162322 ps
CPU time	7.06 seconds
Started	Jun 29 06:54:17 PM PDT 24
Finished	Jun 29 06:54:25 PM PDT 24
Peak memory	236940 kb
Host	smart-58ae6cfb-ef61-416f-a45b-59b50a9bce02
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911911417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_throughput_w_partial_write.911911417
Directory	/workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/12.sram_ctrl_access_during_key_req.2305319802
Short name	T313
Test name
Test status
Simulation time	3460427442 ps
CPU time	1355.13 seconds
Started	Jun 29 06:54:33 PM PDT 24
Finished	Jun 29 07:17:09 PM PDT 24
Peak memory	373708 kb
Host	smart-e7d31337-b6bd-4f09-9a01-327e4b21ec1c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305319802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_access_during_key_req.2305319802
Directory	/workspace/12.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/12.sram_ctrl_alert_test.3510073140
Short name	T815
Test name
Test status
Simulation time	14516297 ps
CPU time	0.68 seconds
Started	Jun 29 06:54:29 PM PDT 24
Finished	Jun 29 06:54:31 PM PDT 24
Peak memory	202668 kb
Host	smart-03157ca7-6766-426c-81f5-5a562e092ff7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510073140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.3510073140
Directory	/workspace/12.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.sram_ctrl_bijection.1131442511
Short name	T746
Test name
Test status
Simulation time	3897627134 ps
CPU time	68.04 seconds
Started	Jun 29 06:54:24 PM PDT 24
Finished	Jun 29 06:55:32 PM PDT 24
Peak memory	202956 kb
Host	smart-5b198ab4-7c63-47ce-b53c-fb0f238ab139
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131442511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection .1131442511
Directory	/workspace/12.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/12.sram_ctrl_executable.2096948256
Short name	T466
Test name
Test status
Simulation time	3742780375 ps
CPU time	1265.64 seconds
Started	Jun 29 06:54:37 PM PDT 24
Finished	Jun 29 07:15:43 PM PDT 24
Peak memory	373564 kb
Host	smart-d9d20b94-f491-40dd-94de-b31997021f4c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096948256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab le.2096948256
Directory	/workspace/12.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/12.sram_ctrl_lc_escalation.1155914658
Short name	T272
Test name
Test status
Simulation time	1021008206 ps
CPU time	6.27 seconds
Started	Jun 29 06:54:36 PM PDT 24
Finished	Jun 29 06:54:43 PM PDT 24
Peak memory	202760 kb
Host	smart-288e51f5-fac1-4377-944e-c31748019eea
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155914658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es calation.1155914658
Directory	/workspace/12.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/12.sram_ctrl_max_throughput.1261469193
Short name	T186
Test name
Test status
Simulation time	129697501 ps
CPU time	93.62 seconds
Started	Jun 29 06:54:19 PM PDT 24
Finished	Jun 29 06:55:53 PM PDT 24
Peak memory	350452 kb
Host	smart-cd67f697-07c1-4f56-bb60-2b58e356336d
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261469193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_max_throughput.1261469193
Directory	/workspace/12.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2054455359
Short name	T558
Test name
Test status
Simulation time	278568389 ps
CPU time	4.78 seconds
Started	Jun 29 06:54:37 PM PDT 24
Finished	Jun 29 06:54:42 PM PDT 24
Peak memory	211328 kb
Host	smart-af323b1a-15f3-4b48-ae50-9644bd64efa8
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054455359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_mem_partial_access.2054455359
Directory	/workspace/12.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/12.sram_ctrl_mem_walk.1014574711
Short name	T508
Test name
Test status
Simulation time	348784774 ps
CPU time	6.04 seconds
Started	Jun 29 06:54:32 PM PDT 24
Finished	Jun 29 06:54:39 PM PDT 24
Peak memory	202864 kb
Host	smart-d34142b1-b96f-40eb-8f88-1c22a2ad3dc5
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014574711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr l_mem_walk.1014574711
Directory	/workspace/12.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/12.sram_ctrl_multiple_keys.2385192763
Short name	T710
Test name
Test status
Simulation time	2326041238 ps
CPU time	1425.32 seconds
Started	Jun 29 06:54:20 PM PDT 24
Finished	Jun 29 07:18:06 PM PDT 24
Peak memory	374660 kb
Host	smart-527d3b6d-ab7e-49d5-854c-c99007f1cb14
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385192763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi ple_keys.2385192763
Directory	/workspace/12.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/12.sram_ctrl_partial_access.2377143318
Short name	T486
Test name
Test status
Simulation time	262694758 ps
CPU time	6.3 seconds
Started	Jun 29 06:54:19 PM PDT 24
Finished	Jun 29 06:54:26 PM PDT 24
Peak memory	229936 kb
Host	smart-94a44d04-caac-44b7-8ab6-3248dd3f3e44
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377143318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12. sram_ctrl_partial_access.2377143318
Directory	/workspace/12.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2970173197
Short name	T144
Test name
Test status
Simulation time	18675705755 ps
CPU time	493.93 seconds
Started	Jun 29 06:54:23 PM PDT 24
Finished	Jun 29 07:02:37 PM PDT 24
Peak memory	202912 kb
Host	smart-7d12be17-7f15-4b79-8b9c-de0d5e10a35c
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970173197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.sram_ctrl_partial_access_b2b.2970173197
Directory	/workspace/12.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/12.sram_ctrl_regwen.461544292
Short name	T149
Test name
Test status
Simulation time	9801457524 ps
CPU time	915.26 seconds
Started	Jun 29 06:54:29 PM PDT 24
Finished	Jun 29 07:09:45 PM PDT 24
Peak memory	369592 kb
Host	smart-d7394d89-7d7f-4d3d-8420-224edfd32e6f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461544292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.461544292
Directory	/workspace/12.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/12.sram_ctrl_smoke.3795482305
Short name	T331
Test name
Test status
Simulation time	312977624 ps
CPU time	6.59 seconds
Started	Jun 29 06:54:21 PM PDT 24
Finished	Jun 29 06:54:28 PM PDT 24
Peak memory	202796 kb
Host	smart-42f53c24-965d-4362-b049-832c33fea50d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795482305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.3795482305
Directory	/workspace/12.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.sram_ctrl_stress_all.1525712565
Short name	T341
Test name
Test status
Simulation time	207796497184 ps
CPU time	4263.83 seconds
Started	Jun 29 06:54:36 PM PDT 24
Finished	Jun 29 08:05:42 PM PDT 24
Peak memory	375276 kb
Host	smart-bd60c117-c004-4a3a-b491-d57b2d3fd4c2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525712565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 12.sram_ctrl_stress_all.1525712565
Directory	/workspace/12.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.424562077
Short name	T417
Test name
Test status
Simulation time	1583728608 ps
CPU time	9.23 seconds
Started	Jun 29 06:54:29 PM PDT 24
Finished	Jun 29 06:54:39 PM PDT 24
Peak memory	212428 kb
Host	smart-297df6e2-5432-49a6-a1a1-0234606c7b34
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=424562077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.424562077
Directory	/workspace/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.sram_ctrl_stress_pipeline.2608347476
Short name	T411
Test name
Test status
Simulation time	6189289030 ps
CPU time	244.16 seconds
Started	Jun 29 06:54:18 PM PDT 24
Finished	Jun 29 06:58:23 PM PDT 24
Peak memory	203004 kb
Host	smart-df92d1e3-d15d-46c6-b9f5-3c4229681d03
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608347476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_stress_pipeline.2608347476
Directory	/workspace/12.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2027807245
Short name	T244
Test name
Test status
Simulation time	167890977 ps
CPU time	1.19 seconds
Started	Jun 29 06:54:27 PM PDT 24
Finished	Jun 29 06:54:29 PM PDT 24
Peak memory	210788 kb
Host	smart-433e1e65-97bd-4a22-8957-041ec04a7671
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027807245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.2027807245
Directory	/workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/13.sram_ctrl_access_during_key_req.1866255565
Short name	T311
Test name
Test status
Simulation time	12227639687 ps
CPU time	705.29 seconds
Started	Jun 29 06:54:30 PM PDT 24
Finished	Jun 29 07:06:16 PM PDT 24
Peak memory	375756 kb
Host	smart-a9175c67-c7cd-49e5-9088-ca16419c87e6
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866255565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_access_during_key_req.1866255565
Directory	/workspace/13.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/13.sram_ctrl_alert_test.1900713911
Short name	T443
Test name
Test status
Simulation time	22349210 ps
CPU time	0.68 seconds
Started	Jun 29 06:54:29 PM PDT 24
Finished	Jun 29 06:54:30 PM PDT 24
Peak memory	202636 kb
Host	smart-f87d0551-2c27-430c-b5bb-6001c07fb9fd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900713911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.1900713911
Directory	/workspace/13.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.sram_ctrl_bijection.4014335881
Short name	T516
Test name
Test status
Simulation time	1196295116 ps
CPU time	17.62 seconds
Started	Jun 29 06:54:31 PM PDT 24
Finished	Jun 29 06:54:49 PM PDT 24
Peak memory	202828 kb
Host	smart-64d23ab9-28f6-4c58-9951-7210b1c5f78c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014335881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection .4014335881
Directory	/workspace/13.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/13.sram_ctrl_executable.1124466654
Short name	T913
Test name
Test status
Simulation time	12243286055 ps
CPU time	654.07 seconds
Started	Jun 29 06:54:34 PM PDT 24
Finished	Jun 29 07:05:28 PM PDT 24
Peak memory	373668 kb
Host	smart-835b7361-1cca-4314-84cf-f0bdde7285d6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124466654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab le.1124466654
Directory	/workspace/13.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/13.sram_ctrl_lc_escalation.828530671
Short name	T365
Test name
Test status
Simulation time	625576963 ps
CPU time	6.96 seconds
Started	Jun 29 06:54:34 PM PDT 24
Finished	Jun 29 06:54:42 PM PDT 24
Peak memory	202784 kb
Host	smart-a4cd63b0-6651-4c86-9403-8a78edd1a863
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828530671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_esc alation.828530671
Directory	/workspace/13.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/13.sram_ctrl_max_throughput.2141841292
Short name	T578
Test name
Test status
Simulation time	269017514 ps
CPU time	13.17 seconds
Started	Jun 29 06:54:33 PM PDT 24
Finished	Jun 29 06:54:47 PM PDT 24
Peak memory	251916 kb
Host	smart-d40cdfb0-4762-4721-989d-31277f510894
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141841292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_max_throughput.2141841292
Directory	/workspace/13.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/13.sram_ctrl_mem_partial_access.1033050044
Short name	T561
Test name
Test status
Simulation time	84240977 ps
CPU time	2.93 seconds
Started	Jun 29 06:54:31 PM PDT 24
Finished	Jun 29 06:54:35 PM PDT 24
Peak memory	211088 kb
Host	smart-4e7746b0-eb6d-488e-a997-fd9fec8302e3
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033050044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_mem_partial_access.1033050044
Directory	/workspace/13.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/13.sram_ctrl_mem_walk.3795445859
Short name	T648
Test name
Test status
Simulation time	292374341 ps
CPU time	4.72 seconds
Started	Jun 29 06:54:30 PM PDT 24
Finished	Jun 29 06:54:36 PM PDT 24
Peak memory	211116 kb
Host	smart-1bb753b8-4a32-47f0-8fd3-2d3224b63bfb
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795445859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr l_mem_walk.3795445859
Directory	/workspace/13.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/13.sram_ctrl_multiple_keys.1392176219
Short name	T368
Test name
Test status
Simulation time	3692144759 ps
CPU time	18.89 seconds
Started	Jun 29 06:54:28 PM PDT 24
Finished	Jun 29 06:54:48 PM PDT 24
Peak memory	208772 kb
Host	smart-4e9dae14-db92-4164-b006-cbebdbd19c64
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392176219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi ple_keys.1392176219
Directory	/workspace/13.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/13.sram_ctrl_partial_access.3675881386
Short name	T172
Test name
Test status
Simulation time	721746345 ps
CPU time	15.38 seconds
Started	Jun 29 06:54:33 PM PDT 24
Finished	Jun 29 06:54:49 PM PDT 24
Peak memory	202808 kb
Host	smart-8efcc44c-2b28-445e-8975-fec3a8387023
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675881386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. sram_ctrl_partial_access.3675881386
Directory	/workspace/13.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.99848175
Short name	T906
Test name
Test status
Simulation time	4630454385 ps
CPU time	349.57 seconds
Started	Jun 29 06:54:31 PM PDT 24
Finished	Jun 29 07:00:21 PM PDT 24
Peak memory	202924 kb
Host	smart-97c2b1cf-b0cf-4286-b261-3de4ab0f13ba
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99848175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_partial_access_b2b.99848175
Directory	/workspace/13.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/13.sram_ctrl_ram_cfg.1007468833
Short name	T902
Test name
Test status
Simulation time	27205964 ps
CPU time	0.79 seconds
Started	Jun 29 06:54:29 PM PDT 24
Finished	Jun 29 06:54:30 PM PDT 24
Peak memory	202880 kb
Host	smart-f3e80883-e453-4999-b23e-0448c045b396
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007468833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.1007468833
Directory	/workspace/13.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/13.sram_ctrl_regwen.3463259118
Short name	T62
Test name
Test status
Simulation time	166635078318 ps
CPU time	1914.39 seconds
Started	Jun 29 06:54:30 PM PDT 24
Finished	Jun 29 07:26:25 PM PDT 24
Peak memory	371712 kb
Host	smart-d09a412c-048c-476e-bf1b-3e893c04dfd4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463259118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.3463259118
Directory	/workspace/13.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/13.sram_ctrl_smoke.1338626289
Short name	T641
Test name
Test status
Simulation time	111453649 ps
CPU time	1.46 seconds
Started	Jun 29 06:54:28 PM PDT 24
Finished	Jun 29 06:54:30 PM PDT 24
Peak memory	202824 kb
Host	smart-a1ca1b58-d9c6-4313-8070-2b22d3c727d8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338626289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.1338626289
Directory	/workspace/13.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.sram_ctrl_stress_all.146513278
Short name	T364
Test name
Test status
Simulation time	7266358118 ps
CPU time	2084.01 seconds
Started	Jun 29 06:54:32 PM PDT 24
Finished	Jun 29 07:29:16 PM PDT 24
Peak memory	375964 kb
Host	smart-6ef6ab80-67c5-4420-b8ec-7cab568bd178
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146513278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 13.sram_ctrl_stress_all.146513278
Directory	/workspace/13.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/13.sram_ctrl_stress_pipeline.1465431796
Short name	T95
Test name
Test status
Simulation time	3746855597 ps
CPU time	168.41 seconds
Started	Jun 29 06:54:33 PM PDT 24
Finished	Jun 29 06:57:22 PM PDT 24
Peak memory	202952 kb
Host	smart-3a63dead-874f-4633-b0f5-fccf8a2721a3
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465431796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_stress_pipeline.1465431796
Directory	/workspace/13.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.2108515757
Short name	T219
Test name
Test status
Simulation time	567772668 ps
CPU time	103.16 seconds
Started	Jun 29 06:54:27 PM PDT 24
Finished	Jun 29 06:56:10 PM PDT 24
Peak memory	353600 kb
Host	smart-9d534d39-2665-4980-9b5f-770a99b10b24
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108515757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.2108515757
Directory	/workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/14.sram_ctrl_access_during_key_req.3897412899
Short name	T355
Test name
Test status
Simulation time	1940430976 ps
CPU time	816.94 seconds
Started	Jun 29 06:54:28 PM PDT 24
Finished	Jun 29 07:08:05 PM PDT 24
Peak memory	373404 kb
Host	smart-9a658486-c9cd-42de-8be9-8045ba59e3b1
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897412899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_access_during_key_req.3897412899
Directory	/workspace/14.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/14.sram_ctrl_alert_test.1908879580
Short name	T722
Test name
Test status
Simulation time	37165196 ps
CPU time	0.65 seconds
Started	Jun 29 06:54:31 PM PDT 24
Finished	Jun 29 06:54:32 PM PDT 24
Peak memory	202236 kb
Host	smart-ebd0d916-5492-4dcc-ae63-450d9fb4048e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908879580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.1908879580
Directory	/workspace/14.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.sram_ctrl_bijection.2452794204
Short name	T579
Test name
Test status
Simulation time	66290429334 ps
CPU time	87.68 seconds
Started	Jun 29 06:54:33 PM PDT 24
Finished	Jun 29 06:56:01 PM PDT 24
Peak memory	202940 kb
Host	smart-b614f9db-ca3b-470e-94e1-5ca9bc3010dd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452794204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection .2452794204
Directory	/workspace/14.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/14.sram_ctrl_executable.2091658403
Short name	T291
Test name
Test status
Simulation time	39555098321 ps
CPU time	1929.41 seconds
Started	Jun 29 06:54:27 PM PDT 24
Finished	Jun 29 07:26:37 PM PDT 24
Peak memory	374684 kb
Host	smart-c39e02c7-9eb6-43bd-8512-db8b60bd7370
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091658403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab le.2091658403
Directory	/workspace/14.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/14.sram_ctrl_lc_escalation.1542688563
Short name	T816
Test name
Test status
Simulation time	2685640104 ps
CPU time	8.85 seconds
Started	Jun 29 06:54:37 PM PDT 24
Finished	Jun 29 06:54:46 PM PDT 24
Peak memory	202860 kb
Host	smart-8be0c66d-aa92-4fb0-bb52-3ff5845aca88
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542688563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es calation.1542688563
Directory	/workspace/14.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/14.sram_ctrl_max_throughput.711674111
Short name	T301
Test name
Test status
Simulation time	420857178 ps
CPU time	50.71 seconds
Started	Jun 29 06:54:30 PM PDT 24
Finished	Jun 29 06:55:21 PM PDT 24
Peak memory	331528 kb
Host	smart-6295c622-2784-43a6-9fa9-e591979e4b39
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711674111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 14.sram_ctrl_max_throughput.711674111
Directory	/workspace/14.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/14.sram_ctrl_mem_partial_access.78711362
Short name	T434
Test name
Test status
Simulation time	251057831 ps
CPU time	3.16 seconds
Started	Jun 29 06:54:33 PM PDT 24
Finished	Jun 29 06:54:36 PM PDT 24
Peak memory	211096 kb
Host	smart-bec3aff5-a002-4b05-a81b-36fab91be19e
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78711362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14. sram_ctrl_mem_partial_access.78711362
Directory	/workspace/14.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/14.sram_ctrl_mem_walk.3061933809
Short name	T589
Test name
Test status
Simulation time	557570936 ps
CPU time	8.69 seconds
Started	Jun 29 06:54:29 PM PDT 24
Finished	Jun 29 06:54:38 PM PDT 24
Peak memory	211100 kb
Host	smart-f454cfd9-bc25-40cb-ac18-1a6b3f443e02
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061933809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr l_mem_walk.3061933809
Directory	/workspace/14.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/14.sram_ctrl_multiple_keys.276348945
Short name	T348
Test name
Test status
Simulation time	4909021105 ps
CPU time	511 seconds
Started	Jun 29 06:54:30 PM PDT 24
Finished	Jun 29 07:03:01 PM PDT 24
Peak memory	374676 kb
Host	smart-081849e0-b0b6-4ad8-8ebf-b275c2fd05d3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276348945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multip le_keys.276348945
Directory	/workspace/14.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/14.sram_ctrl_partial_access.448296411
Short name	T871
Test name
Test status
Simulation time	3495313921 ps
CPU time	39.21 seconds
Started	Jun 29 06:54:37 PM PDT 24
Finished	Jun 29 06:55:18 PM PDT 24
Peak memory	295972 kb
Host	smart-b60e885e-3284-45dd-81c1-fa4d1c282d70
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448296411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.s ram_ctrl_partial_access.448296411
Directory	/workspace/14.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2748321517
Short name	T661
Test name
Test status
Simulation time	15992184894 ps
CPU time	410.83 seconds
Started	Jun 29 06:54:33 PM PDT 24
Finished	Jun 29 07:01:24 PM PDT 24
Peak memory	202916 kb
Host	smart-e6b71885-76a3-430b-9864-3d3b06f11749
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748321517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.sram_ctrl_partial_access_b2b.2748321517
Directory	/workspace/14.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/14.sram_ctrl_ram_cfg.285694384
Short name	T851
Test name
Test status
Simulation time	48162550 ps
CPU time	0.77 seconds
Started	Jun 29 06:54:28 PM PDT 24
Finished	Jun 29 06:54:29 PM PDT 24
Peak memory	202832 kb
Host	smart-b954317c-7e61-4eba-9034-7f0be1c31d48
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285694384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.285694384
Directory	/workspace/14.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/14.sram_ctrl_regwen.2379598197
Short name	T281
Test name
Test status
Simulation time	14342889795 ps
CPU time	636.55 seconds
Started	Jun 29 06:54:29 PM PDT 24
Finished	Jun 29 07:05:06 PM PDT 24
Peak memory	375056 kb
Host	smart-b0798647-57c6-4cfd-9b71-2901d6095ed4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379598197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.2379598197
Directory	/workspace/14.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/14.sram_ctrl_smoke.1388127739
Short name	T288
Test name
Test status
Simulation time	3233303351 ps
CPU time	14.93 seconds
Started	Jun 29 06:54:36 PM PDT 24
Finished	Jun 29 06:54:52 PM PDT 24
Peak memory	202800 kb
Host	smart-bde1a69a-4aba-4655-a9c3-c3238f3f410c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388127739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.1388127739
Directory	/workspace/14.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.sram_ctrl_stress_all.4270293970
Short name	T571
Test name
Test status
Simulation time	27943039300 ps
CPU time	3164.85 seconds
Started	Jun 29 06:54:32 PM PDT 24
Finished	Jun 29 07:47:17 PM PDT 24
Peak memory	382564 kb
Host	smart-ac89b902-4621-43cd-85fd-968fcb7541e0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270293970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 14.sram_ctrl_stress_all.4270293970
Directory	/workspace/14.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/14.sram_ctrl_stress_pipeline.3401811360
Short name	T549
Test name
Test status
Simulation time	5154005160 ps
CPU time	222.41 seconds
Started	Jun 29 06:54:35 PM PDT 24
Finished	Jun 29 06:58:18 PM PDT 24
Peak memory	202940 kb
Host	smart-46b7beee-8386-47c0-9f4a-d017560acbbe
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401811360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_stress_pipeline.3401811360
Directory	/workspace/14.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1999601083
Short name	T601
Test name
Test status
Simulation time	145137773 ps
CPU time	22.91 seconds
Started	Jun 29 06:54:36 PM PDT 24
Finished	Jun 29 06:55:00 PM PDT 24
Peak memory	278012 kb
Host	smart-da585809-26f8-4ffe-8b8c-d00149ba34d8
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999601083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.1999601083
Directory	/workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/15.sram_ctrl_access_during_key_req.1718561963
Short name	T609
Test name
Test status
Simulation time	2881532942 ps
CPU time	849.02 seconds
Started	Jun 29 06:54:43 PM PDT 24
Finished	Jun 29 07:08:53 PM PDT 24
Peak memory	371632 kb
Host	smart-104ab287-808b-49aa-8320-62a45203316b
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718561963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_access_during_key_req.1718561963
Directory	/workspace/15.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/15.sram_ctrl_alert_test.687046250
Short name	T633
Test name
Test status
Simulation time	22432885 ps
CPU time	0.64 seconds
Started	Jun 29 06:54:38 PM PDT 24
Finished	Jun 29 06:54:39 PM PDT 24
Peak memory	202628 kb
Host	smart-7daf25e5-2133-4551-b2cb-3aaa65d19af7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687046250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.687046250
Directory	/workspace/15.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/15.sram_ctrl_bijection.2812690935
Short name	T886
Test name
Test status
Simulation time	4442450606 ps
CPU time	48.86 seconds
Started	Jun 29 06:54:35 PM PDT 24
Finished	Jun 29 06:55:25 PM PDT 24
Peak memory	202940 kb
Host	smart-2f43ee0f-ad9d-4505-9780-16c249adccc8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812690935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection .2812690935
Directory	/workspace/15.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/15.sram_ctrl_executable.2427993082
Short name	T338
Test name
Test status
Simulation time	5277612753 ps
CPU time	781.23 seconds
Started	Jun 29 06:54:40 PM PDT 24
Finished	Jun 29 07:07:42 PM PDT 24
Peak memory	368600 kb
Host	smart-d74909ad-a8e2-4bdc-a23e-c598e792fe05
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427993082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab le.2427993082
Directory	/workspace/15.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/15.sram_ctrl_lc_escalation.3033776730
Short name	T173
Test name
Test status
Simulation time	1371645535 ps
CPU time	6.24 seconds
Started	Jun 29 06:54:39 PM PDT 24
Finished	Jun 29 06:54:46 PM PDT 24
Peak memory	202820 kb
Host	smart-4a0eb648-8a2c-4786-8781-ddf5cec12cdb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033776730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es calation.3033776730
Directory	/workspace/15.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/15.sram_ctrl_max_throughput.2164763350
Short name	T322
Test name
Test status
Simulation time	149716034 ps
CPU time	92.59 seconds
Started	Jun 29 06:54:36 PM PDT 24
Finished	Jun 29 06:56:09 PM PDT 24
Peak memory	353796 kb
Host	smart-20b4ae69-211e-4af7-8dfe-755b08e91c1e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164763350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_max_throughput.2164763350
Directory	/workspace/15.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/15.sram_ctrl_mem_partial_access.2800244319
Short name	T56
Test name
Test status
Simulation time	707800594 ps
CPU time	3.54 seconds
Started	Jun 29 06:54:40 PM PDT 24
Finished	Jun 29 06:54:44 PM PDT 24
Peak memory	211108 kb
Host	smart-63106801-4fda-4fd3-a151-6b95448e1ead
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800244319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_mem_partial_access.2800244319
Directory	/workspace/15.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/15.sram_ctrl_mem_walk.311487123
Short name	T419
Test name
Test status
Simulation time	938099118 ps
CPU time	6 seconds
Started	Jun 29 06:54:38 PM PDT 24
Finished	Jun 29 06:54:45 PM PDT 24
Peak memory	211068 kb
Host	smart-44135ec1-71de-4f31-b8b2-267cae275998
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311487123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl _mem_walk.311487123
Directory	/workspace/15.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/15.sram_ctrl_multiple_keys.525565735
Short name	T783
Test name
Test status
Simulation time	10267993250 ps
CPU time	1311.41 seconds
Started	Jun 29 06:54:30 PM PDT 24
Finished	Jun 29 07:16:22 PM PDT 24
Peak memory	374616 kb
Host	smart-54501344-72f0-49e1-a79c-419a8ca859b4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525565735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multip le_keys.525565735
Directory	/workspace/15.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/15.sram_ctrl_partial_access.696854435
Short name	T487
Test name
Test status
Simulation time	2477264640 ps
CPU time	151.89 seconds
Started	Jun 29 06:54:37 PM PDT 24
Finished	Jun 29 06:57:09 PM PDT 24
Peak memory	368056 kb
Host	smart-a4cfddf7-b6f8-4597-a6ae-ae55e8000cc4
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696854435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.s ram_ctrl_partial_access.696854435
Directory	/workspace/15.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3663902813
Short name	T483
Test name
Test status
Simulation time	58822185110 ps
CPU time	416.17 seconds
Started	Jun 29 06:54:36 PM PDT 24
Finished	Jun 29 07:01:33 PM PDT 24
Peak memory	202904 kb
Host	smart-05ce9d6a-bdab-415e-9994-bebc476558b2
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663902813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 15.sram_ctrl_partial_access_b2b.3663902813
Directory	/workspace/15.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/15.sram_ctrl_ram_cfg.1115714752
Short name	T730
Test name
Test status
Simulation time	31214693 ps
CPU time	0.8 seconds
Started	Jun 29 06:54:36 PM PDT 24
Finished	Jun 29 06:54:37 PM PDT 24
Peak memory	202876 kb
Host	smart-ac4b42fd-7e42-4f95-ad0e-1246045f8eb7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115714752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.1115714752
Directory	/workspace/15.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/15.sram_ctrl_regwen.459323330
Short name	T524
Test name
Test status
Simulation time	2232051785 ps
CPU time	952.19 seconds
Started	Jun 29 06:54:41 PM PDT 24
Finished	Jun 29 07:10:34 PM PDT 24
Peak memory	374004 kb
Host	smart-e74ad199-e6c0-45c0-8d46-1367eab945c2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459323330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.459323330
Directory	/workspace/15.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/15.sram_ctrl_smoke.1670733154
Short name	T839
Test name
Test status
Simulation time	125814761 ps
CPU time	1.01 seconds
Started	Jun 29 06:54:36 PM PDT 24
Finished	Jun 29 06:54:38 PM PDT 24
Peak memory	202528 kb
Host	smart-732039b7-dd31-43a9-b144-19a7f2f42b01
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670733154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.1670733154
Directory	/workspace/15.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.sram_ctrl_stress_all.505689205
Short name	T581
Test name
Test status
Simulation time	49301152372 ps
CPU time	890.54 seconds
Started	Jun 29 06:54:35 PM PDT 24
Finished	Jun 29 07:09:26 PM PDT 24
Peak memory	376388 kb
Host	smart-a88c883e-ff1b-4fdc-94af-44b68c21feb1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505689205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 15.sram_ctrl_stress_all.505689205
Directory	/workspace/15.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3834412390
Short name	T694
Test name
Test status
Simulation time	10283232385 ps
CPU time	632.18 seconds
Started	Jun 29 06:54:35 PM PDT 24
Finished	Jun 29 07:05:07 PM PDT 24
Peak memory	379960 kb
Host	smart-13718224-313f-4ced-8fe2-201b658d2797
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3834412390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.3834412390
Directory	/workspace/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.sram_ctrl_stress_pipeline.2842932122
Short name	T874
Test name
Test status
Simulation time	5230101864 ps
CPU time	135.63 seconds
Started	Jun 29 06:54:37 PM PDT 24
Finished	Jun 29 06:56:54 PM PDT 24
Peak memory	202924 kb
Host	smart-bc5689c7-7855-4d83-bb84-2c2d8020db32
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842932122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_stress_pipeline.2842932122
Directory	/workspace/15.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.833432758
Short name	T872
Test name
Test status
Simulation time	43423123 ps
CPU time	1 seconds
Started	Jun 29 06:54:35 PM PDT 24
Finished	Jun 29 06:54:36 PM PDT 24
Peak memory	202616 kb
Host	smart-1089c659-020b-47b1-afa5-4992cdddf662
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833432758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_throughput_w_partial_write.833432758
Directory	/workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/16.sram_ctrl_access_during_key_req.610137577
Short name	T33
Test name
Test status
Simulation time	1945601108 ps
CPU time	419.84 seconds
Started	Jun 29 06:54:42 PM PDT 24
Finished	Jun 29 07:01:43 PM PDT 24
Peak memory	370160 kb
Host	smart-4b3b28d4-0d62-4be9-bb45-e0270763a26c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610137577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 16.sram_ctrl_access_during_key_req.610137577
Directory	/workspace/16.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/16.sram_ctrl_alert_test.4115256352
Short name	T418
Test name
Test status
Simulation time	22071910 ps
CPU time	0.66 seconds
Started	Jun 29 06:54:38 PM PDT 24
Finished	Jun 29 06:54:39 PM PDT 24
Peak memory	202648 kb
Host	smart-40d7794e-ff59-419d-a632-f5a51d7481e8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115256352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.4115256352
Directory	/workspace/16.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/16.sram_ctrl_bijection.1737946727
Short name	T776
Test name
Test status
Simulation time	5205583590 ps
CPU time	55.98 seconds
Started	Jun 29 06:54:37 PM PDT 24
Finished	Jun 29 06:55:34 PM PDT 24
Peak memory	202908 kb
Host	smart-a0c816ce-9cc2-483d-b174-6ca39432ec26
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737946727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection .1737946727
Directory	/workspace/16.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/16.sram_ctrl_executable.3232094215
Short name	T711
Test name
Test status
Simulation time	7396901405 ps
CPU time	330.68 seconds
Started	Jun 29 06:54:36 PM PDT 24
Finished	Jun 29 07:00:07 PM PDT 24
Peak memory	350432 kb
Host	smart-1c20c5ba-0c92-46c3-ab1e-9d88daf5bc1c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232094215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab le.3232094215
Directory	/workspace/16.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/16.sram_ctrl_lc_escalation.2652916883
Short name	T229
Test name
Test status
Simulation time	2723323598 ps
CPU time	8.2 seconds
Started	Jun 29 06:54:38 PM PDT 24
Finished	Jun 29 06:54:47 PM PDT 24
Peak memory	203000 kb
Host	smart-d361b566-059b-47b4-a408-a65e7a61b15a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652916883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es calation.2652916883
Directory	/workspace/16.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/16.sram_ctrl_max_throughput.2426294428
Short name	T734
Test name
Test status
Simulation time	80474016 ps
CPU time	22.65 seconds
Started	Jun 29 06:54:38 PM PDT 24
Finished	Jun 29 06:55:02 PM PDT 24
Peak memory	272316 kb
Host	smart-99698af7-501a-41b6-bf6a-4f87bd82b04b
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426294428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_max_throughput.2426294428
Directory	/workspace/16.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/16.sram_ctrl_mem_partial_access.222559704
Short name	T424
Test name
Test status
Simulation time	341988359 ps
CPU time	3.27 seconds
Started	Jun 29 06:54:36 PM PDT 24
Finished	Jun 29 06:54:41 PM PDT 24
Peak memory	211080 kb
Host	smart-a450456f-a17d-4918-a437-70e3698054b6
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222559704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16 .sram_ctrl_mem_partial_access.222559704
Directory	/workspace/16.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/16.sram_ctrl_mem_walk.1349923677
Short name	T802
Test name
Test status
Simulation time	2304370344 ps
CPU time	11.24 seconds
Started	Jun 29 06:54:38 PM PDT 24
Finished	Jun 29 06:54:50 PM PDT 24
Peak memory	211168 kb
Host	smart-5493e19b-3bed-48de-a7bc-e2ed48fc002b
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349923677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr l_mem_walk.1349923677
Directory	/workspace/16.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/16.sram_ctrl_multiple_keys.3676662817
Short name	T532
Test name
Test status
Simulation time	8910808036 ps
CPU time	1340.41 seconds
Started	Jun 29 06:54:38 PM PDT 24
Finished	Jun 29 07:17:00 PM PDT 24
Peak memory	371164 kb
Host	smart-c2948d67-bb43-4cd2-9e08-a493a426d7f1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676662817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi ple_keys.3676662817
Directory	/workspace/16.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/16.sram_ctrl_partial_access.222228339
Short name	T375
Test name
Test status
Simulation time	425391735 ps
CPU time	32.04 seconds
Started	Jun 29 06:54:39 PM PDT 24
Finished	Jun 29 06:55:12 PM PDT 24
Peak memory	293564 kb
Host	smart-863f3bbb-e36b-492f-9268-177e39d54071
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222228339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.s ram_ctrl_partial_access.222228339
Directory	/workspace/16.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.2869076142
Short name	T255
Test name
Test status
Simulation time	20814673001 ps
CPU time	537.47 seconds
Started	Jun 29 06:54:42 PM PDT 24
Finished	Jun 29 07:03:41 PM PDT 24
Peak memory	202940 kb
Host	smart-e15d1907-f5a5-4cdd-8770-ede83723137c
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869076142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 16.sram_ctrl_partial_access_b2b.2869076142
Directory	/workspace/16.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/16.sram_ctrl_ram_cfg.2400612549
Short name	T425
Test name
Test status
Simulation time	48506683 ps
CPU time	0.79 seconds
Started	Jun 29 06:54:38 PM PDT 24
Finished	Jun 29 06:54:40 PM PDT 24
Peak memory	202876 kb
Host	smart-f4cc763e-555b-42a8-9d7b-1c085b94c9d7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400612549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.2400612549
Directory	/workspace/16.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/16.sram_ctrl_regwen.3701239358
Short name	T718
Test name
Test status
Simulation time	16054343461 ps
CPU time	893.05 seconds
Started	Jun 29 06:54:38 PM PDT 24
Finished	Jun 29 07:09:32 PM PDT 24
Peak memory	371572 kb
Host	smart-e661d9b6-2140-4a84-91d5-d709044fa213
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701239358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.3701239358
Directory	/workspace/16.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/16.sram_ctrl_smoke.2213302679
Short name	T319
Test name
Test status
Simulation time	65223555 ps
CPU time	1.22 seconds
Started	Jun 29 06:54:39 PM PDT 24
Finished	Jun 29 06:54:41 PM PDT 24
Peak memory	202628 kb
Host	smart-f2329fbd-31f9-4c0f-88c3-70dedb90a6bc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213302679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.2213302679
Directory	/workspace/16.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.sram_ctrl_stress_all.1044254996
Short name	T919
Test name
Test status
Simulation time	22407830639 ps
CPU time	1725.27 seconds
Started	Jun 29 06:54:39 PM PDT 24
Finished	Jun 29 07:23:25 PM PDT 24
Peak memory	377864 kb
Host	smart-9510bd5c-fa20-497a-ac35-d8b95fc62003
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044254996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 16.sram_ctrl_stress_all.1044254996
Directory	/workspace/16.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.336822352
Short name	T377
Test name
Test status
Simulation time	2735260291 ps
CPU time	234.21 seconds
Started	Jun 29 06:54:35 PM PDT 24
Finished	Jun 29 06:58:29 PM PDT 24
Peak memory	375496 kb
Host	smart-d6435c7e-cbf1-465c-a02c-1ec602913cf5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=336822352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.336822352
Directory	/workspace/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.sram_ctrl_stress_pipeline.3411663875
Short name	T933
Test name
Test status
Simulation time	3515747157 ps
CPU time	181.26 seconds
Started	Jun 29 06:54:37 PM PDT 24
Finished	Jun 29 06:57:40 PM PDT 24
Peak memory	202944 kb
Host	smart-a94d4e00-5937-4b88-860a-477937ee4ffc
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411663875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_stress_pipeline.3411663875
Directory	/workspace/16.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2655642638
Short name	T192
Test name
Test status
Simulation time	143221875 ps
CPU time	12.2 seconds
Started	Jun 29 06:54:36 PM PDT 24
Finished	Jun 29 06:54:49 PM PDT 24
Peak memory	251896 kb
Host	smart-6ec717f5-fad1-4570-92f7-3450a987a03e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655642638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.2655642638
Directory	/workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/17.sram_ctrl_access_during_key_req.417001695
Short name	T444
Test name
Test status
Simulation time	25180536004 ps
CPU time	967.14 seconds
Started	Jun 29 06:54:35 PM PDT 24
Finished	Jun 29 07:10:43 PM PDT 24
Peak memory	376676 kb
Host	smart-ade6c093-9716-4ed9-8b4c-5935391da917
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417001695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 17.sram_ctrl_access_during_key_req.417001695
Directory	/workspace/17.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/17.sram_ctrl_alert_test.1176982763
Short name	T863
Test name
Test status
Simulation time	34818632 ps
CPU time	0.68 seconds
Started	Jun 29 06:54:42 PM PDT 24
Finished	Jun 29 06:54:43 PM PDT 24
Peak memory	202636 kb
Host	smart-c2f995dc-d1a6-4d11-9399-3dbe36fa083e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176982763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.1176982763
Directory	/workspace/17.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.sram_ctrl_bijection.3624699990
Short name	T738
Test name
Test status
Simulation time	426915233 ps
CPU time	26.59 seconds
Started	Jun 29 06:54:39 PM PDT 24
Finished	Jun 29 06:55:07 PM PDT 24
Peak memory	202700 kb
Host	smart-fc9ac109-d7b7-4574-bf8b-fd2e9c63639e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624699990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection .3624699990
Directory	/workspace/17.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/17.sram_ctrl_executable.1210103036
Short name	T830
Test name
Test status
Simulation time	36926483626 ps
CPU time	438.18 seconds
Started	Jun 29 06:54:38 PM PDT 24
Finished	Jun 29 07:01:57 PM PDT 24
Peak memory	314184 kb
Host	smart-2054bf86-1880-4244-ae33-56b81f127a7b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210103036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab le.1210103036
Directory	/workspace/17.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/17.sram_ctrl_lc_escalation.1283646763
Short name	T185
Test name
Test status
Simulation time	306881627 ps
CPU time	4.28 seconds
Started	Jun 29 06:54:40 PM PDT 24
Finished	Jun 29 06:54:45 PM PDT 24
Peak memory	202808 kb
Host	smart-d54c8a8c-a282-4b6c-853d-ae3fa3963040
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283646763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es calation.1283646763
Directory	/workspace/17.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/17.sram_ctrl_max_throughput.544282899
Short name	T747
Test name
Test status
Simulation time	139925640 ps
CPU time	150.77 seconds
Started	Jun 29 06:54:35 PM PDT 24
Finished	Jun 29 06:57:07 PM PDT 24
Peak memory	369236 kb
Host	smart-3325b237-f990-42e1-b18c-4df5e61d3121
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544282899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.sram_ctrl_max_throughput.544282899
Directory	/workspace/17.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/17.sram_ctrl_mem_partial_access.600608699
Short name	T755
Test name
Test status
Simulation time	170207801 ps
CPU time	5.43 seconds
Started	Jun 29 06:54:37 PM PDT 24
Finished	Jun 29 06:54:43 PM PDT 24
Peak memory	211044 kb
Host	smart-63be2cb8-bfd1-4135-855c-9d4eb3144197
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600608699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17 .sram_ctrl_mem_partial_access.600608699
Directory	/workspace/17.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/17.sram_ctrl_mem_walk.2789705716
Short name	T848
Test name
Test status
Simulation time	1024247088 ps
CPU time	6.27 seconds
Started	Jun 29 06:54:39 PM PDT 24
Finished	Jun 29 06:54:46 PM PDT 24
Peak memory	202952 kb
Host	smart-02b57329-f1f2-4585-b10c-13e189ee41c3
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789705716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr l_mem_walk.2789705716
Directory	/workspace/17.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/17.sram_ctrl_multiple_keys.2929505518
Short name	T451
Test name
Test status
Simulation time	40499054702 ps
CPU time	1040.74 seconds
Started	Jun 29 06:54:37 PM PDT 24
Finished	Jun 29 07:11:59 PM PDT 24
Peak memory	371016 kb
Host	smart-35e95f62-29b7-49b9-a1a3-258384e778c3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929505518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi ple_keys.2929505518
Directory	/workspace/17.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/17.sram_ctrl_partial_access.2084010179
Short name	T193
Test name
Test status
Simulation time	1099416740 ps
CPU time	16 seconds
Started	Jun 29 06:54:37 PM PDT 24
Finished	Jun 29 06:54:54 PM PDT 24
Peak memory	202772 kb
Host	smart-624d306c-7d19-416c-ae62-d392b7690c38
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084010179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17. sram_ctrl_partial_access.2084010179
Directory	/workspace/17.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1053151583
Short name	T621
Test name
Test status
Simulation time	3820916395 ps
CPU time	273.12 seconds
Started	Jun 29 06:54:43 PM PDT 24
Finished	Jun 29 06:59:16 PM PDT 24
Peak memory	202964 kb
Host	smart-6ff64dbc-e607-425c-9b95-7fdb70412e65
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053151583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 17.sram_ctrl_partial_access_b2b.1053151583
Directory	/workspace/17.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/17.sram_ctrl_ram_cfg.491124234
Short name	T324
Test name
Test status
Simulation time	86387424 ps
CPU time	0.77 seconds
Started	Jun 29 06:54:39 PM PDT 24
Finished	Jun 29 06:54:40 PM PDT 24
Peak memory	202804 kb
Host	smart-13fdb491-538e-40c5-946b-2c23950e5b92
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491124234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.491124234
Directory	/workspace/17.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/17.sram_ctrl_regwen.4086262989
Short name	T387
Test name
Test status
Simulation time	31110663667 ps
CPU time	85.26 seconds
Started	Jun 29 06:54:37 PM PDT 24
Finished	Jun 29 06:56:03 PM PDT 24
Peak memory	268896 kb
Host	smart-2e0bd036-35e8-46ae-bc0b-fe21afe98ad9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086262989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.4086262989
Directory	/workspace/17.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/17.sram_ctrl_smoke.1825080795
Short name	T938
Test name
Test status
Simulation time	1290735375 ps
CPU time	160.05 seconds
Started	Jun 29 06:54:35 PM PDT 24
Finished	Jun 29 06:57:15 PM PDT 24
Peak memory	366884 kb
Host	smart-8d665257-1753-4a64-98fc-0a96d5cc94fc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825080795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.1825080795
Directory	/workspace/17.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.sram_ctrl_stress_all.3540394043
Short name	T780
Test name
Test status
Simulation time	9617638640 ps
CPU time	5119.13 seconds
Started	Jun 29 06:54:41 PM PDT 24
Finished	Jun 29 08:20:01 PM PDT 24
Peak memory	382912 kb
Host	smart-4116a233-78a8-4ac7-a390-aef8b34c8d15
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540394043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 17.sram_ctrl_stress_all.3540394043
Directory	/workspace/17.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1852140524
Short name	T54
Test name
Test status
Simulation time	2817754665 ps
CPU time	424.26 seconds
Started	Jun 29 06:54:35 PM PDT 24
Finished	Jun 29 07:01:40 PM PDT 24
Peak memory	355808 kb
Host	smart-30c1e77a-a0e0-455e-a566-ee2c1c68f1e8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1852140524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.1852140524
Directory	/workspace/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.sram_ctrl_stress_pipeline.1066011815
Short name	T636
Test name
Test status
Simulation time	6594371759 ps
CPU time	302.82 seconds
Started	Jun 29 06:54:38 PM PDT 24
Finished	Jun 29 06:59:42 PM PDT 24
Peak memory	202960 kb
Host	smart-305fea52-df39-4549-9c24-70527e0784c6
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066011815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_stress_pipeline.1066011815
Directory	/workspace/17.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2691674470
Short name	T357
Test name
Test status
Simulation time	306083780 ps
CPU time	140.6 seconds
Started	Jun 29 06:54:39 PM PDT 24
Finished	Jun 29 06:57:00 PM PDT 24
Peak memory	369424 kb
Host	smart-9ae02bfc-38ca-45c1-af38-b7541cd48fed
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691674470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.2691674470
Directory	/workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/18.sram_ctrl_access_during_key_req.1668419207
Short name	T437
Test name
Test status
Simulation time	2138396921 ps
CPU time	763.8 seconds
Started	Jun 29 06:54:49 PM PDT 24
Finished	Jun 29 07:07:33 PM PDT 24
Peak memory	374260 kb
Host	smart-2d8ddfcc-0de9-42ce-9800-bd0c5ee48d76
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668419207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_access_during_key_req.1668419207
Directory	/workspace/18.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/18.sram_ctrl_alert_test.1324158671
Short name	T123
Test name
Test status
Simulation time	11888650 ps
CPU time	0.65 seconds
Started	Jun 29 06:54:47 PM PDT 24
Finished	Jun 29 06:54:48 PM PDT 24
Peak memory	202668 kb
Host	smart-97f8e780-24a5-4903-906d-a58e43d30b27
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324158671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.1324158671
Directory	/workspace/18.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.sram_ctrl_bijection.3990385940
Short name	T210
Test name
Test status
Simulation time	4469341212 ps
CPU time	72.4 seconds
Started	Jun 29 06:54:38 PM PDT 24
Finished	Jun 29 06:55:51 PM PDT 24
Peak memory	202952 kb
Host	smart-296759ce-a5dc-44d0-a6e4-ef1d0ea04100
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990385940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection .3990385940
Directory	/workspace/18.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/18.sram_ctrl_executable.2388201354
Short name	T687
Test name
Test status
Simulation time	5147430936 ps
CPU time	660.46 seconds
Started	Jun 29 06:54:46 PM PDT 24
Finished	Jun 29 07:05:47 PM PDT 24
Peak memory	375752 kb
Host	smart-7cd5f0f2-53f5-4ca5-bc81-a6c15ebcf133
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388201354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab le.2388201354
Directory	/workspace/18.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/18.sram_ctrl_lc_escalation.2528611118
Short name	T237
Test name
Test status
Simulation time	1679829008 ps
CPU time	4.32 seconds
Started	Jun 29 06:54:47 PM PDT 24
Finished	Jun 29 06:54:51 PM PDT 24
Peak memory	211032 kb
Host	smart-cf1ddf1e-1919-487e-b669-65adcde1b44e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528611118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es calation.2528611118
Directory	/workspace/18.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/18.sram_ctrl_max_throughput.3631423114
Short name	T893
Test name
Test status
Simulation time	511614447 ps
CPU time	27.9 seconds
Started	Jun 29 06:54:40 PM PDT 24
Finished	Jun 29 06:55:08 PM PDT 24
Peak memory	284576 kb
Host	smart-354e6df8-71b5-40c6-80d9-ff0bc0b1942a
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631423114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_max_throughput.3631423114
Directory	/workspace/18.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/18.sram_ctrl_mem_partial_access.2359108394
Short name	T873
Test name
Test status
Simulation time	537607256 ps
CPU time	2.98 seconds
Started	Jun 29 06:54:44 PM PDT 24
Finished	Jun 29 06:54:48 PM PDT 24
Peak memory	210996 kb
Host	smart-607fbb0c-6e8e-4d98-926e-8e83eee89ec8
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359108394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_mem_partial_access.2359108394
Directory	/workspace/18.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/18.sram_ctrl_mem_walk.3288484056
Short name	T492
Test name
Test status
Simulation time	228174513 ps
CPU time	5.49 seconds
Started	Jun 29 06:54:46 PM PDT 24
Finished	Jun 29 06:54:52 PM PDT 24
Peak memory	211084 kb
Host	smart-96f63379-812e-47a1-affc-1cdb0cfb3003
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288484056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr l_mem_walk.3288484056
Directory	/workspace/18.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/18.sram_ctrl_multiple_keys.2018834090
Short name	T808
Test name
Test status
Simulation time	821747120 ps
CPU time	243.72 seconds
Started	Jun 29 06:54:41 PM PDT 24
Finished	Jun 29 06:58:45 PM PDT 24
Peak memory	363860 kb
Host	smart-c414a1fb-c3b1-464d-8c9b-2740c4783b46
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018834090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi ple_keys.2018834090
Directory	/workspace/18.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/18.sram_ctrl_partial_access.3832267234
Short name	T403
Test name
Test status
Simulation time	1360461905 ps
CPU time	12.45 seconds
Started	Jun 29 06:54:38 PM PDT 24
Finished	Jun 29 06:54:52 PM PDT 24
Peak memory	202820 kb
Host	smart-c71c9fd1-3704-4258-bc2a-9e5b81def603
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832267234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. sram_ctrl_partial_access.3832267234
Directory	/workspace/18.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3373552632
Short name	T926
Test name
Test status
Simulation time	21209807713 ps
CPU time	385.92 seconds
Started	Jun 29 06:54:38 PM PDT 24
Finished	Jun 29 07:01:05 PM PDT 24
Peak memory	202840 kb
Host	smart-eb03a326-db1f-4a02-bbb9-c8faa45b211f
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373552632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 18.sram_ctrl_partial_access_b2b.3373552632
Directory	/workspace/18.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/18.sram_ctrl_ram_cfg.2169918522
Short name	T463
Test name
Test status
Simulation time	83215584 ps
CPU time	0.75 seconds
Started	Jun 29 06:54:46 PM PDT 24
Finished	Jun 29 06:54:47 PM PDT 24
Peak memory	202844 kb
Host	smart-40889c4e-6f79-429c-bd59-f2b4b1d332a0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169918522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.2169918522
Directory	/workspace/18.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/18.sram_ctrl_regwen.3691001755
Short name	T736
Test name
Test status
Simulation time	6925414909 ps
CPU time	917.7 seconds
Started	Jun 29 06:54:44 PM PDT 24
Finished	Jun 29 07:10:02 PM PDT 24
Peak memory	369508 kb
Host	smart-13680e2e-23af-4bf8-9ff1-a3d9e493878d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691001755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.3691001755
Directory	/workspace/18.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/18.sram_ctrl_smoke.1998314698
Short name	T435
Test name
Test status
Simulation time	238277486 ps
CPU time	58.17 seconds
Started	Jun 29 06:54:39 PM PDT 24
Finished	Jun 29 06:55:38 PM PDT 24
Peak memory	324660 kb
Host	smart-5dfd3a0d-2160-4d61-a43a-605a5d1b11f6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998314698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.1998314698
Directory	/workspace/18.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.sram_ctrl_stress_all.1200989768
Short name	T762
Test name
Test status
Simulation time	34376877530 ps
CPU time	2689.93 seconds
Started	Jun 29 06:54:45 PM PDT 24
Finished	Jun 29 07:39:36 PM PDT 24
Peak memory	375168 kb
Host	smart-03dfdc87-6a0d-4fdc-b5fa-8ca4a6cf23c0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200989768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 18.sram_ctrl_stress_all.1200989768
Directory	/workspace/18.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.4147797742
Short name	T370
Test name
Test status
Simulation time	13368300821 ps
CPU time	192.7 seconds
Started	Jun 29 06:54:46 PM PDT 24
Finished	Jun 29 06:57:59 PM PDT 24
Peak memory	346216 kb
Host	smart-2b2312b1-c16c-430e-b3be-3bbfe7d744ef
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4147797742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.4147797742
Directory	/workspace/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.sram_ctrl_stress_pipeline.1171507674
Short name	T350
Test name
Test status
Simulation time	43726432626 ps
CPU time	302.11 seconds
Started	Jun 29 06:54:43 PM PDT 24
Finished	Jun 29 06:59:45 PM PDT 24
Peak memory	202940 kb
Host	smart-55f95f2c-255e-4ac5-84d0-31af7c0861fe
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171507674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_stress_pipeline.1171507674
Directory	/workspace/18.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.978953819
Short name	T928
Test name
Test status
Simulation time	534019148 ps
CPU time	111.33 seconds
Started	Jun 29 06:54:37 PM PDT 24
Finished	Jun 29 06:56:30 PM PDT 24
Peak memory	370288 kb
Host	smart-1cf5273b-e157-43db-918d-00c3d5b752b5
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978953819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_throughput_w_partial_write.978953819
Directory	/workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/19.sram_ctrl_access_during_key_req.3670644798
Short name	T449
Test name
Test status
Simulation time	1551092247 ps
CPU time	408.96 seconds
Started	Jun 29 06:54:48 PM PDT 24
Finished	Jun 29 07:01:38 PM PDT 24
Peak memory	375660 kb
Host	smart-18c91136-802a-4e87-92e6-357e6b245310
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670644798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_access_during_key_req.3670644798
Directory	/workspace/19.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/19.sram_ctrl_alert_test.916720326
Short name	T309
Test name
Test status
Simulation time	22570173 ps
CPU time	0.67 seconds
Started	Jun 29 06:54:48 PM PDT 24
Finished	Jun 29 06:54:49 PM PDT 24
Peak memory	202620 kb
Host	smart-e9324d91-c118-4b93-b844-2dc180f8050f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916720326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.916720326
Directory	/workspace/19.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.sram_ctrl_bijection.3332876436
Short name	T391
Test name
Test status
Simulation time	9044446437 ps
CPU time	35.97 seconds
Started	Jun 29 06:54:45 PM PDT 24
Finished	Jun 29 06:55:21 PM PDT 24
Peak memory	202916 kb
Host	smart-80c64ec1-e986-435f-b963-8541daca7e4c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332876436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection .3332876436
Directory	/workspace/19.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/19.sram_ctrl_executable.4257290122
Short name	T721
Test name
Test status
Simulation time	14511292278 ps
CPU time	279.45 seconds
Started	Jun 29 06:54:44 PM PDT 24
Finished	Jun 29 06:59:24 PM PDT 24
Peak memory	368552 kb
Host	smart-8dcec9ea-17da-4e25-82e0-ef4ad3aff062
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257290122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab le.4257290122
Directory	/workspace/19.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/19.sram_ctrl_lc_escalation.3682954265
Short name	T221
Test name
Test status
Simulation time	4055981644 ps
CPU time	5.01 seconds
Started	Jun 29 06:54:46 PM PDT 24
Finished	Jun 29 06:54:52 PM PDT 24
Peak memory	211120 kb
Host	smart-605c2c9f-c209-4a40-80df-fa32aef9356f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682954265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es calation.3682954265
Directory	/workspace/19.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/19.sram_ctrl_max_throughput.1557783703
Short name	T202
Test name
Test status
Simulation time	1570704929 ps
CPU time	42.3 seconds
Started	Jun 29 06:54:47 PM PDT 24
Finished	Jun 29 06:55:30 PM PDT 24
Peak memory	311064 kb
Host	smart-542761f2-34c8-4a67-bb46-9af0f544b15c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557783703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_max_throughput.1557783703
Directory	/workspace/19.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/19.sram_ctrl_mem_partial_access.1916103840
Short name	T82
Test name
Test status
Simulation time	125861705 ps
CPU time	4.87 seconds
Started	Jun 29 06:54:45 PM PDT 24
Finished	Jun 29 06:54:50 PM PDT 24
Peak memory	211096 kb
Host	smart-fde8a510-ef31-4237-bcf8-80cf4b7dac47
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916103840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_mem_partial_access.1916103840
Directory	/workspace/19.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/19.sram_ctrl_mem_walk.1785104728
Short name	T879
Test name
Test status
Simulation time	138062851 ps
CPU time	4.81 seconds
Started	Jun 29 06:54:50 PM PDT 24
Finished	Jun 29 06:54:55 PM PDT 24
Peak memory	211056 kb
Host	smart-984a99b6-1aff-4c81-9ec8-816ac6efc0ce
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785104728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr l_mem_walk.1785104728
Directory	/workspace/19.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/19.sram_ctrl_multiple_keys.2890288112
Short name	T544
Test name
Test status
Simulation time	16550446318 ps
CPU time	464.18 seconds
Started	Jun 29 06:54:51 PM PDT 24
Finished	Jun 29 07:02:35 PM PDT 24
Peak memory	371972 kb
Host	smart-b4e2dc65-a75c-4cd7-998a-f49e6406edfa
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890288112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi ple_keys.2890288112
Directory	/workspace/19.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/19.sram_ctrl_partial_access.3214188496
Short name	T713
Test name
Test status
Simulation time	403778900 ps
CPU time	47.09 seconds
Started	Jun 29 06:54:50 PM PDT 24
Finished	Jun 29 06:55:37 PM PDT 24
Peak memory	294136 kb
Host	smart-7c989f43-9a96-4333-9594-80ec92510168
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214188496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19. sram_ctrl_partial_access.3214188496
Directory	/workspace/19.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.2162231816
Short name	T887
Test name
Test status
Simulation time	1937014667 ps
CPU time	142.78 seconds
Started	Jun 29 06:54:45 PM PDT 24
Finished	Jun 29 06:57:08 PM PDT 24
Peak memory	202716 kb
Host	smart-d79eaf56-d729-40fd-8625-2f34b59d56fd
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162231816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.sram_ctrl_partial_access_b2b.2162231816
Directory	/workspace/19.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/19.sram_ctrl_ram_cfg.1139421551
Short name	T205
Test name
Test status
Simulation time	55465462 ps
CPU time	0.74 seconds
Started	Jun 29 06:54:47 PM PDT 24
Finished	Jun 29 06:54:48 PM PDT 24
Peak memory	202888 kb
Host	smart-c3e5a8b3-fe0c-411f-8a04-ad214f6f2d71
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139421551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.1139421551
Directory	/workspace/19.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/19.sram_ctrl_regwen.552572817
Short name	T904
Test name
Test status
Simulation time	2096135093 ps
CPU time	911.52 seconds
Started	Jun 29 06:54:46 PM PDT 24
Finished	Jun 29 07:09:58 PM PDT 24
Peak memory	374988 kb
Host	smart-71d705df-cff8-4062-8248-ab6cc5aeba52
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552572817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.552572817
Directory	/workspace/19.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/19.sram_ctrl_smoke.3804915530
Short name	T833
Test name
Test status
Simulation time	333299521 ps
CPU time	10 seconds
Started	Jun 29 06:54:46 PM PDT 24
Finished	Jun 29 06:54:57 PM PDT 24
Peak memory	202820 kb
Host	smart-9447fd9b-4425-4e9c-b4f0-47a8b94c64da
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804915530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.3804915530
Directory	/workspace/19.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.sram_ctrl_stress_all.3893145302
Short name	T846
Test name
Test status
Simulation time	87665243575 ps
CPU time	3028.76 seconds
Started	Jun 29 06:54:44 PM PDT 24
Finished	Jun 29 07:45:14 PM PDT 24
Peak memory	375668 kb
Host	smart-5eec85bc-4e49-4554-aa55-95aa5af357c5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893145302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 19.sram_ctrl_stress_all.3893145302
Directory	/workspace/19.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.698955721
Short name	T392
Test name
Test status
Simulation time	557410032 ps
CPU time	40.69 seconds
Started	Jun 29 06:54:49 PM PDT 24
Finished	Jun 29 06:55:30 PM PDT 24
Peak memory	219344 kb
Host	smart-44864cf5-636c-4f07-9bdd-ba263f7424ea
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=698955721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.698955721
Directory	/workspace/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.sram_ctrl_stress_pipeline.859310930
Short name	T104
Test name
Test status
Simulation time	17916614439 ps
CPU time	236.81 seconds
Started	Jun 29 06:54:45 PM PDT 24
Finished	Jun 29 06:58:43 PM PDT 24
Peak memory	202960 kb
Host	smart-e8fdeace-bf0c-43b3-a1b0-0e63fd804956
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859310930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19 .sram_ctrl_stress_pipeline.859310930
Directory	/workspace/19.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3439244726
Short name	T169
Test name
Test status
Simulation time	517129245 ps
CPU time	79.79 seconds
Started	Jun 29 06:54:45 PM PDT 24
Finished	Jun 29 06:56:06 PM PDT 24
Peak memory	347244 kb
Host	smart-4bbcfbdd-4560-4575-a4c2-8e440854eee6
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439244726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.3439244726
Directory	/workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/2.sram_ctrl_access_during_key_req.332897096
Short name	T582
Test name
Test status
Simulation time	2718648067 ps
CPU time	555.27 seconds
Started	Jun 29 06:53:55 PM PDT 24
Finished	Jun 29 07:03:11 PM PDT 24
Peak memory	367884 kb
Host	smart-2a8fdbeb-592b-465b-bd4a-3b698025084e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332897096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.sram_ctrl_access_during_key_req.332897096
Directory	/workspace/2.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/2.sram_ctrl_alert_test.4232037585
Short name	T759
Test name
Test status
Simulation time	50066940 ps
CPU time	0.72 seconds
Started	Jun 29 06:53:57 PM PDT 24
Finished	Jun 29 06:53:59 PM PDT 24
Peak memory	202660 kb
Host	smart-d1fe3e71-2600-4111-b727-85e6fa4a92e7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232037585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.4232037585
Directory	/workspace/2.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.sram_ctrl_bijection.4232769409
Short name	T478
Test name
Test status
Simulation time	311546272 ps
CPU time	20.34 seconds
Started	Jun 29 06:53:57 PM PDT 24
Finished	Jun 29 06:54:18 PM PDT 24
Peak memory	202796 kb
Host	smart-4a36a911-3cab-416f-ba51-bf3e20c86a2b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232769409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection. 4232769409
Directory	/workspace/2.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/2.sram_ctrl_executable.3371224091
Short name	T427
Test name
Test status
Simulation time	7281170082 ps
CPU time	1223.04 seconds
Started	Jun 29 06:54:10 PM PDT 24
Finished	Jun 29 07:14:34 PM PDT 24
Peak memory	374308 kb
Host	smart-51ea6ef1-4a27-4e30-bb4c-5818adfe016e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371224091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl e.3371224091
Directory	/workspace/2.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/2.sram_ctrl_lc_escalation.2355755156
Short name	T840
Test name
Test status
Simulation time	802132566 ps
CPU time	7.06 seconds
Started	Jun 29 06:53:58 PM PDT 24
Finished	Jun 29 06:54:06 PM PDT 24
Peak memory	202864 kb
Host	smart-0704078d-91f5-492a-84c5-23103a8435e9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355755156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc alation.2355755156
Directory	/workspace/2.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/2.sram_ctrl_max_throughput.2039592782
Short name	T323
Test name
Test status
Simulation time	100601763 ps
CPU time	32.52 seconds
Started	Jun 29 06:53:54 PM PDT 24
Finished	Jun 29 06:54:27 PM PDT 24
Peak memory	300436 kb
Host	smart-ef3aa40e-c1c2-4c4c-890c-6b9a13eb37c7
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039592782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_max_throughput.2039592782
Directory	/workspace/2.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/2.sram_ctrl_mem_partial_access.211085721
Short name	T295
Test name
Test status
Simulation time	334019726 ps
CPU time	4.51 seconds
Started	Jun 29 06:53:55 PM PDT 24
Finished	Jun 29 06:54:00 PM PDT 24
Peak memory	211084 kb
Host	smart-3cc33fa2-0a78-4940-b65f-a1b8780f708f
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211085721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. sram_ctrl_mem_partial_access.211085721
Directory	/workspace/2.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/2.sram_ctrl_mem_walk.1024250784
Short name	T167
Test name
Test status
Simulation time	75384414 ps
CPU time	4.47 seconds
Started	Jun 29 06:53:57 PM PDT 24
Finished	Jun 29 06:54:03 PM PDT 24
Peak memory	211072 kb
Host	smart-e6e11bf8-6474-4479-9c55-479410a4cef8
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024250784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl _mem_walk.1024250784
Directory	/workspace/2.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/2.sram_ctrl_multiple_keys.3844922300
Short name	T729
Test name
Test status
Simulation time	13874978409 ps
CPU time	720.18 seconds
Started	Jun 29 06:53:54 PM PDT 24
Finished	Jun 29 07:05:55 PM PDT 24
Peak memory	373804 kb
Host	smart-8bea5e2d-b4e2-489c-84dc-fd82514c5002
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844922300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip le_keys.3844922300
Directory	/workspace/2.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/2.sram_ctrl_partial_access.360105889
Short name	T552
Test name
Test status
Simulation time	389873163 ps
CPU time	40 seconds
Started	Jun 29 06:53:57 PM PDT 24
Finished	Jun 29 06:54:38 PM PDT 24
Peak memory	293624 kb
Host	smart-646a0225-6aa2-4cea-960e-d65bd0902eae
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360105889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sr am_ctrl_partial_access.360105889
Directory	/workspace/2.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/2.sram_ctrl_ram_cfg.3115898703
Short name	T265
Test name
Test status
Simulation time	47466027 ps
CPU time	0.76 seconds
Started	Jun 29 06:53:57 PM PDT 24
Finished	Jun 29 06:53:59 PM PDT 24
Peak memory	202880 kb
Host	smart-3ceb9d28-63b3-45df-ae40-233f2ca33a9c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115898703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.3115898703
Directory	/workspace/2.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/2.sram_ctrl_regwen.356958465
Short name	T543
Test name
Test status
Simulation time	5505984400 ps
CPU time	377.6 seconds
Started	Jun 29 06:53:56 PM PDT 24
Finished	Jun 29 07:00:14 PM PDT 24
Peak memory	369204 kb
Host	smart-b9cb8559-6c32-4f2a-9bb4-b029c7152d66
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356958465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.356958465
Directory	/workspace/2.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/2.sram_ctrl_sec_cm.215120361
Short name	T15
Test name
Test status
Simulation time	451887258 ps
CPU time	1.88 seconds
Started	Jun 29 06:53:55 PM PDT 24
Finished	Jun 29 06:53:57 PM PDT 24
Peak memory	221884 kb
Host	smart-ef84cdcf-ed0e-49c5-acb3-3eff3d013938
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215120361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_sec_cm.215120361
Directory	/workspace/2.sram_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/2.sram_ctrl_smoke.3355478509
Short name	T560
Test name
Test status
Simulation time	448848517 ps
CPU time	41.65 seconds
Started	Jun 29 06:53:52 PM PDT 24
Finished	Jun 29 06:54:35 PM PDT 24
Peak memory	311628 kb
Host	smart-fcf85ba0-821f-4333-ab07-e7d974e9ea86
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355478509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.3355478509
Directory	/workspace/2.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.sram_ctrl_stress_all.3934108172
Short name	T261
Test name
Test status
Simulation time	2866696758 ps
CPU time	119.65 seconds
Started	Jun 29 06:53:57 PM PDT 24
Finished	Jun 29 06:55:58 PM PDT 24
Peak memory	322152 kb
Host	smart-e8cb6908-98e1-48a5-baa8-449927b1a63c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934108172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.sram_ctrl_stress_all.3934108172
Directory	/workspace/2.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3234746229
Short name	T297
Test name
Test status
Simulation time	2700101202 ps
CPU time	521.61 seconds
Started	Jun 29 06:54:01 PM PDT 24
Finished	Jun 29 07:02:43 PM PDT 24
Peak memory	371760 kb
Host	smart-54a06919-04a9-4f05-abbc-01a6afc1e1f1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3234746229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.3234746229
Directory	/workspace/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.sram_ctrl_stress_pipeline.2674320664
Short name	T644
Test name
Test status
Simulation time	1595639935 ps
CPU time	153.98 seconds
Started	Jun 29 06:53:55 PM PDT 24
Finished	Jun 29 06:56:30 PM PDT 24
Peak memory	202828 kb
Host	smart-3928d6e9-c81f-4f31-9ba4-a6b2708e529e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674320664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_stress_pipeline.2674320664
Directory	/workspace/2.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1661467770
Short name	T293
Test name
Test status
Simulation time	44702798 ps
CPU time	2.16 seconds
Started	Jun 29 06:54:02 PM PDT 24
Finished	Jun 29 06:54:05 PM PDT 24
Peak memory	212052 kb
Host	smart-d2be9117-e3e1-492c-89cd-564f50ecc33f
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661467770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.1661467770
Directory	/workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/20.sram_ctrl_access_during_key_req.4110821910
Short name	T803
Test name
Test status
Simulation time	56417183580 ps
CPU time	1199.51 seconds
Started	Jun 29 06:54:57 PM PDT 24
Finished	Jun 29 07:14:58 PM PDT 24
Peak memory	373684 kb
Host	smart-721b97d4-a459-4bda-aadf-7e60d73ee01f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110821910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 20.sram_ctrl_access_during_key_req.4110821910
Directory	/workspace/20.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/20.sram_ctrl_bijection.3095838442
Short name	T120
Test name
Test status
Simulation time	15129847884 ps
CPU time	77.11 seconds
Started	Jun 29 06:54:52 PM PDT 24
Finished	Jun 29 06:56:09 PM PDT 24
Peak memory	202988 kb
Host	smart-85ee803c-8c7c-4317-89db-3ab9390922ed
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095838442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection .3095838442
Directory	/workspace/20.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/20.sram_ctrl_executable.1506230516
Short name	T884
Test name
Test status
Simulation time	9201327920 ps
CPU time	936.77 seconds
Started	Jun 29 06:54:57 PM PDT 24
Finished	Jun 29 07:10:34 PM PDT 24
Peak memory	374460 kb
Host	smart-30b8e9ca-b704-4737-b3e5-ce8b7afb19d3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506230516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab le.1506230516
Directory	/workspace/20.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/20.sram_ctrl_lc_escalation.2487307816
Short name	T929
Test name
Test status
Simulation time	569463599 ps
CPU time	7.92 seconds
Started	Jun 29 06:54:49 PM PDT 24
Finished	Jun 29 06:54:57 PM PDT 24
Peak memory	211008 kb
Host	smart-f1e11b23-ea0f-4bd2-95e2-3e0b5d5c7597
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487307816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es calation.2487307816
Directory	/workspace/20.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/20.sram_ctrl_max_throughput.939584183
Short name	T480
Test name
Test status
Simulation time	78059631 ps
CPU time	21.07 seconds
Started	Jun 29 06:54:49 PM PDT 24
Finished	Jun 29 06:55:11 PM PDT 24
Peak memory	271336 kb
Host	smart-7f392879-a3f0-4690-827e-7127ac5a2ab9
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939584183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 20.sram_ctrl_max_throughput.939584183
Directory	/workspace/20.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/20.sram_ctrl_mem_partial_access.2214785335
Short name	T439
Test name
Test status
Simulation time	420076937 ps
CPU time	3.37 seconds
Started	Jun 29 06:54:57 PM PDT 24
Finished	Jun 29 06:55:01 PM PDT 24
Peak memory	211068 kb
Host	smart-841e5695-2dd7-4ddf-8870-c692320570da
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214785335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_mem_partial_access.2214785335
Directory	/workspace/20.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/20.sram_ctrl_mem_walk.3031417503
Short name	T246
Test name
Test status
Simulation time	102370155 ps
CPU time	5.4 seconds
Started	Jun 29 06:54:59 PM PDT 24
Finished	Jun 29 06:55:05 PM PDT 24
Peak memory	211092 kb
Host	smart-de9bae36-cd22-4a3d-94c9-53f6fdb4edd9
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031417503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr l_mem_walk.3031417503
Directory	/workspace/20.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/20.sram_ctrl_multiple_keys.1614558902
Short name	T176
Test name
Test status
Simulation time	8797240568 ps
CPU time	143.16 seconds
Started	Jun 29 06:54:52 PM PDT 24
Finished	Jun 29 06:57:15 PM PDT 24
Peak memory	344540 kb
Host	smart-a228ce4b-420d-4ac7-9347-3f8d3549a764
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614558902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi ple_keys.1614558902
Directory	/workspace/20.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/20.sram_ctrl_partial_access.234731044
Short name	T320
Test name
Test status
Simulation time	3296907717 ps
CPU time	15.65 seconds
Started	Jun 29 06:54:50 PM PDT 24
Finished	Jun 29 06:55:05 PM PDT 24
Peak memory	202948 kb
Host	smart-07a3dd3a-f969-46df-8f84-36348ddae32c
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234731044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.s ram_ctrl_partial_access.234731044
Directory	/workspace/20.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.314956803
Short name	T754
Test name
Test status
Simulation time	10874108262 ps
CPU time	279.85 seconds
Started	Jun 29 06:54:45 PM PDT 24
Finished	Jun 29 06:59:25 PM PDT 24
Peak memory	202944 kb
Host	smart-478f774c-be5c-4d8b-8739-b4e043de1500
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314956803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 20.sram_ctrl_partial_access_b2b.314956803
Directory	/workspace/20.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/20.sram_ctrl_ram_cfg.3399641563
Short name	T381
Test name
Test status
Simulation time	89175558 ps
CPU time	0.77 seconds
Started	Jun 29 06:54:59 PM PDT 24
Finished	Jun 29 06:55:01 PM PDT 24
Peak memory	202884 kb
Host	smart-2b5d5d0e-3aa1-4a5f-9158-f85e78bffcb0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399641563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.3399641563
Directory	/workspace/20.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/20.sram_ctrl_regwen.2579486706
Short name	T36
Test name
Test status
Simulation time	68683541545 ps
CPU time	1030.37 seconds
Started	Jun 29 06:55:02 PM PDT 24
Finished	Jun 29 07:12:13 PM PDT 24
Peak memory	375740 kb
Host	smart-26a0ac5d-35be-4428-a2bd-0e6155d927b5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579486706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.2579486706
Directory	/workspace/20.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/20.sram_ctrl_smoke.3823483594
Short name	T260
Test name
Test status
Simulation time	242281155 ps
CPU time	64.88 seconds
Started	Jun 29 06:54:46 PM PDT 24
Finished	Jun 29 06:55:51 PM PDT 24
Peak memory	340960 kb
Host	smart-17854393-230b-41c2-b23a-6585f6e40647
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823483594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.3823483594
Directory	/workspace/20.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/20.sram_ctrl_stress_all.1030212940
Short name	T63
Test name
Test status
Simulation time	17720006371 ps
CPU time	193.81 seconds
Started	Jun 29 06:54:56 PM PDT 24
Finished	Jun 29 06:58:11 PM PDT 24
Peak memory	357252 kb
Host	smart-ba3e1a8c-6194-4b72-8f6d-69511761fdec
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030212940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 20.sram_ctrl_stress_all.1030212940
Directory	/workspace/20.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3297417435
Short name	T64
Test name
Test status
Simulation time	4344695117 ps
CPU time	530.64 seconds
Started	Jun 29 06:54:57 PM PDT 24
Finished	Jun 29 07:03:48 PM PDT 24
Peak memory	379972 kb
Host	smart-210306fe-a077-4131-a977-5abb54a022a1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3297417435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.3297417435
Directory	/workspace/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.sram_ctrl_stress_pipeline.1165010275
Short name	T726
Test name
Test status
Simulation time	2318645272 ps
CPU time	224.46 seconds
Started	Jun 29 06:54:50 PM PDT 24
Finished	Jun 29 06:58:35 PM PDT 24
Peak memory	202896 kb
Host	smart-244cb49a-9f29-4b75-b854-310bd4751d3f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165010275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_stress_pipeline.1165010275
Directory	/workspace/20.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.2865132766
Short name	T284
Test name
Test status
Simulation time	519330144 ps
CPU time	110.57 seconds
Started	Jun 29 06:54:50 PM PDT 24
Finished	Jun 29 06:56:41 PM PDT 24
Peak memory	361292 kb
Host	smart-d33194c4-b3fe-4976-87da-7163d65533ce
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865132766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.2865132766
Directory	/workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/21.sram_ctrl_access_during_key_req.72625689
Short name	T42
Test name
Test status
Simulation time	2558265617 ps
CPU time	45.11 seconds
Started	Jun 29 06:54:57 PM PDT 24
Finished	Jun 29 06:55:42 PM PDT 24
Peak memory	272052 kb
Host	smart-4f3e20c6-a915-43e8-bd62-079b6ca6d0e6
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72625689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 21.sram_ctrl_access_during_key_req.72625689
Directory	/workspace/21.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/21.sram_ctrl_alert_test.1407202835
Short name	T475
Test name
Test status
Simulation time	41134917 ps
CPU time	0.66 seconds
Started	Jun 29 06:54:54 PM PDT 24
Finished	Jun 29 06:54:55 PM PDT 24
Peak memory	202644 kb
Host	smart-8ba98bc8-1080-41d6-be08-da09dd2f8413
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407202835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.1407202835
Directory	/workspace/21.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.sram_ctrl_bijection.679275305
Short name	T306
Test name
Test status
Simulation time	21835270595 ps
CPU time	90.65 seconds
Started	Jun 29 06:54:59 PM PDT 24
Finished	Jun 29 06:56:30 PM PDT 24
Peak memory	202924 kb
Host	smart-c9adeffb-6598-48b3-9122-8a5fe77a42b3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679275305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection. 679275305
Directory	/workspace/21.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/21.sram_ctrl_executable.577632870
Short name	T862
Test name
Test status
Simulation time	79730699330 ps
CPU time	1499.55 seconds
Started	Jun 29 06:54:55 PM PDT 24
Finished	Jun 29 07:19:55 PM PDT 24
Peak memory	373760 kb
Host	smart-a5d49747-ba64-4e3e-8c9c-8c8a88296ca1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577632870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executabl e.577632870
Directory	/workspace/21.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/21.sram_ctrl_lc_escalation.1529641592
Short name	T583
Test name
Test status
Simulation time	734592031 ps
CPU time	4.53 seconds
Started	Jun 29 06:54:57 PM PDT 24
Finished	Jun 29 06:55:03 PM PDT 24
Peak memory	203076 kb
Host	smart-f29bfaa9-4c55-48c6-8bf9-eeec1acb1cd2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529641592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es calation.1529641592
Directory	/workspace/21.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/21.sram_ctrl_max_throughput.3236491147
Short name	T768
Test name
Test status
Simulation time	1671523582 ps
CPU time	53.14 seconds
Started	Jun 29 06:54:57 PM PDT 24
Finished	Jun 29 06:55:51 PM PDT 24
Peak memory	322564 kb
Host	smart-faf39406-2aa1-443b-8a21-50162d0a0675
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236491147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 21.sram_ctrl_max_throughput.3236491147
Directory	/workspace/21.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/21.sram_ctrl_mem_partial_access.2039923046
Short name	T507
Test name
Test status
Simulation time	413538789 ps
CPU time	3.28 seconds
Started	Jun 29 06:54:58 PM PDT 24
Finished	Jun 29 06:55:01 PM PDT 24
Peak memory	211096 kb
Host	smart-730f27e2-3926-4e6b-b2a3-bf6f861f6abb
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039923046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_mem_partial_access.2039923046
Directory	/workspace/21.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/21.sram_ctrl_mem_walk.2905177506
Short name	T50
Test name
Test status
Simulation time	189415605 ps
CPU time	5.36 seconds
Started	Jun 29 06:54:58 PM PDT 24
Finished	Jun 29 06:55:04 PM PDT 24
Peak memory	202840 kb
Host	smart-12523a2d-cd7c-4db8-b95e-8acd42d6cc0e
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905177506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr l_mem_walk.2905177506
Directory	/workspace/21.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/21.sram_ctrl_multiple_keys.1029620720
Short name	T446
Test name
Test status
Simulation time	3226855607 ps
CPU time	736.37 seconds
Started	Jun 29 06:54:57 PM PDT 24
Finished	Jun 29 07:07:14 PM PDT 24
Peak memory	373676 kb
Host	smart-64e165dd-0fb2-4b54-9110-4e19350f7ad3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029620720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi ple_keys.1029620720
Directory	/workspace/21.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/21.sram_ctrl_partial_access.401036606
Short name	T457
Test name
Test status
Simulation time	2423434308 ps
CPU time	21.45 seconds
Started	Jun 29 06:54:55 PM PDT 24
Finished	Jun 29 06:55:16 PM PDT 24
Peak memory	202948 kb
Host	smart-533c6386-35c4-4349-ab46-30b16ac699c5
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401036606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.s ram_ctrl_partial_access.401036606
Directory	/workspace/21.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.954206893
Short name	T829
Test name
Test status
Simulation time	18678210741 ps
CPU time	492.18 seconds
Started	Jun 29 06:54:56 PM PDT 24
Finished	Jun 29 07:03:08 PM PDT 24
Peak memory	202876 kb
Host	smart-13d0e61d-da83-41e2-b8f4-a0a477ece5e5
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954206893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 21.sram_ctrl_partial_access_b2b.954206893
Directory	/workspace/21.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/21.sram_ctrl_ram_cfg.3456161753
Short name	T501
Test name
Test status
Simulation time	29730902 ps
CPU time	0.77 seconds
Started	Jun 29 06:55:00 PM PDT 24
Finished	Jun 29 06:55:01 PM PDT 24
Peak memory	202876 kb
Host	smart-ad334ef0-d3ae-440a-a7a4-0b283a0a71cf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456161753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.3456161753
Directory	/workspace/21.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/21.sram_ctrl_regwen.3447313759
Short name	T834
Test name
Test status
Simulation time	463251776 ps
CPU time	107.83 seconds
Started	Jun 29 06:54:57 PM PDT 24
Finished	Jun 29 06:56:46 PM PDT 24
Peak memory	340036 kb
Host	smart-f4019fb4-d90b-4672-90f8-68f1b163d54a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447313759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.3447313759
Directory	/workspace/21.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/21.sram_ctrl_smoke.4016425337
Short name	T820
Test name
Test status
Simulation time	743314318 ps
CPU time	16.97 seconds
Started	Jun 29 06:54:57 PM PDT 24
Finished	Jun 29 06:55:15 PM PDT 24
Peak memory	202756 kb
Host	smart-d08e21c2-988f-4305-aa3c-1d58c74dac79
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016425337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.4016425337
Directory	/workspace/21.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.sram_ctrl_stress_all.444680216
Short name	T30
Test name
Test status
Simulation time	6579703873 ps
CPU time	2007.95 seconds
Started	Jun 29 06:54:59 PM PDT 24
Finished	Jun 29 07:28:28 PM PDT 24
Peak memory	383128 kb
Host	smart-9c7ec8f9-14f4-41a6-8756-9d8c400dd134
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444680216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.sram_ctrl_stress_all.444680216
Directory	/workspace/21.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.959946226
Short name	T65
Test name
Test status
Simulation time	2538868718 ps
CPU time	168.42 seconds
Started	Jun 29 06:54:54 PM PDT 24
Finished	Jun 29 06:57:43 PM PDT 24
Peak memory	324704 kb
Host	smart-8cc888e3-17a7-4c30-bb5d-42c2ba201b32
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=959946226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.959946226
Directory	/workspace/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.sram_ctrl_stress_pipeline.4292212401
Short name	T888
Test name
Test status
Simulation time	7147947420 ps
CPU time	176.69 seconds
Started	Jun 29 06:54:54 PM PDT 24
Finished	Jun 29 06:57:51 PM PDT 24
Peak memory	202940 kb
Host	smart-9fc3e181-b924-461f-8aea-3348e5b3ebc4
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292212401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_stress_pipeline.4292212401
Directory	/workspace/21.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.1730942136
Short name	T676
Test name
Test status
Simulation time	155080078 ps
CPU time	90.98 seconds
Started	Jun 29 06:54:55 PM PDT 24
Finished	Jun 29 06:56:27 PM PDT 24
Peak memory	350556 kb
Host	smart-96b8cccd-d2ea-424d-a092-48c37aa171bb
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730942136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.1730942136
Directory	/workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/22.sram_ctrl_access_during_key_req.1790415041
Short name	T222
Test name
Test status
Simulation time	2911821879 ps
CPU time	1184.2 seconds
Started	Jun 29 06:55:01 PM PDT 24
Finished	Jun 29 07:14:46 PM PDT 24
Peak memory	373680 kb
Host	smart-65ef0b7a-5484-45ae-84a5-e69f5b625ec8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790415041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 22.sram_ctrl_access_during_key_req.1790415041
Directory	/workspace/22.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/22.sram_ctrl_alert_test.2080577668
Short name	T876
Test name
Test status
Simulation time	21601231 ps
CPU time	0.72 seconds
Started	Jun 29 06:55:02 PM PDT 24
Finished	Jun 29 06:55:03 PM PDT 24
Peak memory	202300 kb
Host	smart-830e686b-c6bf-4c77-9ef0-e567df2cee01
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080577668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.2080577668
Directory	/workspace/22.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.sram_ctrl_bijection.4267787112
Short name	T592
Test name
Test status
Simulation time	3556791383 ps
CPU time	62 seconds
Started	Jun 29 06:54:54 PM PDT 24
Finished	Jun 29 06:55:57 PM PDT 24
Peak memory	202932 kb
Host	smart-d42aa3ff-e831-4d70-a11d-c404277a9eb3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267787112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection .4267787112
Directory	/workspace/22.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/22.sram_ctrl_executable.3021031243
Short name	T843
Test name
Test status
Simulation time	3026121891 ps
CPU time	195.42 seconds
Started	Jun 29 06:54:59 PM PDT 24
Finished	Jun 29 06:58:15 PM PDT 24
Peak memory	322992 kb
Host	smart-ca71476f-6610-479e-8bfd-f4fdb42369b7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021031243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executab le.3021031243
Directory	/workspace/22.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/22.sram_ctrl_lc_escalation.411449874
Short name	T393
Test name
Test status
Simulation time	1933247637 ps
CPU time	7 seconds
Started	Jun 29 06:55:01 PM PDT 24
Finished	Jun 29 06:55:09 PM PDT 24
Peak memory	202796 kb
Host	smart-135a2123-0817-4c93-9e25-8e7f521e2ce9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411449874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_esc alation.411449874
Directory	/workspace/22.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/22.sram_ctrl_max_throughput.1235778848
Short name	T799
Test name
Test status
Simulation time	471352665 ps
CPU time	88.44 seconds
Started	Jun 29 06:54:55 PM PDT 24
Finished	Jun 29 06:56:24 PM PDT 24
Peak memory	353012 kb
Host	smart-2ac457a7-1798-4a18-bb09-f961e762b8f9
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235778848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 22.sram_ctrl_max_throughput.1235778848
Directory	/workspace/22.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/22.sram_ctrl_mem_partial_access.246915625
Short name	T511
Test name
Test status
Simulation time	391442602 ps
CPU time	3.35 seconds
Started	Jun 29 06:55:01 PM PDT 24
Finished	Jun 29 06:55:05 PM PDT 24
Peak memory	211032 kb
Host	smart-1ca80b2e-b963-4331-8a71-983df7d97114
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246915625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22 .sram_ctrl_mem_partial_access.246915625
Directory	/workspace/22.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/22.sram_ctrl_mem_walk.1118197271
Short name	T536
Test name
Test status
Simulation time	96763647 ps
CPU time	5.34 seconds
Started	Jun 29 06:54:59 PM PDT 24
Finished	Jun 29 06:55:04 PM PDT 24
Peak memory	211128 kb
Host	smart-eb636171-61f3-435c-8be9-8ca97cf55ff6
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118197271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr l_mem_walk.1118197271
Directory	/workspace/22.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/22.sram_ctrl_multiple_keys.83137885
Short name	T670
Test name
Test status
Simulation time	48209259170 ps
CPU time	1167.62 seconds
Started	Jun 29 06:54:57 PM PDT 24
Finished	Jun 29 07:14:26 PM PDT 24
Peak memory	375140 kb
Host	smart-81ba0b67-3c74-47ee-9729-b6f5b26510b4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83137885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multipl e_keys.83137885
Directory	/workspace/22.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/22.sram_ctrl_partial_access.2320355891
Short name	T672
Test name
Test status
Simulation time	1381611201 ps
CPU time	13.65 seconds
Started	Jun 29 06:54:59 PM PDT 24
Finished	Jun 29 06:55:13 PM PDT 24
Peak memory	202760 kb
Host	smart-cd483e8d-ab9e-431f-85e3-abf1093b12b7
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320355891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22. sram_ctrl_partial_access.2320355891
Directory	/workspace/22.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.3986806274
Short name	T861
Test name
Test status
Simulation time	5070622260 ps
CPU time	388.26 seconds
Started	Jun 29 06:54:56 PM PDT 24
Finished	Jun 29 07:01:24 PM PDT 24
Peak memory	202932 kb
Host	smart-c4407c3f-e846-450f-a97c-5911fd334383
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986806274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 22.sram_ctrl_partial_access_b2b.3986806274
Directory	/workspace/22.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/22.sram_ctrl_ram_cfg.4208571248
Short name	T930
Test name
Test status
Simulation time	31431066 ps
CPU time	0.79 seconds
Started	Jun 29 06:54:59 PM PDT 24
Finished	Jun 29 06:55:00 PM PDT 24
Peak memory	202880 kb
Host	smart-6e47fb55-1b5b-442d-9cd5-1a5b9e039b3e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208571248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.4208571248
Directory	/workspace/22.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/22.sram_ctrl_regwen.4017834639
Short name	T858
Test name
Test status
Simulation time	5040425190 ps
CPU time	618.09 seconds
Started	Jun 29 06:55:01 PM PDT 24
Finished	Jun 29 07:05:20 PM PDT 24
Peak memory	367636 kb
Host	smart-13393c76-11e5-4cb1-84b7-41da0ed377cb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017834639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.4017834639
Directory	/workspace/22.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/22.sram_ctrl_smoke.1688597901
Short name	T161
Test name
Test status
Simulation time	597907849 ps
CPU time	12.33 seconds
Started	Jun 29 06:54:58 PM PDT 24
Finished	Jun 29 06:55:11 PM PDT 24
Peak memory	202800 kb
Host	smart-12f56be2-309a-49a5-a833-eaed4cf80329
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688597901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.1688597901
Directory	/workspace/22.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.sram_ctrl_stress_all.1219574093
Short name	T314
Test name
Test status
Simulation time	53273215961 ps
CPU time	5037.41 seconds
Started	Jun 29 06:55:03 PM PDT 24
Finished	Jun 29 08:19:01 PM PDT 24
Peak memory	383516 kb
Host	smart-734ce419-babe-49a0-94ee-039f7eb7fb44
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219574093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 22.sram_ctrl_stress_all.1219574093
Directory	/workspace/22.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.248234586
Short name	T481
Test name
Test status
Simulation time	10661564741 ps
CPU time	258.39 seconds
Started	Jun 29 06:54:59 PM PDT 24
Finished	Jun 29 06:59:18 PM PDT 24
Peak memory	341096 kb
Host	smart-a41e3e12-f1d0-4f79-8085-a8bf20313211
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=248234586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.248234586
Directory	/workspace/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.sram_ctrl_stress_pipeline.912375466
Short name	T620
Test name
Test status
Simulation time	7303920796 ps
CPU time	173.9 seconds
Started	Jun 29 06:54:55 PM PDT 24
Finished	Jun 29 06:57:50 PM PDT 24
Peak memory	202960 kb
Host	smart-d8817c78-3c4e-45c6-b228-24b739b7af89
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912375466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22 .sram_ctrl_stress_pipeline.912375466
Directory	/workspace/22.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.950502131
Short name	T643
Test name
Test status
Simulation time	125017648 ps
CPU time	7.51 seconds
Started	Jun 29 06:55:02 PM PDT 24
Finished	Jun 29 06:55:10 PM PDT 24
Peak memory	238096 kb
Host	smart-aea7a0ec-7917-4991-8639-d811a5eaf57b
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950502131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 22.sram_ctrl_throughput_w_partial_write.950502131
Directory	/workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/23.sram_ctrl_access_during_key_req.3851206112
Short name	T302
Test name
Test status
Simulation time	2273988872 ps
CPU time	958.76 seconds
Started	Jun 29 06:55:02 PM PDT 24
Finished	Jun 29 07:11:01 PM PDT 24
Peak memory	374600 kb
Host	smart-87078cc4-3c85-4661-acd4-fbbc8d99b14f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851206112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 23.sram_ctrl_access_during_key_req.3851206112
Directory	/workspace/23.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/23.sram_ctrl_alert_test.3211460577
Short name	T752
Test name
Test status
Simulation time	16105844 ps
CPU time	0.69 seconds
Started	Jun 29 06:55:00 PM PDT 24
Finished	Jun 29 06:55:02 PM PDT 24
Peak memory	202652 kb
Host	smart-212bd7f2-986a-410e-803d-bb3fcebc3241
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211460577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.3211460577
Directory	/workspace/23.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.sram_ctrl_bijection.3856151875
Short name	T231
Test name
Test status
Simulation time	979450052 ps
CPU time	32.79 seconds
Started	Jun 29 06:55:13 PM PDT 24
Finished	Jun 29 06:55:46 PM PDT 24
Peak memory	202780 kb
Host	smart-d15003a8-c687-4481-a2be-05125f84e227
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856151875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection .3856151875
Directory	/workspace/23.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/23.sram_ctrl_executable.3937969817
Short name	T453
Test name
Test status
Simulation time	16469998278 ps
CPU time	1154.75 seconds
Started	Jun 29 06:55:00 PM PDT 24
Finished	Jun 29 07:14:15 PM PDT 24
Peak memory	375680 kb
Host	smart-a3cd58f6-dc53-4641-b849-c1d6f9dc4c56
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937969817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab le.3937969817
Directory	/workspace/23.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/23.sram_ctrl_lc_escalation.1727918459
Short name	T743
Test name
Test status
Simulation time	976435318 ps
CPU time	5.07 seconds
Started	Jun 29 06:55:00 PM PDT 24
Finished	Jun 29 06:55:06 PM PDT 24
Peak memory	202796 kb
Host	smart-0ee912e2-dbab-46c0-86ee-427dcb599a42
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727918459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es calation.1727918459
Directory	/workspace/23.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/23.sram_ctrl_max_throughput.3178437068
Short name	T882
Test name
Test status
Simulation time	327346674 ps
CPU time	6.87 seconds
Started	Jun 29 06:55:00 PM PDT 24
Finished	Jun 29 06:55:07 PM PDT 24
Peak memory	235376 kb
Host	smart-374be419-e0cc-465f-a26f-50f51f20f680
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178437068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 23.sram_ctrl_max_throughput.3178437068
Directory	/workspace/23.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/23.sram_ctrl_mem_partial_access.1978580211
Short name	T593
Test name
Test status
Simulation time	887944585 ps
CPU time	3.08 seconds
Started	Jun 29 06:55:12 PM PDT 24
Finished	Jun 29 06:55:16 PM PDT 24
Peak memory	211108 kb
Host	smart-999d2721-5c51-467f-af73-2e5b7b31bf83
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978580211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_mem_partial_access.1978580211
Directory	/workspace/23.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/23.sram_ctrl_mem_walk.3837362435
Short name	T195
Test name
Test status
Simulation time	444338213 ps
CPU time	10.13 seconds
Started	Jun 29 06:55:02 PM PDT 24
Finished	Jun 29 06:55:13 PM PDT 24
Peak memory	211080 kb
Host	smart-96f69231-d7f0-4033-8a4d-7987e2aef5ee
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837362435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr l_mem_walk.3837362435
Directory	/workspace/23.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/23.sram_ctrl_multiple_keys.666660108
Short name	T786
Test name
Test status
Simulation time	57682687644 ps
CPU time	1216.32 seconds
Started	Jun 29 06:54:58 PM PDT 24
Finished	Jun 29 07:15:15 PM PDT 24
Peak memory	366500 kb
Host	smart-94be21b4-49ae-4094-970c-af017b124f25
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666660108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multip le_keys.666660108
Directory	/workspace/23.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/23.sram_ctrl_partial_access.269865123
Short name	T572
Test name
Test status
Simulation time	623500117 ps
CPU time	116.85 seconds
Started	Jun 29 06:55:03 PM PDT 24
Finished	Jun 29 06:57:00 PM PDT 24
Peak memory	354928 kb
Host	smart-5b69209e-b386-45bd-aafe-89bd6e2d092a
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269865123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.s ram_ctrl_partial_access.269865123
Directory	/workspace/23.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.598267266
Short name	T407
Test name
Test status
Simulation time	12998415975 ps
CPU time	239.04 seconds
Started	Jun 29 06:55:03 PM PDT 24
Finished	Jun 29 06:59:02 PM PDT 24
Peak memory	202896 kb
Host	smart-577872fb-e85f-4323-a770-ec56faf6b646
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598267266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 23.sram_ctrl_partial_access_b2b.598267266
Directory	/workspace/23.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/23.sram_ctrl_ram_cfg.1920659074
Short name	T290
Test name
Test status
Simulation time	74885370 ps
CPU time	0.76 seconds
Started	Jun 29 06:55:00 PM PDT 24
Finished	Jun 29 06:55:02 PM PDT 24
Peak memory	202892 kb
Host	smart-00b1f4c6-8ba5-4af3-b45e-1979d1e4cb39
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920659074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.1920659074
Directory	/workspace/23.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/23.sram_ctrl_smoke.2792010696
Short name	T121
Test name
Test status
Simulation time	164783961 ps
CPU time	3.95 seconds
Started	Jun 29 06:55:03 PM PDT 24
Finished	Jun 29 06:55:07 PM PDT 24
Peak memory	202784 kb
Host	smart-5ab39592-3e9a-469e-bf9a-bc1605679422
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792010696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.2792010696
Directory	/workspace/23.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/23.sram_ctrl_stress_all.175735058
Short name	T226
Test name
Test status
Simulation time	7510476493 ps
CPU time	3644.54 seconds
Started	Jun 29 06:54:59 PM PDT 24
Finished	Jun 29 07:55:45 PM PDT 24
Peak memory	375756 kb
Host	smart-f3e163a5-f32e-450a-a5b3-8e05911b5f76
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175735058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 23.sram_ctrl_stress_all.175735058
Directory	/workspace/23.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3094880758
Short name	T761
Test name
Test status
Simulation time	435784089 ps
CPU time	94.28 seconds
Started	Jun 29 06:55:02 PM PDT 24
Finished	Jun 29 06:56:36 PM PDT 24
Peak memory	314520 kb
Host	smart-a74aad00-c9d6-4320-9460-04cfc7e0ab20
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3094880758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.3094880758
Directory	/workspace/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.sram_ctrl_stress_pipeline.4058894871
Short name	T343
Test name
Test status
Simulation time	1747752746 ps
CPU time	148.75 seconds
Started	Jun 29 06:55:13 PM PDT 24
Finished	Jun 29 06:57:42 PM PDT 24
Peak memory	202840 kb
Host	smart-a22dd925-6d2b-4fbd-a65f-258c098dd9d7
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058894871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_stress_pipeline.4058894871
Directory	/workspace/23.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.2260889961
Short name	T230
Test name
Test status
Simulation time	93418974 ps
CPU time	25.99 seconds
Started	Jun 29 06:55:03 PM PDT 24
Finished	Jun 29 06:55:29 PM PDT 24
Peak memory	279904 kb
Host	smart-916b8b75-ef9a-4125-96dc-512009e16d0f
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260889961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.2260889961
Directory	/workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/24.sram_ctrl_access_during_key_req.3263214080
Short name	T779
Test name
Test status
Simulation time	5420689230 ps
CPU time	885.08 seconds
Started	Jun 29 06:55:15 PM PDT 24
Finished	Jun 29 07:10:01 PM PDT 24
Peak memory	371700 kb
Host	smart-08dff964-ea2e-49eb-8c80-ba2061c8f4ca
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263214080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 24.sram_ctrl_access_during_key_req.3263214080
Directory	/workspace/24.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/24.sram_ctrl_alert_test.3922482022
Short name	T200
Test name
Test status
Simulation time	17921232 ps
CPU time	0.69 seconds
Started	Jun 29 06:55:07 PM PDT 24
Finished	Jun 29 06:55:08 PM PDT 24
Peak memory	202584 kb
Host	smart-f0d49e71-16c8-4684-ae48-a65becca763b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922482022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.3922482022
Directory	/workspace/24.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.sram_ctrl_bijection.487462540
Short name	T401
Test name
Test status
Simulation time	10244454648 ps
CPU time	56.01 seconds
Started	Jun 29 06:55:00 PM PDT 24
Finished	Jun 29 06:55:56 PM PDT 24
Peak memory	202948 kb
Host	smart-b5bf917f-4b6d-44e9-995d-15d91e2739d9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487462540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection. 487462540
Directory	/workspace/24.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/24.sram_ctrl_executable.3404463334
Short name	T464
Test name
Test status
Simulation time	13292250645 ps
CPU time	1023.24 seconds
Started	Jun 29 06:55:09 PM PDT 24
Finished	Jun 29 07:12:13 PM PDT 24
Peak memory	362456 kb
Host	smart-78f81c05-6ae8-457b-9df3-72e452c74160
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404463334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab le.3404463334
Directory	/workspace/24.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/24.sram_ctrl_max_throughput.3902162336
Short name	T384
Test name
Test status
Simulation time	92844193 ps
CPU time	4.2 seconds
Started	Jun 29 06:55:08 PM PDT 24
Finished	Jun 29 06:55:13 PM PDT 24
Peak memory	224344 kb
Host	smart-15a8a128-ff22-4614-9dce-109b8c4cd5d5
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902162336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 24.sram_ctrl_max_throughput.3902162336
Directory	/workspace/24.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/24.sram_ctrl_mem_partial_access.1355036295
Short name	T606
Test name
Test status
Simulation time	226995573 ps
CPU time	3.13 seconds
Started	Jun 29 06:55:09 PM PDT 24
Finished	Jun 29 06:55:12 PM PDT 24
Peak memory	211028 kb
Host	smart-76b33260-326f-4e2e-a9d2-dfe05c909376
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355036295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_mem_partial_access.1355036295
Directory	/workspace/24.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/24.sram_ctrl_mem_walk.2063901869
Short name	T580
Test name
Test status
Simulation time	692324433 ps
CPU time	10.58 seconds
Started	Jun 29 06:55:09 PM PDT 24
Finished	Jun 29 06:55:20 PM PDT 24
Peak memory	211076 kb
Host	smart-615abde4-e928-4fa5-a7f0-63acd338e037
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063901869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr l_mem_walk.2063901869
Directory	/workspace/24.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/24.sram_ctrl_multiple_keys.781445141
Short name	T630
Test name
Test status
Simulation time	50145238290 ps
CPU time	602.03 seconds
Started	Jun 29 06:55:00 PM PDT 24
Finished	Jun 29 07:05:03 PM PDT 24
Peak memory	371856 kb
Host	smart-4fe1b187-725c-4500-baec-0a198a3c6314
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781445141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multip le_keys.781445141
Directory	/workspace/24.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/24.sram_ctrl_partial_access.1869013217
Short name	T900
Test name
Test status
Simulation time	1252818859 ps
CPU time	11.98 seconds
Started	Jun 29 06:55:07 PM PDT 24
Finished	Jun 29 06:55:19 PM PDT 24
Peak memory	202812 kb
Host	smart-f09a0a1c-ad09-49e6-9813-ed8ff2722e8d
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869013217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24. sram_ctrl_partial_access.1869013217
Directory	/workspace/24.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.2620825044
Short name	T836
Test name
Test status
Simulation time	27257032025 ps
CPU time	268.37 seconds
Started	Jun 29 06:55:09 PM PDT 24
Finished	Jun 29 06:59:37 PM PDT 24
Peak memory	202856 kb
Host	smart-2590d518-ccd8-4858-a0ce-9d7198368fa0
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620825044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 24.sram_ctrl_partial_access_b2b.2620825044
Directory	/workspace/24.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/24.sram_ctrl_ram_cfg.1281903340
Short name	T568
Test name
Test status
Simulation time	108716831 ps
CPU time	0.84 seconds
Started	Jun 29 06:55:08 PM PDT 24
Finished	Jun 29 06:55:09 PM PDT 24
Peak memory	202880 kb
Host	smart-c97bf224-2ec3-40fa-b239-f5f06a82841b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281903340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.1281903340
Directory	/workspace/24.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/24.sram_ctrl_regwen.831283927
Short name	T525
Test name
Test status
Simulation time	4806358449 ps
CPU time	409.5 seconds
Started	Jun 29 06:55:06 PM PDT 24
Finished	Jun 29 07:01:56 PM PDT 24
Peak memory	359272 kb
Host	smart-7dc7e6eb-996f-4329-8d15-721c46d34140
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831283927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.831283927
Directory	/workspace/24.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/24.sram_ctrl_smoke.752188010
Short name	T382
Test name
Test status
Simulation time	83348394 ps
CPU time	2.46 seconds
Started	Jun 29 06:55:13 PM PDT 24
Finished	Jun 29 06:55:15 PM PDT 24
Peak memory	202840 kb
Host	smart-daadbe55-36a9-4830-971b-57a030ba517f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752188010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.752188010
Directory	/workspace/24.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.sram_ctrl_stress_all.3373219991
Short name	T386
Test name
Test status
Simulation time	216344883070 ps
CPU time	1699.49 seconds
Started	Jun 29 06:55:07 PM PDT 24
Finished	Jun 29 07:23:27 PM PDT 24
Peak memory	374328 kb
Host	smart-714e11a7-dd6f-4ca7-be47-a2a99210b151
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373219991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 24.sram_ctrl_stress_all.3373219991
Directory	/workspace/24.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.144717637
Short name	T709
Test name
Test status
Simulation time	1151463124 ps
CPU time	158.15 seconds
Started	Jun 29 06:55:09 PM PDT 24
Finished	Jun 29 06:57:48 PM PDT 24
Peak memory	378708 kb
Host	smart-ef804593-7239-47b7-8dbf-1679c4779000
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=144717637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.144717637
Directory	/workspace/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.sram_ctrl_stress_pipeline.1023655909
Short name	T406
Test name
Test status
Simulation time	5035002049 ps
CPU time	257.22 seconds
Started	Jun 29 06:55:09 PM PDT 24
Finished	Jun 29 06:59:27 PM PDT 24
Peak memory	202892 kb
Host	smart-9269d1ca-8dc4-4b37-9e45-b20d296a8124
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023655909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_stress_pipeline.1023655909
Directory	/workspace/24.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.597594977
Short name	T264
Test name
Test status
Simulation time	142250766 ps
CPU time	80.77 seconds
Started	Jun 29 06:55:09 PM PDT 24
Finished	Jun 29 06:56:30 PM PDT 24
Peak memory	356776 kb
Host	smart-c67348fc-022b-4f2b-8c5e-7792e027b88d
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597594977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 24.sram_ctrl_throughput_w_partial_write.597594977
Directory	/workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/25.sram_ctrl_access_during_key_req.2330701874
Short name	T921
Test name
Test status
Simulation time	11935518110 ps
CPU time	750.94 seconds
Started	Jun 29 06:55:18 PM PDT 24
Finished	Jun 29 07:07:49 PM PDT 24
Peak memory	369964 kb
Host	smart-76c87801-b72a-46a3-aedc-ad9696c62176
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330701874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 25.sram_ctrl_access_during_key_req.2330701874
Directory	/workspace/25.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/25.sram_ctrl_alert_test.3433300895
Short name	T171
Test name
Test status
Simulation time	25153141 ps
CPU time	0.7 seconds
Started	Jun 29 06:55:16 PM PDT 24
Finished	Jun 29 06:55:17 PM PDT 24
Peak memory	202604 kb
Host	smart-b1fea140-aaa5-4bc5-8a62-2fb4f724ce30
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433300895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.3433300895
Directory	/workspace/25.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.sram_ctrl_bijection.1721030826
Short name	T600
Test name
Test status
Simulation time	1907315968 ps
CPU time	50.06 seconds
Started	Jun 29 06:55:10 PM PDT 24
Finished	Jun 29 06:56:00 PM PDT 24
Peak memory	202776 kb
Host	smart-927feeab-14cd-4801-9e09-d2954eece3ef
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721030826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection .1721030826
Directory	/workspace/25.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/25.sram_ctrl_executable.2895099415
Short name	T616
Test name
Test status
Simulation time	20108334007 ps
CPU time	149.13 seconds
Started	Jun 29 06:55:16 PM PDT 24
Finished	Jun 29 06:57:45 PM PDT 24
Peak memory	328776 kb
Host	smart-f0ca57d8-b07a-4bae-a743-51ce0887becd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895099415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab le.2895099415
Directory	/workspace/25.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/25.sram_ctrl_lc_escalation.19453908
Short name	T126
Test name
Test status
Simulation time	1679277691 ps
CPU time	9.89 seconds
Started	Jun 29 06:55:08 PM PDT 24
Finished	Jun 29 06:55:18 PM PDT 24
Peak memory	202860 kb
Host	smart-7522ae37-76d5-4502-b849-a3c86f79f553
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19453908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_esca lation.19453908
Directory	/workspace/25.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/25.sram_ctrl_max_throughput.3038349912
Short name	T157
Test name
Test status
Simulation time	195580023 ps
CPU time	57.6 seconds
Started	Jun 29 06:55:07 PM PDT 24
Finished	Jun 29 06:56:05 PM PDT 24
Peak memory	316928 kb
Host	smart-994cde93-e8e6-4fd5-aa22-859fdb221b7a
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038349912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 25.sram_ctrl_max_throughput.3038349912
Directory	/workspace/25.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/25.sram_ctrl_mem_partial_access.3723473218
Short name	T48
Test name
Test status
Simulation time	92173447 ps
CPU time	5.47 seconds
Started	Jun 29 06:55:16 PM PDT 24
Finished	Jun 29 06:55:22 PM PDT 24
Peak memory	211092 kb
Host	smart-50abaa56-6424-4dd0-9bc6-e4307a0f1305
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723473218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_mem_partial_access.3723473218
Directory	/workspace/25.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/25.sram_ctrl_mem_walk.1541063565
Short name	T853
Test name
Test status
Simulation time	1011757042 ps
CPU time	5.97 seconds
Started	Jun 29 06:55:16 PM PDT 24
Finished	Jun 29 06:55:23 PM PDT 24
Peak memory	211068 kb
Host	smart-44876753-196c-4f6e-b398-1190b5fe73f8
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541063565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr l_mem_walk.1541063565
Directory	/workspace/25.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/25.sram_ctrl_multiple_keys.2211979529
Short name	T627
Test name
Test status
Simulation time	52665172646 ps
CPU time	962.77 seconds
Started	Jun 29 06:55:15 PM PDT 24
Finished	Jun 29 07:11:19 PM PDT 24
Peak memory	375776 kb
Host	smart-5dafc5fa-366e-46a0-9288-0aef9af7040f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211979529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi ple_keys.2211979529
Directory	/workspace/25.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/25.sram_ctrl_partial_access.2841599776
Short name	T154
Test name
Test status
Simulation time	266154162 ps
CPU time	56.04 seconds
Started	Jun 29 06:55:15 PM PDT 24
Finished	Jun 29 06:56:11 PM PDT 24
Peak memory	303004 kb
Host	smart-3e4b7008-6856-44b3-b8b5-936219233b37
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841599776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25. sram_ctrl_partial_access.2841599776
Directory	/workspace/25.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1184358829
Short name	T321
Test name
Test status
Simulation time	59390303820 ps
CPU time	442.05 seconds
Started	Jun 29 06:55:15 PM PDT 24
Finished	Jun 29 07:02:38 PM PDT 24
Peak memory	202892 kb
Host	smart-5f70599c-856a-47b1-aa93-ae79afabe2e4
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184358829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.sram_ctrl_partial_access_b2b.1184358829
Directory	/workspace/25.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/25.sram_ctrl_ram_cfg.2747424378
Short name	T737
Test name
Test status
Simulation time	97300710 ps
CPU time	0.94 seconds
Started	Jun 29 06:55:17 PM PDT 24
Finished	Jun 29 06:55:18 PM PDT 24
Peak memory	202864 kb
Host	smart-63375e79-97b9-48b4-9ae8-11e88e5ac2f6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747424378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.2747424378
Directory	/workspace/25.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/25.sram_ctrl_regwen.1496652509
Short name	T584
Test name
Test status
Simulation time	79024538027 ps
CPU time	713.93 seconds
Started	Jun 29 06:55:15 PM PDT 24
Finished	Jun 29 07:07:10 PM PDT 24
Peak memory	368584 kb
Host	smart-430db2ac-c267-4584-a950-47c8f709ff77
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496652509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.1496652509
Directory	/workspace/25.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/25.sram_ctrl_smoke.1308231085
Short name	T276
Test name
Test status
Simulation time	356409568 ps
CPU time	1.32 seconds
Started	Jun 29 06:55:10 PM PDT 24
Finished	Jun 29 06:55:11 PM PDT 24
Peak memory	202784 kb
Host	smart-ec03575c-aeab-44c0-9d20-6874fe795752
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308231085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.1308231085
Directory	/workspace/25.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.sram_ctrl_stress_all.223015682
Short name	T745
Test name
Test status
Simulation time	15462279981 ps
CPU time	1188.02 seconds
Started	Jun 29 06:55:16 PM PDT 24
Finished	Jun 29 07:15:04 PM PDT 24
Peak memory	369932 kb
Host	smart-455a26b4-3a15-43a3-ba3c-c84ebdc90b97
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223015682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.sram_ctrl_stress_all.223015682
Directory	/workspace/25.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.426801287
Short name	T733
Test name
Test status
Simulation time	1479763394 ps
CPU time	229.73 seconds
Started	Jun 29 06:55:16 PM PDT 24
Finished	Jun 29 06:59:07 PM PDT 24
Peak memory	331064 kb
Host	smart-e9fd5d5a-9f51-403a-a78a-9fbfb2433c6d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=426801287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.426801287
Directory	/workspace/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.sram_ctrl_stress_pipeline.784320660
Short name	T607
Test name
Test status
Simulation time	2015262370 ps
CPU time	192.25 seconds
Started	Jun 29 06:55:08 PM PDT 24
Finished	Jun 29 06:58:21 PM PDT 24
Peak memory	202768 kb
Host	smart-30039cc3-e7af-45d4-a941-5b90e8d311eb
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784320660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25 .sram_ctrl_stress_pipeline.784320660
Directory	/workspace/25.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3981475992
Short name	T854
Test name
Test status
Simulation time	554981716 ps
CPU time	47.85 seconds
Started	Jun 29 06:55:11 PM PDT 24
Finished	Jun 29 06:55:59 PM PDT 24
Peak memory	302212 kb
Host	smart-b03c19bf-e85a-4dd1-bb9d-1168d0c87b32
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981475992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.3981475992
Directory	/workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/26.sram_ctrl_access_during_key_req.3918883904
Short name	T37
Test name
Test status
Simulation time	3095861009 ps
CPU time	763.55 seconds
Started	Jun 29 06:55:17 PM PDT 24
Finished	Jun 29 07:08:01 PM PDT 24
Peak memory	374636 kb
Host	smart-d673fb57-52e6-47aa-8fbd-680b97a37863
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918883904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 26.sram_ctrl_access_during_key_req.3918883904
Directory	/workspace/26.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/26.sram_ctrl_alert_test.2739329227
Short name	T758
Test name
Test status
Simulation time	91685116 ps
CPU time	0.62 seconds
Started	Jun 29 06:55:15 PM PDT 24
Finished	Jun 29 06:55:16 PM PDT 24
Peak memory	202672 kb
Host	smart-6bde2c44-74b9-4598-b0f8-ca223b6138f4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739329227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.2739329227
Directory	/workspace/26.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/26.sram_ctrl_bijection.1948021125
Short name	T29
Test name
Test status
Simulation time	13885205891 ps
CPU time	82.26 seconds
Started	Jun 29 06:55:16 PM PDT 24
Finished	Jun 29 06:56:39 PM PDT 24
Peak memory	202956 kb
Host	smart-2ef49a3a-68f2-47c0-8ebc-b26a8cb142a3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948021125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection .1948021125
Directory	/workspace/26.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/26.sram_ctrl_executable.2353652693
Short name	T764
Test name
Test status
Simulation time	33136148503 ps
CPU time	562.6 seconds
Started	Jun 29 06:55:17 PM PDT 24
Finished	Jun 29 07:04:40 PM PDT 24
Peak memory	374324 kb
Host	smart-fc7a022f-e1ef-413b-b375-a6ea1aa7ed8b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353652693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executab le.2353652693
Directory	/workspace/26.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/26.sram_ctrl_lc_escalation.1580572430
Short name	T182
Test name
Test status
Simulation time	318300075 ps
CPU time	4.04 seconds
Started	Jun 29 06:55:18 PM PDT 24
Finished	Jun 29 06:55:22 PM PDT 24
Peak memory	202888 kb
Host	smart-76ff042a-263f-432c-a350-2456a71d643e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580572430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es calation.1580572430
Directory	/workspace/26.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/26.sram_ctrl_max_throughput.617263923
Short name	T793
Test name
Test status
Simulation time	569757665 ps
CPU time	93.73 seconds
Started	Jun 29 06:55:15 PM PDT 24
Finished	Jun 29 06:56:50 PM PDT 24
Peak memory	335652 kb
Host	smart-b63f471d-efc0-4e10-8448-01a345af9049
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617263923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 26.sram_ctrl_max_throughput.617263923
Directory	/workspace/26.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/26.sram_ctrl_mem_partial_access.3319707510
Short name	T39
Test name
Test status
Simulation time	161576793 ps
CPU time	3.07 seconds
Started	Jun 29 06:55:17 PM PDT 24
Finished	Jun 29 06:55:20 PM PDT 24
Peak memory	211068 kb
Host	smart-f5eae233-687d-485b-8cb4-21fe6896a216
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319707510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_mem_partial_access.3319707510
Directory	/workspace/26.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/26.sram_ctrl_mem_walk.1893977913
Short name	T388
Test name
Test status
Simulation time	464434845 ps
CPU time	10.64 seconds
Started	Jun 29 06:55:14 PM PDT 24
Finished	Jun 29 06:55:25 PM PDT 24
Peak memory	211048 kb
Host	smart-fb22f01c-5c9e-4d82-94b3-1bf1cb8ead51
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893977913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr l_mem_walk.1893977913
Directory	/workspace/26.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/26.sram_ctrl_multiple_keys.1597944751
Short name	T518
Test name
Test status
Simulation time	76980598383 ps
CPU time	1314.66 seconds
Started	Jun 29 06:55:18 PM PDT 24
Finished	Jun 29 07:17:13 PM PDT 24
Peak memory	372648 kb
Host	smart-4ce94e97-df13-41d9-9d3d-4aed9e0e48c7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597944751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi ple_keys.1597944751
Directory	/workspace/26.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/26.sram_ctrl_partial_access.4227900927
Short name	T550
Test name
Test status
Simulation time	997666273 ps
CPU time	19.27 seconds
Started	Jun 29 06:55:16 PM PDT 24
Finished	Jun 29 06:55:36 PM PDT 24
Peak memory	202876 kb
Host	smart-3611dddc-897a-4a5b-870b-fa068060c54b
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227900927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. sram_ctrl_partial_access.4227900927
Directory	/workspace/26.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3427076990
Short name	T682
Test name
Test status
Simulation time	13763612518 ps
CPU time	353.33 seconds
Started	Jun 29 06:55:16 PM PDT 24
Finished	Jun 29 07:01:10 PM PDT 24
Peak memory	202936 kb
Host	smart-adde8c0e-7a32-4097-a5e7-eeb9c2fd6489
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427076990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.sram_ctrl_partial_access_b2b.3427076990
Directory	/workspace/26.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/26.sram_ctrl_ram_cfg.3294067606
Short name	T259
Test name
Test status
Simulation time	77311877 ps
CPU time	0.76 seconds
Started	Jun 29 06:55:15 PM PDT 24
Finished	Jun 29 06:55:16 PM PDT 24
Peak memory	202844 kb
Host	smart-98fe9a59-4dac-4ddf-9c85-4325a2497c55
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294067606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.3294067606
Directory	/workspace/26.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/26.sram_ctrl_regwen.969203539
Short name	T911
Test name
Test status
Simulation time	20074600807 ps
CPU time	2184.68 seconds
Started	Jun 29 06:55:17 PM PDT 24
Finished	Jun 29 07:31:42 PM PDT 24
Peak memory	374660 kb
Host	smart-67ffd2dd-1b1a-439a-9502-11ab4015f15d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969203539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.969203539
Directory	/workspace/26.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/26.sram_ctrl_smoke.879998731
Short name	T727
Test name
Test status
Simulation time	793604492 ps
CPU time	9.41 seconds
Started	Jun 29 06:55:17 PM PDT 24
Finished	Jun 29 06:55:27 PM PDT 24
Peak memory	202864 kb
Host	smart-ccc094f4-f8cf-4b85-9b52-1e87b934e9c7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879998731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.879998731
Directory	/workspace/26.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.sram_ctrl_stress_all.3018931764
Short name	T277
Test name
Test status
Simulation time	96198536724 ps
CPU time	2602.76 seconds
Started	Jun 29 06:55:16 PM PDT 24
Finished	Jun 29 07:38:40 PM PDT 24
Peak memory	376184 kb
Host	smart-b638036a-3c0d-4986-ba4f-e743b3aee220
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018931764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 26.sram_ctrl_stress_all.3018931764
Directory	/workspace/26.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/26.sram_ctrl_stress_pipeline.48612579
Short name	T294
Test name
Test status
Simulation time	10724555554 ps
CPU time	314.22 seconds
Started	Jun 29 06:55:17 PM PDT 24
Finished	Jun 29 07:00:32 PM PDT 24
Peak memory	202972 kb
Host	smart-c9d391b3-b56d-4982-a73e-bf9f09cc799b
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48612579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. sram_ctrl_stress_pipeline.48612579
Directory	/workspace/26.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.1924114125
Short name	T223
Test name
Test status
Simulation time	1817972826 ps
CPU time	96.38 seconds
Started	Jun 29 06:55:14 PM PDT 24
Finished	Jun 29 06:56:51 PM PDT 24
Peak memory	368048 kb
Host	smart-1f137314-072a-48bd-8930-4bcc7b97e72b
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924114125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.1924114125
Directory	/workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/27.sram_ctrl_access_during_key_req.2623178137
Short name	T239
Test name
Test status
Simulation time	1391960845 ps
CPU time	132.14 seconds
Started	Jun 29 06:55:26 PM PDT 24
Finished	Jun 29 06:57:39 PM PDT 24
Peak memory	348552 kb
Host	smart-4846681f-179f-4f3a-8814-3e90af58a6c4
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623178137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 27.sram_ctrl_access_during_key_req.2623178137
Directory	/workspace/27.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/27.sram_ctrl_alert_test.691879416
Short name	T201
Test name
Test status
Simulation time	19318591 ps
CPU time	0.66 seconds
Started	Jun 29 06:55:25 PM PDT 24
Finished	Jun 29 06:55:26 PM PDT 24
Peak memory	202652 kb
Host	smart-c5217191-c0dd-4842-8255-938fdea7a97e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691879416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.691879416
Directory	/workspace/27.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.sram_ctrl_bijection.243202385
Short name	T447
Test name
Test status
Simulation time	11294484889 ps
CPU time	45.11 seconds
Started	Jun 29 06:55:24 PM PDT 24
Finished	Jun 29 06:56:09 PM PDT 24
Peak memory	202968 kb
Host	smart-dffd0528-2a75-48ca-b272-14ea284dd6b2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243202385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection. 243202385
Directory	/workspace/27.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/27.sram_ctrl_executable.2965514553
Short name	T662
Test name
Test status
Simulation time	1372576887 ps
CPU time	259.44 seconds
Started	Jun 29 06:55:26 PM PDT 24
Finished	Jun 29 06:59:46 PM PDT 24
Peak memory	373240 kb
Host	smart-f2023efc-08df-4a2a-bc1b-8e59b8cd06a7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965514553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab le.2965514553
Directory	/workspace/27.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/27.sram_ctrl_lc_escalation.1723351674
Short name	T21
Test name
Test status
Simulation time	1061332530 ps
CPU time	7.64 seconds
Started	Jun 29 06:55:22 PM PDT 24
Finished	Jun 29 06:55:30 PM PDT 24
Peak memory	202728 kb
Host	smart-bc134966-5e17-4113-8ac0-d8574de649de
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723351674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es calation.1723351674
Directory	/workspace/27.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/27.sram_ctrl_max_throughput.958071952
Short name	T278
Test name
Test status
Simulation time	43746311 ps
CPU time	1.56 seconds
Started	Jun 29 06:55:25 PM PDT 24
Finished	Jun 29 06:55:27 PM PDT 24
Peak memory	210972 kb
Host	smart-d8380e15-cd66-4e19-9c04-4b0b9c69c901
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958071952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 27.sram_ctrl_max_throughput.958071952
Directory	/workspace/27.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/27.sram_ctrl_mem_partial_access.2600408129
Short name	T801
Test name
Test status
Simulation time	3283242476 ps
CPU time	5.85 seconds
Started	Jun 29 06:55:25 PM PDT 24
Finished	Jun 29 06:55:31 PM PDT 24
Peak memory	211216 kb
Host	smart-3b6632b4-0754-471b-a0ae-6ffb2cebb96c
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600408129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_mem_partial_access.2600408129
Directory	/workspace/27.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/27.sram_ctrl_mem_walk.4014244338
Short name	T454
Test name
Test status
Simulation time	144728650 ps
CPU time	8.28 seconds
Started	Jun 29 06:55:23 PM PDT 24
Finished	Jun 29 06:55:32 PM PDT 24
Peak memory	211092 kb
Host	smart-6ed8a85a-375a-4d42-88da-e667970efb0d
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014244338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr l_mem_walk.4014244338
Directory	/workspace/27.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/27.sram_ctrl_multiple_keys.4194068991
Short name	T165
Test name
Test status
Simulation time	2650332375 ps
CPU time	750.55 seconds
Started	Jun 29 06:55:23 PM PDT 24
Finished	Jun 29 07:07:54 PM PDT 24
Peak memory	374508 kb
Host	smart-4f44d5b3-78de-4f73-b25c-4b290330fc1e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194068991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi ple_keys.4194068991
Directory	/workspace/27.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/27.sram_ctrl_partial_access.4143604893
Short name	T162
Test name
Test status
Simulation time	439384859 ps
CPU time	10.08 seconds
Started	Jun 29 06:55:22 PM PDT 24
Finished	Jun 29 06:55:33 PM PDT 24
Peak memory	237296 kb
Host	smart-be71e0bb-5ffb-460e-b8c8-1e17d17e64db
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143604893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27. sram_ctrl_partial_access.4143604893
Directory	/workspace/27.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.1562792817
Short name	T920
Test name
Test status
Simulation time	4710522911 ps
CPU time	354.37 seconds
Started	Jun 29 06:55:28 PM PDT 24
Finished	Jun 29 07:01:23 PM PDT 24
Peak memory	203180 kb
Host	smart-0e8d3e00-212c-4558-a981-5faec3c5c463
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562792817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.sram_ctrl_partial_access_b2b.1562792817
Directory	/workspace/27.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/27.sram_ctrl_ram_cfg.1165155575
Short name	T117
Test name
Test status
Simulation time	73730459 ps
CPU time	0.73 seconds
Started	Jun 29 06:55:21 PM PDT 24
Finished	Jun 29 06:55:22 PM PDT 24
Peak memory	202868 kb
Host	smart-cfc037e4-588a-4ba7-a294-2adca32b52b7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165155575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.1165155575
Directory	/workspace/27.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/27.sram_ctrl_regwen.675824100
Short name	T304
Test name
Test status
Simulation time	17027055118 ps
CPU time	821.3 seconds
Started	Jun 29 06:55:23 PM PDT 24
Finished	Jun 29 07:09:05 PM PDT 24
Peak memory	374968 kb
Host	smart-4882862c-3418-4fe1-a3a1-dd040592945f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675824100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.675824100
Directory	/workspace/27.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/27.sram_ctrl_smoke.4144263707
Short name	T358
Test name
Test status
Simulation time	130182487 ps
CPU time	7.12 seconds
Started	Jun 29 06:55:24 PM PDT 24
Finished	Jun 29 06:55:31 PM PDT 24
Peak memory	202796 kb
Host	smart-8fb50344-0be7-40ba-b2be-3a609cb7d64f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144263707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.4144263707
Directory	/workspace/27.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.sram_ctrl_stress_all.2266292271
Short name	T441
Test name
Test status
Simulation time	18961857249 ps
CPU time	6895.68 seconds
Started	Jun 29 06:55:24 PM PDT 24
Finished	Jun 29 08:50:20 PM PDT 24
Peak memory	375356 kb
Host	smart-f47f1ab6-d4cf-40b7-9900-8326f75ab381
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266292271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 27.sram_ctrl_stress_all.2266292271
Directory	/workspace/27.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.738917166
Short name	T109
Test name
Test status
Simulation time	1099461944 ps
CPU time	56.33 seconds
Started	Jun 29 06:55:30 PM PDT 24
Finished	Jun 29 06:56:27 PM PDT 24
Peak memory	304184 kb
Host	smart-0319f620-5618-41a1-b3ba-9e7dc95a6597
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=738917166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.738917166
Directory	/workspace/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.sram_ctrl_stress_pipeline.1785094709
Short name	T883
Test name
Test status
Simulation time	12189851942 ps
CPU time	290 seconds
Started	Jun 29 06:55:24 PM PDT 24
Finished	Jun 29 07:00:15 PM PDT 24
Peak memory	202992 kb
Host	smart-986fbdf2-f46c-4819-807d-d15702703a97
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785094709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_stress_pipeline.1785094709
Directory	/workspace/27.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.3980180264
Short name	T196
Test name
Test status
Simulation time	853920198 ps
CPU time	66.08 seconds
Started	Jun 29 06:55:25 PM PDT 24
Finished	Jun 29 06:56:31 PM PDT 24
Peak memory	342848 kb
Host	smart-7a215a04-91e4-4ecc-af03-6fb684a86c38
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980180264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.3980180264
Directory	/workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/28.sram_ctrl_access_during_key_req.3887388673
Short name	T785
Test name
Test status
Simulation time	1707016024 ps
CPU time	434.64 seconds
Started	Jun 29 06:55:32 PM PDT 24
Finished	Jun 29 07:02:47 PM PDT 24
Peak memory	362296 kb
Host	smart-258eaf8d-f4ee-4035-a67d-377eefb25b4c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887388673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 28.sram_ctrl_access_during_key_req.3887388673
Directory	/workspace/28.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/28.sram_ctrl_alert_test.3834230696
Short name	T782
Test name
Test status
Simulation time	37492499 ps
CPU time	0.66 seconds
Started	Jun 29 06:55:30 PM PDT 24
Finished	Jun 29 06:55:31 PM PDT 24
Peak memory	202656 kb
Host	smart-1211e454-a55a-46cf-8c1e-1ce30ffe4be8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834230696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.3834230696
Directory	/workspace/28.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.sram_ctrl_bijection.2485480554
Short name	T408
Test name
Test status
Simulation time	29642282119 ps
CPU time	74.48 seconds
Started	Jun 29 06:55:23 PM PDT 24
Finished	Jun 29 06:56:38 PM PDT 24
Peak memory	203000 kb
Host	smart-0b08deb9-13d8-46e5-a25f-004145cc0ca8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485480554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection .2485480554
Directory	/workspace/28.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/28.sram_ctrl_executable.3101876927
Short name	T655
Test name
Test status
Simulation time	10220034889 ps
CPU time	1042.12 seconds
Started	Jun 29 06:55:33 PM PDT 24
Finished	Jun 29 07:12:56 PM PDT 24
Peak memory	367604 kb
Host	smart-cfe3061e-83b1-4aa3-b127-be6fd4cbe74f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101876927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab le.3101876927
Directory	/workspace/28.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/28.sram_ctrl_lc_escalation.535933233
Short name	T784
Test name
Test status
Simulation time	6720807607 ps
CPU time	6.78 seconds
Started	Jun 29 06:55:30 PM PDT 24
Finished	Jun 29 06:55:37 PM PDT 24
Peak memory	202924 kb
Host	smart-45918812-723b-4b2a-966c-6ca7c53e2784
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535933233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_esc alation.535933233
Directory	/workspace/28.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/28.sram_ctrl_max_throughput.3535989014
Short name	T514
Test name
Test status
Simulation time	113787647 ps
CPU time	75.86 seconds
Started	Jun 29 06:55:25 PM PDT 24
Finished	Jun 29 06:56:41 PM PDT 24
Peak memory	330848 kb
Host	smart-ec3bc981-b013-4cc4-a8b6-e839a5c98498
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535989014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 28.sram_ctrl_max_throughput.3535989014
Directory	/workspace/28.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/28.sram_ctrl_mem_partial_access.3895935711
Short name	T346
Test name
Test status
Simulation time	333316640 ps
CPU time	5.22 seconds
Started	Jun 29 06:55:33 PM PDT 24
Finished	Jun 29 06:55:39 PM PDT 24
Peak memory	211076 kb
Host	smart-78de8771-fbb0-472b-8c38-bbb546f07840
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895935711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_mem_partial_access.3895935711
Directory	/workspace/28.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/28.sram_ctrl_mem_walk.291170091
Short name	T790
Test name
Test status
Simulation time	174056602 ps
CPU time	10.01 seconds
Started	Jun 29 06:55:31 PM PDT 24
Finished	Jun 29 06:55:42 PM PDT 24
Peak memory	211012 kb
Host	smart-cad1d3eb-cdc0-4264-951d-fa2da0569243
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291170091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl _mem_walk.291170091
Directory	/workspace/28.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/28.sram_ctrl_multiple_keys.1513172144
Short name	T656
Test name
Test status
Simulation time	2792564486 ps
CPU time	197.36 seconds
Started	Jun 29 06:55:23 PM PDT 24
Finished	Jun 29 06:58:40 PM PDT 24
Peak memory	346600 kb
Host	smart-c56b03ea-6eb2-4eb9-9d42-a0ec60850a3a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513172144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi ple_keys.1513172144
Directory	/workspace/28.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/28.sram_ctrl_partial_access.1877356158
Short name	T353
Test name
Test status
Simulation time	788128282 ps
CPU time	10.54 seconds
Started	Jun 29 06:55:25 PM PDT 24
Finished	Jun 29 06:55:36 PM PDT 24
Peak memory	235488 kb
Host	smart-06f4c824-a4f2-40ed-8fa3-5c08074b367c
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877356158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28. sram_ctrl_partial_access.1877356158
Directory	/workspace/28.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.4224909736
Short name	T594
Test name
Test status
Simulation time	12846414716 ps
CPU time	462.32 seconds
Started	Jun 29 06:55:26 PM PDT 24
Finished	Jun 29 07:03:08 PM PDT 24
Peak memory	202948 kb
Host	smart-8a8bf928-2026-46ad-ba1d-be63b55fef91
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224909736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 28.sram_ctrl_partial_access_b2b.4224909736
Directory	/workspace/28.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/28.sram_ctrl_ram_cfg.3536600422
Short name	T895
Test name
Test status
Simulation time	30020683 ps
CPU time	0.81 seconds
Started	Jun 29 06:55:31 PM PDT 24
Finished	Jun 29 06:55:32 PM PDT 24
Peak memory	202880 kb
Host	smart-73793328-cccc-4988-9be7-2f2683fe1a6c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536600422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.3536600422
Directory	/workspace/28.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/28.sram_ctrl_regwen.1460633861
Short name	T20
Test name
Test status
Simulation time	57990626159 ps
CPU time	1120.03 seconds
Started	Jun 29 06:55:33 PM PDT 24
Finished	Jun 29 07:14:14 PM PDT 24
Peak memory	368164 kb
Host	smart-9402332f-dbab-4530-81fe-0ff040c311b4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460633861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.1460633861
Directory	/workspace/28.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/28.sram_ctrl_smoke.1812893785
Short name	T901
Test name
Test status
Simulation time	929137731 ps
CPU time	12.16 seconds
Started	Jun 29 06:55:25 PM PDT 24
Finished	Jun 29 06:55:38 PM PDT 24
Peak memory	249860 kb
Host	smart-d8350d5f-a830-447e-ae69-7f2637e574e7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812893785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.1812893785
Directory	/workspace/28.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.sram_ctrl_stress_all.1111946137
Short name	T68
Test name
Test status
Simulation time	43339634709 ps
CPU time	1344.08 seconds
Started	Jun 29 06:55:32 PM PDT 24
Finished	Jun 29 07:17:57 PM PDT 24
Peak memory	375736 kb
Host	smart-d536ca08-c796-47b8-95c5-8b464ca37b39
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111946137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.sram_ctrl_stress_all.1111946137
Directory	/workspace/28.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1162570380
Short name	T615
Test name
Test status
Simulation time	27598958822 ps
CPU time	638.88 seconds
Started	Jun 29 06:55:33 PM PDT 24
Finished	Jun 29 07:06:12 PM PDT 24
Peak memory	375904 kb
Host	smart-aa476d3b-fe9a-4e49-bd2e-42018ec2de85
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1162570380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.1162570380
Directory	/workspace/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.sram_ctrl_stress_pipeline.698964938
Short name	T300
Test name
Test status
Simulation time	4570383875 ps
CPU time	233 seconds
Started	Jun 29 06:55:28 PM PDT 24
Finished	Jun 29 06:59:22 PM PDT 24
Peak memory	203160 kb
Host	smart-1e8d8d5e-af3c-464c-9697-b919ca4c2e1a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698964938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28 .sram_ctrl_stress_pipeline.698964938
Directory	/workspace/28.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.3865148646
Short name	T597
Test name
Test status
Simulation time	52270424 ps
CPU time	4.12 seconds
Started	Jun 29 06:55:30 PM PDT 24
Finished	Jun 29 06:55:35 PM PDT 24
Peak memory	223168 kb
Host	smart-890ada5b-6e2a-4f43-a2ce-a590be5cc38d
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865148646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.3865148646
Directory	/workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/29.sram_ctrl_access_during_key_req.4005298329
Short name	T84
Test name
Test status
Simulation time	3069570176 ps
CPU time	1072.93 seconds
Started	Jun 29 06:55:31 PM PDT 24
Finished	Jun 29 07:13:24 PM PDT 24
Peak memory	365560 kb
Host	smart-43b3bfba-e297-4db2-a9c5-da39c8457eb5
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005298329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 29.sram_ctrl_access_during_key_req.4005298329
Directory	/workspace/29.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/29.sram_ctrl_alert_test.2287430272
Short name	T669
Test name
Test status
Simulation time	14711308 ps
CPU time	0.65 seconds
Started	Jun 29 06:55:38 PM PDT 24
Finished	Jun 29 06:55:39 PM PDT 24
Peak memory	202616 kb
Host	smart-a8f2de4b-7d0c-425d-89df-cd1dd6656ac6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287430272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.2287430272
Directory	/workspace/29.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.sram_ctrl_bijection.3340575781
Short name	T67
Test name
Test status
Simulation time	7356543683 ps
CPU time	25.7 seconds
Started	Jun 29 06:55:29 PM PDT 24
Finished	Jun 29 06:55:55 PM PDT 24
Peak memory	202960 kb
Host	smart-ad292c80-818a-4f51-849a-2bad9b91c764
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340575781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection .3340575781
Directory	/workspace/29.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/29.sram_ctrl_executable.3357343069
Short name	T723
Test name
Test status
Simulation time	744483687 ps
CPU time	22.2 seconds
Started	Jun 29 06:55:33 PM PDT 24
Finished	Jun 29 06:55:55 PM PDT 24
Peak memory	266620 kb
Host	smart-12a9e02e-f22f-4242-93ab-7439ba46257f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357343069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab le.3357343069
Directory	/workspace/29.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/29.sram_ctrl_lc_escalation.3615368911
Short name	T555
Test name
Test status
Simulation time	2347456938 ps
CPU time	9.05 seconds
Started	Jun 29 06:55:31 PM PDT 24
Finished	Jun 29 06:55:41 PM PDT 24
Peak memory	202932 kb
Host	smart-871ed529-6d87-4f5f-a52a-52b6784d8380
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615368911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es calation.3615368911
Directory	/workspace/29.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/29.sram_ctrl_max_throughput.3065385764
Short name	T158
Test name
Test status
Simulation time	154840712 ps
CPU time	2.18 seconds
Started	Jun 29 06:55:31 PM PDT 24
Finished	Jun 29 06:55:34 PM PDT 24
Peak memory	212040 kb
Host	smart-5d1ccac9-5227-47da-8c53-152ad7e1a083
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065385764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 29.sram_ctrl_max_throughput.3065385764
Directory	/workspace/29.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/29.sram_ctrl_mem_partial_access.2102678867
Short name	T608
Test name
Test status
Simulation time	399356704 ps
CPU time	6.15 seconds
Started	Jun 29 06:55:30 PM PDT 24
Finished	Jun 29 06:55:37 PM PDT 24
Peak memory	211128 kb
Host	smart-be9ac38d-99fe-47ca-a651-04ef410f059b
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102678867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_mem_partial_access.2102678867
Directory	/workspace/29.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/29.sram_ctrl_mem_walk.1237716961
Short name	T268
Test name
Test status
Simulation time	529603441 ps
CPU time	8.61 seconds
Started	Jun 29 06:55:32 PM PDT 24
Finished	Jun 29 06:55:41 PM PDT 24
Peak memory	211080 kb
Host	smart-df96f60a-0bac-4c8f-9623-f9cbe6108214
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237716961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr l_mem_walk.1237716961
Directory	/workspace/29.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/29.sram_ctrl_multiple_keys.704655857
Short name	T250
Test name
Test status
Simulation time	12432713539 ps
CPU time	1356.85 seconds
Started	Jun 29 06:55:32 PM PDT 24
Finished	Jun 29 07:18:09 PM PDT 24
Peak memory	373016 kb
Host	smart-84c5f21b-38ee-4447-9c34-4bbbd8b0431e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704655857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multip le_keys.704655857
Directory	/workspace/29.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/29.sram_ctrl_partial_access.614435135
Short name	T336
Test name
Test status
Simulation time	108546557 ps
CPU time	6.23 seconds
Started	Jun 29 06:55:30 PM PDT 24
Finished	Jun 29 06:55:37 PM PDT 24
Peak memory	227752 kb
Host	smart-0e8397fa-3c72-4433-aa83-f00bddf6feef
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614435135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.s ram_ctrl_partial_access.614435135
Directory	/workspace/29.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.3541940011
Short name	T548
Test name
Test status
Simulation time	67730288717 ps
CPU time	446.98 seconds
Started	Jun 29 06:55:31 PM PDT 24
Finished	Jun 29 07:02:59 PM PDT 24
Peak memory	202896 kb
Host	smart-6efe5d98-5fb3-4b04-9727-2327ef46c4c4
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541940011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 29.sram_ctrl_partial_access_b2b.3541940011
Directory	/workspace/29.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/29.sram_ctrl_ram_cfg.960365682
Short name	T450
Test name
Test status
Simulation time	81625125 ps
CPU time	0.73 seconds
Started	Jun 29 06:55:31 PM PDT 24
Finished	Jun 29 06:55:33 PM PDT 24
Peak memory	202844 kb
Host	smart-56f755db-3077-41cb-8a19-4d9edf37d04f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960365682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.960365682
Directory	/workspace/29.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/29.sram_ctrl_regwen.769752495
Short name	T194
Test name
Test status
Simulation time	17430168459 ps
CPU time	1992.73 seconds
Started	Jun 29 06:55:33 PM PDT 24
Finished	Jun 29 07:28:47 PM PDT 24
Peak memory	374732 kb
Host	smart-32935382-106a-4620-8c76-5fd53c3e8436
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769752495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.769752495
Directory	/workspace/29.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/29.sram_ctrl_smoke.1542210620
Short name	T797
Test name
Test status
Simulation time	639879904 ps
CPU time	15.03 seconds
Started	Jun 29 06:55:30 PM PDT 24
Finished	Jun 29 06:55:46 PM PDT 24
Peak memory	202792 kb
Host	smart-12690229-d0cd-419f-adf2-503fbf9d02aa
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542210620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.1542210620
Directory	/workspace/29.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.sram_ctrl_stress_all.2182811842
Short name	T939
Test name
Test status
Simulation time	22777844403 ps
CPU time	3908.45 seconds
Started	Jun 29 06:55:33 PM PDT 24
Finished	Jun 29 08:00:43 PM PDT 24
Peak memory	385080 kb
Host	smart-706c1584-eae5-4226-a8bb-75190ed245f0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182811842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 29.sram_ctrl_stress_all.2182811842
Directory	/workspace/29.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.519304624
Short name	T617
Test name
Test status
Simulation time	644139896 ps
CPU time	280.44 seconds
Started	Jun 29 06:55:29 PM PDT 24
Finished	Jun 29 07:00:10 PM PDT 24
Peak memory	372720 kb
Host	smart-53526922-2774-45bf-b6b5-563e18f31b3e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=519304624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.519304624
Directory	/workspace/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.sram_ctrl_stress_pipeline.3731829115
Short name	T361
Test name
Test status
Simulation time	1582957490 ps
CPU time	118.92 seconds
Started	Jun 29 06:55:32 PM PDT 24
Finished	Jun 29 06:57:32 PM PDT 24
Peak memory	202828 kb
Host	smart-44101533-b6eb-4770-aaa1-e6c2c59edcee
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731829115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_stress_pipeline.3731829115
Directory	/workspace/29.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3722346636
Short name	T241
Test name
Test status
Simulation time	148621258 ps
CPU time	4.83 seconds
Started	Jun 29 06:55:34 PM PDT 24
Finished	Jun 29 06:55:39 PM PDT 24
Peak memory	226508 kb
Host	smart-a9440804-ce8d-4a01-a3a6-ef0823c3ea74
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722346636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.3722346636
Directory	/workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/3.sram_ctrl_access_during_key_req.1312511604
Short name	T792
Test name
Test status
Simulation time	8534802011 ps
CPU time	938.1 seconds
Started	Jun 29 06:53:59 PM PDT 24
Finished	Jun 29 07:09:38 PM PDT 24
Peak memory	365752 kb
Host	smart-9e68051f-5309-47f8-8803-010c3d3e57c1
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312511604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_access_during_key_req.1312511604
Directory	/workspace/3.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/3.sram_ctrl_alert_test.4047957095
Short name	T725
Test name
Test status
Simulation time	57958544 ps
CPU time	0.69 seconds
Started	Jun 29 06:53:56 PM PDT 24
Finished	Jun 29 06:53:58 PM PDT 24
Peak memory	202600 kb
Host	smart-9c50fe89-1b19-4fc5-b60d-34e57acd3fc7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047957095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.4047957095
Directory	/workspace/3.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.sram_ctrl_bijection.3184032423
Short name	T842
Test name
Test status
Simulation time	4354151032 ps
CPU time	65.56 seconds
Started	Jun 29 06:53:56 PM PDT 24
Finished	Jun 29 06:55:02 PM PDT 24
Peak memory	202908 kb
Host	smart-f6624ca3-51ca-4cee-bdef-e44c278927cb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184032423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection. 3184032423
Directory	/workspace/3.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/3.sram_ctrl_executable.4098591083
Short name	T639
Test name
Test status
Simulation time	6831268215 ps
CPU time	521.96 seconds
Started	Jun 29 06:53:58 PM PDT 24
Finished	Jun 29 07:02:41 PM PDT 24
Peak memory	351152 kb
Host	smart-cf28efbc-c233-465e-b326-4ffff5df1795
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098591083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl e.4098591083
Directory	/workspace/3.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/3.sram_ctrl_lc_escalation.3309337674
Short name	T274
Test name
Test status
Simulation time	664597823 ps
CPU time	8.93 seconds
Started	Jun 29 06:53:55 PM PDT 24
Finished	Jun 29 06:54:05 PM PDT 24
Peak memory	202868 kb
Host	smart-d06a72f7-3742-44b4-ac53-62934afb03ab
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309337674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc alation.3309337674
Directory	/workspace/3.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/3.sram_ctrl_max_throughput.1329716718
Short name	T422
Test name
Test status
Simulation time	139182342 ps
CPU time	103.75 seconds
Started	Jun 29 06:53:59 PM PDT 24
Finished	Jun 29 06:55:43 PM PDT 24
Peak memory	357056 kb
Host	smart-b8d0c3cc-a474-4dbb-8edb-0c89fc300611
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329716718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_max_throughput.1329716718
Directory	/workspace/3.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/3.sram_ctrl_mem_partial_access.3738245225
Short name	T684
Test name
Test status
Simulation time	305828651 ps
CPU time	5.7 seconds
Started	Jun 29 06:54:05 PM PDT 24
Finished	Jun 29 06:54:12 PM PDT 24
Peak memory	211000 kb
Host	smart-0f81f2a9-6ceb-4d30-bbcb-65c1dc4558d5
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738245225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_mem_partial_access.3738245225
Directory	/workspace/3.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/3.sram_ctrl_mem_walk.142196716
Short name	T405
Test name
Test status
Simulation time	1332310719 ps
CPU time	6.23 seconds
Started	Jun 29 06:53:57 PM PDT 24
Finished	Jun 29 06:54:05 PM PDT 24
Peak memory	211056 kb
Host	smart-b9b1bb2f-5a9d-4109-86dc-5d6cd17c5708
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142196716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ mem_walk.142196716
Directory	/workspace/3.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/3.sram_ctrl_multiple_keys.900702775
Short name	T849
Test name
Test status
Simulation time	58601817461 ps
CPU time	1611.41 seconds
Started	Jun 29 06:53:57 PM PDT 24
Finished	Jun 29 07:20:50 PM PDT 24
Peak memory	364496 kb
Host	smart-f4aad5fd-25eb-4cb9-8672-e168cc9a4c90
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900702775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multipl e_keys.900702775
Directory	/workspace/3.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/3.sram_ctrl_partial_access.2644615765
Short name	T588
Test name
Test status
Simulation time	5165511622 ps
CPU time	66.4 seconds
Started	Jun 29 06:53:59 PM PDT 24
Finished	Jun 29 06:55:06 PM PDT 24
Peak memory	327416 kb
Host	smart-eba4478f-a92d-4953-ba46-13f86ebb013f
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644615765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s ram_ctrl_partial_access.2644615765
Directory	/workspace/3.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.4035179538
Short name	T677
Test name
Test status
Simulation time	11235254109 ps
CPU time	181.28 seconds
Started	Jun 29 06:53:56 PM PDT 24
Finished	Jun 29 06:56:58 PM PDT 24
Peak memory	202920 kb
Host	smart-aef4a0ef-d356-4c07-9cbf-a7d0f81a7d3e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035179538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 3.sram_ctrl_partial_access_b2b.4035179538
Directory	/workspace/3.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/3.sram_ctrl_ram_cfg.2251481999
Short name	T912
Test name
Test status
Simulation time	76049374 ps
CPU time	0.77 seconds
Started	Jun 29 06:53:58 PM PDT 24
Finished	Jun 29 06:54:00 PM PDT 24
Peak memory	202852 kb
Host	smart-e00f65e8-ed40-423d-a616-3fe5d5b71b73
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251481999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.2251481999
Directory	/workspace/3.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/3.sram_ctrl_regwen.1158234790
Short name	T431
Test name
Test status
Simulation time	12875281015 ps
CPU time	760.94 seconds
Started	Jun 29 06:53:56 PM PDT 24
Finished	Jun 29 07:06:38 PM PDT 24
Peak memory	364160 kb
Host	smart-a589f03b-ec53-4a26-961b-a42425f41f81
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158234790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.1158234790
Directory	/workspace/3.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/3.sram_ctrl_sec_cm.4257640475
Short name	T17
Test name
Test status
Simulation time	148972317 ps
CPU time	1.94 seconds
Started	Jun 29 06:53:59 PM PDT 24
Finished	Jun 29 06:54:02 PM PDT 24
Peak memory	222188 kb
Host	smart-767afe11-a34e-4ea2-a373-260d9a7395fc
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257640475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.4257640475
Directory	/workspace/3.sram_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/3.sram_ctrl_smoke.3304426488
Short name	T546
Test name
Test status
Simulation time	676922778 ps
CPU time	14.15 seconds
Started	Jun 29 06:53:56 PM PDT 24
Finished	Jun 29 06:54:11 PM PDT 24
Peak memory	250796 kb
Host	smart-3e6362e9-664c-4af8-a638-0cf64127d237
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304426488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.3304426488
Directory	/workspace/3.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.sram_ctrl_stress_all.1147156136
Short name	T208
Test name
Test status
Simulation time	8221896207 ps
CPU time	2984.06 seconds
Started	Jun 29 06:54:00 PM PDT 24
Finished	Jun 29 07:43:45 PM PDT 24
Peak memory	375168 kb
Host	smart-7d45dff6-ab6a-43d4-b661-7e5c13e55041
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147156136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 3.sram_ctrl_stress_all.1147156136
Directory	/workspace/3.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.4046295694
Short name	T724
Test name
Test status
Simulation time	122073897 ps
CPU time	9.41 seconds
Started	Jun 29 06:53:56 PM PDT 24
Finished	Jun 29 06:54:06 PM PDT 24
Peak memory	211140 kb
Host	smart-9b52ae45-b11d-4144-9e8f-e80cfb01f8ea
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4046295694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.4046295694
Directory	/workspace/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.sram_ctrl_stress_pipeline.1780160369
Short name	T105
Test name
Test status
Simulation time	4896437397 ps
CPU time	124.46 seconds
Started	Jun 29 06:53:59 PM PDT 24
Finished	Jun 29 06:56:04 PM PDT 24
Peak memory	202952 kb
Host	smart-abadb958-3a66-44ee-b377-ca49e4185ae6
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780160369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_stress_pipeline.1780160369
Directory	/workspace/3.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.706644258
Short name	T256
Test name
Test status
Simulation time	72984590 ps
CPU time	1.38 seconds
Started	Jun 29 06:53:58 PM PDT 24
Finished	Jun 29 06:54:00 PM PDT 24
Peak memory	211020 kb
Host	smart-d948ba76-5d0b-42d8-821c-ddf1e7f24865
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706644258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_throughput_w_partial_write.706644258
Directory	/workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/30.sram_ctrl_access_during_key_req.1615043206
Short name	T240
Test name
Test status
Simulation time	2354747572 ps
CPU time	431.56 seconds
Started	Jun 29 06:55:38 PM PDT 24
Finished	Jun 29 07:02:50 PM PDT 24
Peak memory	352120 kb
Host	smart-c84a8147-6893-4012-af8d-cf60a1693d7e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615043206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 30.sram_ctrl_access_during_key_req.1615043206
Directory	/workspace/30.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/30.sram_ctrl_alert_test.3608761317
Short name	T328
Test name
Test status
Simulation time	35931281 ps
CPU time	0.63 seconds
Started	Jun 29 06:55:38 PM PDT 24
Finished	Jun 29 06:55:39 PM PDT 24
Peak memory	202248 kb
Host	smart-8ca6b8d0-0d51-421f-8df8-0b4bd6564db8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608761317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.3608761317
Directory	/workspace/30.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/30.sram_ctrl_bijection.229421543
Short name	T860
Test name
Test status
Simulation time	1719315443 ps
CPU time	28.63 seconds
Started	Jun 29 06:55:39 PM PDT 24
Finished	Jun 29 06:56:08 PM PDT 24
Peak memory	202760 kb
Host	smart-0f9434e3-ed96-4978-a786-5177edd423d5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229421543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection. 229421543
Directory	/workspace/30.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/30.sram_ctrl_executable.4026371971
Short name	T530
Test name
Test status
Simulation time	2554039970 ps
CPU time	1042.12 seconds
Started	Jun 29 06:55:39 PM PDT 24
Finished	Jun 29 07:13:02 PM PDT 24
Peak memory	374764 kb
Host	smart-65c73ee4-202b-4820-87bd-10f4276d53aa
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026371971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab le.4026371971
Directory	/workspace/30.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/30.sram_ctrl_lc_escalation.4161801561
Short name	T750
Test name
Test status
Simulation time	751578724 ps
CPU time	4.79 seconds
Started	Jun 29 06:55:39 PM PDT 24
Finished	Jun 29 06:55:44 PM PDT 24
Peak memory	211012 kb
Host	smart-5b6f809a-c645-4cee-ac6a-94cc93a93287
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161801561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es calation.4161801561
Directory	/workspace/30.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/30.sram_ctrl_max_throughput.1111971951
Short name	T712
Test name
Test status
Simulation time	424414870 ps
CPU time	76.48 seconds
Started	Jun 29 06:55:41 PM PDT 24
Finished	Jun 29 06:56:58 PM PDT 24
Peak memory	331176 kb
Host	smart-d42d2cd1-61cf-4961-b78d-1e91f31db179
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111971951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 30.sram_ctrl_max_throughput.1111971951
Directory	/workspace/30.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/30.sram_ctrl_mem_partial_access.1084987523
Short name	T49
Test name
Test status
Simulation time	213405789 ps
CPU time	3.53 seconds
Started	Jun 29 06:55:39 PM PDT 24
Finished	Jun 29 06:55:43 PM PDT 24
Peak memory	211068 kb
Host	smart-f18160b4-7db9-463d-86c8-c11b78994425
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084987523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_mem_partial_access.1084987523
Directory	/workspace/30.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/30.sram_ctrl_mem_walk.1679139151
Short name	T602
Test name
Test status
Simulation time	713014668 ps
CPU time	9.91 seconds
Started	Jun 29 06:55:38 PM PDT 24
Finished	Jun 29 06:55:49 PM PDT 24
Peak memory	211116 kb
Host	smart-fcfa6552-57d2-4815-8b5f-e31f6e78587d
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679139151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr l_mem_walk.1679139151
Directory	/workspace/30.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/30.sram_ctrl_multiple_keys.354076013
Short name	T178
Test name
Test status
Simulation time	1520004133 ps
CPU time	103.71 seconds
Started	Jun 29 06:55:41 PM PDT 24
Finished	Jun 29 06:57:25 PM PDT 24
Peak memory	324612 kb
Host	smart-d1b31840-26b9-4c62-85cd-556ba660850a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354076013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multip le_keys.354076013
Directory	/workspace/30.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/30.sram_ctrl_partial_access.3751908043
Short name	T645
Test name
Test status
Simulation time	350603113 ps
CPU time	26.57 seconds
Started	Jun 29 06:55:39 PM PDT 24
Finished	Jun 29 06:56:07 PM PDT 24
Peak memory	271456 kb
Host	smart-29e8e8f9-d6ce-4c3e-a6cb-487717a42763
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751908043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30. sram_ctrl_partial_access.3751908043
Directory	/workspace/30.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2609209627
Short name	T538
Test name
Test status
Simulation time	14364874937 ps
CPU time	413.87 seconds
Started	Jun 29 06:55:39 PM PDT 24
Finished	Jun 29 07:02:33 PM PDT 24
Peak memory	202892 kb
Host	smart-bf650eb1-1187-4bed-a1fb-cc000c52ddb4
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609209627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_partial_access_b2b.2609209627
Directory	/workspace/30.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/30.sram_ctrl_ram_cfg.3132397195
Short name	T689
Test name
Test status
Simulation time	332281991 ps
CPU time	0.86 seconds
Started	Jun 29 06:55:39 PM PDT 24
Finished	Jun 29 06:55:41 PM PDT 24
Peak memory	202868 kb
Host	smart-27cda2a2-089e-4da0-8874-3521acb6e09d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132397195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.3132397195
Directory	/workspace/30.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/30.sram_ctrl_regwen.2997228548
Short name	T344
Test name
Test status
Simulation time	5801268644 ps
CPU time	1496.74 seconds
Started	Jun 29 06:55:40 PM PDT 24
Finished	Jun 29 07:20:37 PM PDT 24
Peak memory	374704 kb
Host	smart-94a49458-ccb3-4a60-b100-beed33007d1d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997228548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.2997228548
Directory	/workspace/30.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/30.sram_ctrl_smoke.3293252051
Short name	T611
Test name
Test status
Simulation time	2053957646 ps
CPU time	11.6 seconds
Started	Jun 29 06:55:38 PM PDT 24
Finished	Jun 29 06:55:50 PM PDT 24
Peak memory	202780 kb
Host	smart-fc04e64e-e44b-49ea-8a93-1ad2152d8a6a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293252051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.3293252051
Directory	/workspace/30.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/30.sram_ctrl_stress_all.678883603
Short name	T788
Test name
Test status
Simulation time	46519567416 ps
CPU time	4086.21 seconds
Started	Jun 29 06:55:40 PM PDT 24
Finished	Jun 29 08:03:47 PM PDT 24
Peak memory	376744 kb
Host	smart-90864830-751f-49ef-a2d4-c98e9e8fbf8e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678883603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_stress_all.678883603
Directory	/workspace/30.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.200194767
Short name	T45
Test name
Test status
Simulation time	889404306 ps
CPU time	37.8 seconds
Started	Jun 29 06:55:38 PM PDT 24
Finished	Jun 29 06:56:16 PM PDT 24
Peak memory	263268 kb
Host	smart-d2c23009-5901-4aad-9127-d008fe1882a2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=200194767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.200194767
Directory	/workspace/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.sram_ctrl_stress_pipeline.926581093
Short name	T212
Test name
Test status
Simulation time	5411074993 ps
CPU time	265.4 seconds
Started	Jun 29 06:55:38 PM PDT 24
Finished	Jun 29 07:00:04 PM PDT 24
Peak memory	202940 kb
Host	smart-73d8c6d2-6b5d-4159-a1ab-a24df22833d2
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926581093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30 .sram_ctrl_stress_pipeline.926581093
Directory	/workspace/30.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.3585381962
Short name	T399
Test name
Test status
Simulation time	122758427 ps
CPU time	8.71 seconds
Started	Jun 29 06:55:39 PM PDT 24
Finished	Jun 29 06:55:48 PM PDT 24
Peak memory	238976 kb
Host	smart-3e8a6075-ade9-41c6-9174-322dd3af33c6
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585381962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.3585381962
Directory	/workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/31.sram_ctrl_access_during_key_req.2320615175
Short name	T296
Test name
Test status
Simulation time	15306063992 ps
CPU time	1328.2 seconds
Started	Jun 29 06:55:48 PM PDT 24
Finished	Jun 29 07:17:56 PM PDT 24
Peak memory	372668 kb
Host	smart-3afff51d-ae8c-470b-9d43-940d8b8eb472
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320615175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 31.sram_ctrl_access_during_key_req.2320615175
Directory	/workspace/31.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/31.sram_ctrl_alert_test.2193307710
Short name	T844
Test name
Test status
Simulation time	31565242 ps
CPU time	0.64 seconds
Started	Jun 29 06:55:48 PM PDT 24
Finished	Jun 29 06:55:49 PM PDT 24
Peak memory	202632 kb
Host	smart-d664d0dc-d40c-4694-9755-549ce01852ea
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193307710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.2193307710
Directory	/workspace/31.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.sram_ctrl_bijection.3501379847
Short name	T257
Test name
Test status
Simulation time	10168577641 ps
CPU time	82.73 seconds
Started	Jun 29 06:55:38 PM PDT 24
Finished	Jun 29 06:57:01 PM PDT 24
Peak memory	202924 kb
Host	smart-aa678d88-51b8-4d6e-8d60-8f3771c80511
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501379847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection .3501379847
Directory	/workspace/31.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/31.sram_ctrl_executable.965562211
Short name	T303
Test name
Test status
Simulation time	896833949 ps
CPU time	49.03 seconds
Started	Jun 29 06:55:47 PM PDT 24
Finished	Jun 29 06:56:36 PM PDT 24
Peak memory	265260 kb
Host	smart-98bb9af8-0c31-4adf-bef6-25c40c84de12
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965562211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executabl e.965562211
Directory	/workspace/31.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/31.sram_ctrl_lc_escalation.1445216757
Short name	T440
Test name
Test status
Simulation time	1785994919 ps
CPU time	4.99 seconds
Started	Jun 29 06:55:51 PM PDT 24
Finished	Jun 29 06:55:57 PM PDT 24
Peak memory	211040 kb
Host	smart-67c2c204-b100-4e9e-9a90-bad51cbb50ab
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445216757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es calation.1445216757
Directory	/workspace/31.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/31.sram_ctrl_max_throughput.2811351696
Short name	T280
Test name
Test status
Simulation time	294802095 ps
CPU time	21.03 seconds
Started	Jun 29 06:55:48 PM PDT 24
Finished	Jun 29 06:56:09 PM PDT 24
Peak memory	268256 kb
Host	smart-9c8793bd-5b6b-4145-b80a-256c0bbe2fda
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811351696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 31.sram_ctrl_max_throughput.2811351696
Directory	/workspace/31.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/31.sram_ctrl_mem_partial_access.1465887020
Short name	T794
Test name
Test status
Simulation time	168535969 ps
CPU time	2.77 seconds
Started	Jun 29 06:55:50 PM PDT 24
Finished	Jun 29 06:55:53 PM PDT 24
Peak memory	211044 kb
Host	smart-5551faa7-103d-4464-835f-073c680db70d
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465887020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_mem_partial_access.1465887020
Directory	/workspace/31.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/31.sram_ctrl_mem_walk.1022904118
Short name	T875
Test name
Test status
Simulation time	453848046 ps
CPU time	11.15 seconds
Started	Jun 29 06:55:48 PM PDT 24
Finished	Jun 29 06:56:00 PM PDT 24
Peak memory	202864 kb
Host	smart-496ce078-446e-4aa3-8f10-28155b0d633a
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022904118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr l_mem_walk.1022904118
Directory	/workspace/31.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/31.sram_ctrl_multiple_keys.3749042754
Short name	T576
Test name
Test status
Simulation time	2698366927 ps
CPU time	253.7 seconds
Started	Jun 29 06:55:40 PM PDT 24
Finished	Jun 29 06:59:54 PM PDT 24
Peak memory	368104 kb
Host	smart-70e07f61-8997-4d79-b2ee-9156c50032e4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749042754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi ple_keys.3749042754
Directory	/workspace/31.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/31.sram_ctrl_partial_access.1977321714
Short name	T360
Test name
Test status
Simulation time	2173695649 ps
CPU time	11.76 seconds
Started	Jun 29 06:55:46 PM PDT 24
Finished	Jun 29 06:55:58 PM PDT 24
Peak memory	202908 kb
Host	smart-6f204cbf-d4a5-48db-9b3f-1770f504913c
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977321714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31. sram_ctrl_partial_access.1977321714
Directory	/workspace/31.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2374484997
Short name	T102
Test name
Test status
Simulation time	65507559276 ps
CPU time	443.62 seconds
Started	Jun 29 06:55:51 PM PDT 24
Finished	Jun 29 07:03:15 PM PDT 24
Peak memory	202900 kb
Host	smart-fba3b89a-0692-4f11-a56e-3308c6364452
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374484997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.sram_ctrl_partial_access_b2b.2374484997
Directory	/workspace/31.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/31.sram_ctrl_ram_cfg.2730518969
Short name	T823
Test name
Test status
Simulation time	222640781 ps
CPU time	0.75 seconds
Started	Jun 29 06:55:46 PM PDT 24
Finished	Jun 29 06:55:48 PM PDT 24
Peak memory	202784 kb
Host	smart-b1b0c688-4258-4ea3-8653-084e7bed0190
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730518969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.2730518969
Directory	/workspace/31.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/31.sram_ctrl_regwen.2146107234
Short name	T512
Test name
Test status
Simulation time	988648096 ps
CPU time	560.65 seconds
Started	Jun 29 06:55:47 PM PDT 24
Finished	Jun 29 07:05:09 PM PDT 24
Peak memory	369476 kb
Host	smart-9d1baab6-d945-409c-bd57-77703c606c09
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146107234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.2146107234
Directory	/workspace/31.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/31.sram_ctrl_smoke.3230618001
Short name	T778
Test name
Test status
Simulation time	112649582 ps
CPU time	79.47 seconds
Started	Jun 29 06:55:40 PM PDT 24
Finished	Jun 29 06:57:00 PM PDT 24
Peak memory	336604 kb
Host	smart-4f1811d3-48b6-4ecb-8d60-e2794fe83e5c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230618001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.3230618001
Directory	/workspace/31.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.sram_ctrl_stress_all.3274423899
Short name	T312
Test name
Test status
Simulation time	15506666656 ps
CPU time	1539.77 seconds
Started	Jun 29 06:55:47 PM PDT 24
Finished	Jun 29 07:21:28 PM PDT 24
Peak memory	372720 kb
Host	smart-dfd17030-0b4e-4d67-80d6-0e271312af18
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274423899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 31.sram_ctrl_stress_all.3274423899
Directory	/workspace/31.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1500534694
Short name	T113
Test name
Test status
Simulation time	1350927118 ps
CPU time	79.82 seconds
Started	Jun 29 06:55:46 PM PDT 24
Finished	Jun 29 06:57:07 PM PDT 24
Peak memory	293932 kb
Host	smart-c655f318-8454-43d0-ac7a-aca55c80d9de
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1500534694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.1500534694
Directory	/workspace/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.sram_ctrl_stress_pipeline.3756765966
Short name	T359
Test name
Test status
Simulation time	3420369459 ps
CPU time	156.3 seconds
Started	Jun 29 06:55:39 PM PDT 24
Finished	Jun 29 06:58:16 PM PDT 24
Peak memory	202948 kb
Host	smart-9d446212-5c6a-42c9-9b51-cede3493d5eb
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756765966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_stress_pipeline.3756765966
Directory	/workspace/31.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.355231598
Short name	T461
Test name
Test status
Simulation time	573624149 ps
CPU time	10.12 seconds
Started	Jun 29 06:55:47 PM PDT 24
Finished	Jun 29 06:55:58 PM PDT 24
Peak memory	239800 kb
Host	smart-83619740-8c0e-4987-be4b-4c3265cf378b
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355231598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 31.sram_ctrl_throughput_w_partial_write.355231598
Directory	/workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/32.sram_ctrl_alert_test.3738423127
Short name	T916
Test name
Test status
Simulation time	12966707 ps
CPU time	0.67 seconds
Started	Jun 29 06:55:54 PM PDT 24
Finished	Jun 29 06:55:56 PM PDT 24
Peak memory	202280 kb
Host	smart-7e43c4f9-9ae5-47f4-8b18-bfbe58d993b8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738423127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.3738423127
Directory	/workspace/32.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.sram_ctrl_bijection.1425083742
Short name	T413
Test name
Test status
Simulation time	418854860 ps
CPU time	26.32 seconds
Started	Jun 29 06:55:51 PM PDT 24
Finished	Jun 29 06:56:17 PM PDT 24
Peak memory	202800 kb
Host	smart-8baf1626-08c4-4dea-a831-1ea3dcfbfe48
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425083742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection .1425083742
Directory	/workspace/32.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/32.sram_ctrl_executable.2878453364
Short name	T513
Test name
Test status
Simulation time	4547621063 ps
CPU time	609.37 seconds
Started	Jun 29 06:55:47 PM PDT 24
Finished	Jun 29 07:05:57 PM PDT 24
Peak memory	369636 kb
Host	smart-bcc59eff-5f4b-454e-acc9-12afa69ffa2a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878453364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab le.2878453364
Directory	/workspace/32.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/32.sram_ctrl_lc_escalation.3112522343
Short name	T864
Test name
Test status
Simulation time	714793563 ps
CPU time	6.83 seconds
Started	Jun 29 06:55:48 PM PDT 24
Finished	Jun 29 06:55:55 PM PDT 24
Peak memory	214224 kb
Host	smart-561f4dbb-c01a-4e20-8ecd-c9a4117ba9b2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112522343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es calation.3112522343
Directory	/workspace/32.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/32.sram_ctrl_max_throughput.1824062745
Short name	T637
Test name
Test status
Simulation time	433892741 ps
CPU time	71.62 seconds
Started	Jun 29 06:55:50 PM PDT 24
Finished	Jun 29 06:57:02 PM PDT 24
Peak memory	340824 kb
Host	smart-8bdbfa53-a04f-4fb1-b769-065d30ecd480
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824062745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 32.sram_ctrl_max_throughput.1824062745
Directory	/workspace/32.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/32.sram_ctrl_mem_partial_access.1879613709
Short name	T258
Test name
Test status
Simulation time	90603501 ps
CPU time	5.07 seconds
Started	Jun 29 06:55:54 PM PDT 24
Finished	Jun 29 06:55:59 PM PDT 24
Peak memory	211104 kb
Host	smart-ae64598b-4c2a-43ec-9b9a-e4d9f871c7cb
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879613709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_mem_partial_access.1879613709
Directory	/workspace/32.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/32.sram_ctrl_mem_walk.4037068277
Short name	T436
Test name
Test status
Simulation time	2219443764 ps
CPU time	10.59 seconds
Started	Jun 29 06:55:50 PM PDT 24
Finished	Jun 29 06:56:02 PM PDT 24
Peak memory	211164 kb
Host	smart-9e1df992-1453-4ab0-9912-e652a8c9dc87
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037068277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr l_mem_walk.4037068277
Directory	/workspace/32.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/32.sram_ctrl_multiple_keys.3629521099
Short name	T145
Test name
Test status
Simulation time	16932376151 ps
CPU time	459.43 seconds
Started	Jun 29 06:55:46 PM PDT 24
Finished	Jun 29 07:03:26 PM PDT 24
Peak memory	375016 kb
Host	smart-0c31736a-32c7-4ba5-810b-1704313bf6d8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629521099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi ple_keys.3629521099
Directory	/workspace/32.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/32.sram_ctrl_partial_access.2324825748
Short name	T337
Test name
Test status
Simulation time	1722759319 ps
CPU time	4.05 seconds
Started	Jun 29 06:55:47 PM PDT 24
Finished	Jun 29 06:55:51 PM PDT 24
Peak memory	203032 kb
Host	smart-8d727eb4-31c5-43a5-b8f7-1bc51970ad42
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324825748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32. sram_ctrl_partial_access.2324825748
Directory	/workspace/32.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.471407840
Short name	T671
Test name
Test status
Simulation time	63166996932 ps
CPU time	374.93 seconds
Started	Jun 29 06:55:50 PM PDT 24
Finished	Jun 29 07:02:06 PM PDT 24
Peak memory	202964 kb
Host	smart-c276291b-8c72-448f-bb0d-863483479bbb
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471407840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 32.sram_ctrl_partial_access_b2b.471407840
Directory	/workspace/32.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/32.sram_ctrl_ram_cfg.2761331257
Short name	T821
Test name
Test status
Simulation time	27755593 ps
CPU time	0.79 seconds
Started	Jun 29 06:55:47 PM PDT 24
Finished	Jun 29 06:55:48 PM PDT 24
Peak memory	202868 kb
Host	smart-77806fbb-c375-4d44-9c41-a4904121b5f8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761331257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.2761331257
Directory	/workspace/32.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/32.sram_ctrl_regwen.245622807
Short name	T770
Test name
Test status
Simulation time	16389440559 ps
CPU time	843.62 seconds
Started	Jun 29 06:55:48 PM PDT 24
Finished	Jun 29 07:09:52 PM PDT 24
Peak memory	357232 kb
Host	smart-e7f447db-406c-4246-93de-07684a83f83d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245622807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.245622807
Directory	/workspace/32.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/32.sram_ctrl_smoke.3802675437
Short name	T262
Test name
Test status
Simulation time	250541366 ps
CPU time	10.43 seconds
Started	Jun 29 06:55:47 PM PDT 24
Finished	Jun 29 06:55:58 PM PDT 24
Peak memory	202856 kb
Host	smart-0160c345-3922-4144-ba8a-16212c52a069
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802675437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.3802675437
Directory	/workspace/32.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.sram_ctrl_stress_all.647609489
Short name	T197
Test name
Test status
Simulation time	88725240866 ps
CPU time	853.86 seconds
Started	Jun 29 06:55:55 PM PDT 24
Finished	Jun 29 07:10:09 PM PDT 24
Peak memory	332716 kb
Host	smart-c6063494-4655-4c99-a223-c4d4cf3c1a51
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647609489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_stress_all.647609489
Directory	/workspace/32.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1829856872
Short name	T52
Test name
Test status
Simulation time	1732920250 ps
CPU time	532.3 seconds
Started	Jun 29 06:55:54 PM PDT 24
Finished	Jun 29 07:04:47 PM PDT 24
Peak memory	371476 kb
Host	smart-73b76ad2-dc00-4112-8fe8-a009011b51bf
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1829856872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.1829856872
Directory	/workspace/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.sram_ctrl_stress_pipeline.3331898250
Short name	T307
Test name
Test status
Simulation time	6295895230 ps
CPU time	309.7 seconds
Started	Jun 29 06:55:50 PM PDT 24
Finished	Jun 29 07:01:01 PM PDT 24
Peak memory	202936 kb
Host	smart-7fe4bae9-fc86-4f2f-b2e7-8f6cc6ce6445
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331898250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_stress_pipeline.3331898250
Directory	/workspace/32.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3127773589
Short name	T213
Test name
Test status
Simulation time	750644044 ps
CPU time	50.77 seconds
Started	Jun 29 06:55:50 PM PDT 24
Finished	Jun 29 06:56:42 PM PDT 24
Peak memory	304048 kb
Host	smart-4d3fa131-2905-43e5-9e17-b795aa694b51
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127773589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.3127773589
Directory	/workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/33.sram_ctrl_access_during_key_req.1152278906
Short name	T772
Test name
Test status
Simulation time	881922927 ps
CPU time	284.38 seconds
Started	Jun 29 06:55:53 PM PDT 24
Finished	Jun 29 07:00:38 PM PDT 24
Peak memory	372472 kb
Host	smart-b952e725-a0f9-4bf1-b1fa-79b54fbec6d7
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152278906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 33.sram_ctrl_access_during_key_req.1152278906
Directory	/workspace/33.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/33.sram_ctrl_alert_test.175503149
Short name	T773
Test name
Test status
Simulation time	16099693 ps
CPU time	0.66 seconds
Started	Jun 29 06:55:54 PM PDT 24
Finished	Jun 29 06:55:56 PM PDT 24
Peak memory	202652 kb
Host	smart-a09ca4b7-33ee-4a05-b282-5e96cffb02ed
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175503149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.175503149
Directory	/workspace/33.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.sram_ctrl_bijection.3449544766
Short name	T367
Test name
Test status
Simulation time	425802357 ps
CPU time	26.17 seconds
Started	Jun 29 06:55:55 PM PDT 24
Finished	Jun 29 06:56:22 PM PDT 24
Peak memory	202808 kb
Host	smart-def436c4-2fe4-4094-8884-b11da2391e51
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449544766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection .3449544766
Directory	/workspace/33.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/33.sram_ctrl_executable.3889707868
Short name	T238
Test name
Test status
Simulation time	61185192291 ps
CPU time	1583.56 seconds
Started	Jun 29 06:55:54 PM PDT 24
Finished	Jun 29 07:22:19 PM PDT 24
Peak memory	373936 kb
Host	smart-bc91914d-0631-47a2-bd07-7d4cb0326115
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889707868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab le.3889707868
Directory	/workspace/33.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/33.sram_ctrl_lc_escalation.2188807711
Short name	T289
Test name
Test status
Simulation time	860769764 ps
CPU time	4.82 seconds
Started	Jun 29 06:55:54 PM PDT 24
Finished	Jun 29 06:55:59 PM PDT 24
Peak memory	202800 kb
Host	smart-7d77d426-01a0-412d-bd5e-ece5dc9ce085
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188807711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es calation.2188807711
Directory	/workspace/33.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/33.sram_ctrl_max_throughput.1007652495
Short name	T663
Test name
Test status
Simulation time	502822868 ps
CPU time	43.53 seconds
Started	Jun 29 06:55:54 PM PDT 24
Finished	Jun 29 06:56:38 PM PDT 24
Peak memory	300844 kb
Host	smart-60d680c8-6d59-43c0-90c6-a6e824ef0a6e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007652495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 33.sram_ctrl_max_throughput.1007652495
Directory	/workspace/33.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/33.sram_ctrl_mem_partial_access.2768165564
Short name	T595
Test name
Test status
Simulation time	168728987 ps
CPU time	2.68 seconds
Started	Jun 29 06:55:54 PM PDT 24
Finished	Jun 29 06:55:58 PM PDT 24
Peak memory	211044 kb
Host	smart-d83433da-3313-45bb-88ee-82cee3e15d53
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768165564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_mem_partial_access.2768165564
Directory	/workspace/33.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/33.sram_ctrl_mem_walk.767081424
Short name	T374
Test name
Test status
Simulation time	591222367 ps
CPU time	6 seconds
Started	Jun 29 06:55:54 PM PDT 24
Finished	Jun 29 06:56:01 PM PDT 24
Peak memory	211056 kb
Host	smart-2d57d5ea-9433-4ebe-a1b2-e630ac50baf3
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767081424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl _mem_walk.767081424
Directory	/workspace/33.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/33.sram_ctrl_multiple_keys.502035956
Short name	T473
Test name
Test status
Simulation time	5412204399 ps
CPU time	308.79 seconds
Started	Jun 29 06:55:56 PM PDT 24
Finished	Jun 29 07:01:05 PM PDT 24
Peak memory	339080 kb
Host	smart-dc52be1d-6200-4de2-a1db-efdc2daa2e62
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502035956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multip le_keys.502035956
Directory	/workspace/33.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/33.sram_ctrl_partial_access.287121929
Short name	T152
Test name
Test status
Simulation time	219035847 ps
CPU time	12.29 seconds
Started	Jun 29 06:55:54 PM PDT 24
Finished	Jun 29 06:56:07 PM PDT 24
Peak memory	202792 kb
Host	smart-416cc83c-0b07-4df3-bad6-fcd6491dbf2e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287121929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.s ram_ctrl_partial_access.287121929
Directory	/workspace/33.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2589976458
Short name	T591
Test name
Test status
Simulation time	2460203544 ps
CPU time	180.67 seconds
Started	Jun 29 06:55:54 PM PDT 24
Finished	Jun 29 06:58:55 PM PDT 24
Peak memory	202848 kb
Host	smart-8cf07176-d7fa-48f2-a34a-82bad0029d44
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589976458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 33.sram_ctrl_partial_access_b2b.2589976458
Directory	/workspace/33.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/33.sram_ctrl_ram_cfg.1058989746
Short name	T629
Test name
Test status
Simulation time	210732998 ps
CPU time	0.8 seconds
Started	Jun 29 06:55:53 PM PDT 24
Finished	Jun 29 06:55:54 PM PDT 24
Peak memory	202852 kb
Host	smart-1bdac51f-169a-489b-a2dd-161646421f6c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058989746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.1058989746
Directory	/workspace/33.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/33.sram_ctrl_regwen.1172245490
Short name	T465
Test name
Test status
Simulation time	52891728581 ps
CPU time	555.51 seconds
Started	Jun 29 06:55:54 PM PDT 24
Finished	Jun 29 07:05:10 PM PDT 24
Peak memory	374668 kb
Host	smart-d57b7913-9cdb-43c9-99db-fbe03b3f1c78
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172245490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.1172245490
Directory	/workspace/33.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/33.sram_ctrl_smoke.2496782852
Short name	T881
Test name
Test status
Simulation time	157404936 ps
CPU time	9.42 seconds
Started	Jun 29 06:55:57 PM PDT 24
Finished	Jun 29 06:56:07 PM PDT 24
Peak memory	202776 kb
Host	smart-6f552df0-3815-4589-b446-df3a77f2fe0b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496782852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.2496782852
Directory	/workspace/33.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.sram_ctrl_stress_all.2408729681
Short name	T679
Test name
Test status
Simulation time	196466926296 ps
CPU time	4312.97 seconds
Started	Jun 29 06:55:54 PM PDT 24
Finished	Jun 29 08:07:49 PM PDT 24
Peak memory	377020 kb
Host	smart-35f3c0f6-0cfb-4e7c-ab22-abbd6369c0b2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408729681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 33.sram_ctrl_stress_all.2408729681
Directory	/workspace/33.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/33.sram_ctrl_stress_pipeline.2720913106
Short name	T206
Test name
Test status
Simulation time	4766015792 ps
CPU time	241.3 seconds
Started	Jun 29 06:55:54 PM PDT 24
Finished	Jun 29 06:59:56 PM PDT 24
Peak memory	202912 kb
Host	smart-8645c4e2-c135-4d0a-a491-838cab5e477f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720913106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_stress_pipeline.2720913106
Directory	/workspace/33.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1754249417
Short name	T715
Test name
Test status
Simulation time	184283698 ps
CPU time	12.18 seconds
Started	Jun 29 06:55:54 PM PDT 24
Finished	Jun 29 06:56:08 PM PDT 24
Peak memory	252872 kb
Host	smart-cc6b52ff-6a1c-4c37-b58a-d75843a53a21
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754249417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.1754249417
Directory	/workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/34.sram_ctrl_access_during_key_req.3238272625
Short name	T824
Test name
Test status
Simulation time	15020932996 ps
CPU time	1754.57 seconds
Started	Jun 29 06:56:04 PM PDT 24
Finished	Jun 29 07:25:20 PM PDT 24
Peak memory	374716 kb
Host	smart-e4be40d8-1d65-481d-be9e-22bed54edd31
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238272625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 34.sram_ctrl_access_during_key_req.3238272625
Directory	/workspace/34.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/34.sram_ctrl_alert_test.2437436303
Short name	T164
Test name
Test status
Simulation time	50657180 ps
CPU time	0.69 seconds
Started	Jun 29 06:56:04 PM PDT 24
Finished	Jun 29 06:56:06 PM PDT 24
Peak memory	202640 kb
Host	smart-ed216463-0722-4831-8b66-50577b7d8c06
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437436303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.2437436303
Directory	/workspace/34.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.sram_ctrl_bijection.1660516728
Short name	T651
Test name
Test status
Simulation time	619564673 ps
CPU time	22.41 seconds
Started	Jun 29 06:56:03 PM PDT 24
Finished	Jun 29 06:56:26 PM PDT 24
Peak memory	202804 kb
Host	smart-51b3d46e-aec8-4d46-836c-a7ed7b693762
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660516728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection .1660516728
Directory	/workspace/34.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/34.sram_ctrl_executable.2458404341
Short name	T96
Test name
Test status
Simulation time	97907976273 ps
CPU time	979.97 seconds
Started	Jun 29 06:56:04 PM PDT 24
Finished	Jun 29 07:12:25 PM PDT 24
Peak memory	374764 kb
Host	smart-99804323-cb98-42e3-8ca2-911350454c02
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458404341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab le.2458404341
Directory	/workspace/34.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/34.sram_ctrl_lc_escalation.125812885
Short name	T7
Test name
Test status
Simulation time	6385797143 ps
CPU time	7.07 seconds
Started	Jun 29 06:56:04 PM PDT 24
Finished	Jun 29 06:56:12 PM PDT 24
Peak memory	202936 kb
Host	smart-81bf7cfb-4b2b-4adf-b522-d9bc909401bc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125812885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_esc alation.125812885
Directory	/workspace/34.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/34.sram_ctrl_max_throughput.703655930
Short name	T3
Test name
Test status
Simulation time	80861376 ps
CPU time	17.68 seconds
Started	Jun 29 06:56:03 PM PDT 24
Finished	Jun 29 06:56:21 PM PDT 24
Peak memory	268228 kb
Host	smart-9d119951-7411-49d4-b105-aad046b53fca
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703655930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 34.sram_ctrl_max_throughput.703655930
Directory	/workspace/34.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/34.sram_ctrl_mem_partial_access.949542909
Short name	T376
Test name
Test status
Simulation time	427260946 ps
CPU time	3.3 seconds
Started	Jun 29 06:56:03 PM PDT 24
Finished	Jun 29 06:56:07 PM PDT 24
Peak memory	211132 kb
Host	smart-96ff31b0-93e6-4513-85f8-0574596097eb
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949542909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34 .sram_ctrl_mem_partial_access.949542909
Directory	/workspace/34.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/34.sram_ctrl_mem_walk.1010906568
Short name	T657
Test name
Test status
Simulation time	1759585074 ps
CPU time	10.95 seconds
Started	Jun 29 06:56:03 PM PDT 24
Finished	Jun 29 06:56:15 PM PDT 24
Peak memory	211064 kb
Host	smart-1856d201-e110-4ff3-8926-0167f15f3b17
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010906568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr l_mem_walk.1010906568
Directory	/workspace/34.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/34.sram_ctrl_multiple_keys.945508129
Short name	T352
Test name
Test status
Simulation time	3220958320 ps
CPU time	1345.97 seconds
Started	Jun 29 06:56:02 PM PDT 24
Finished	Jun 29 07:18:29 PM PDT 24
Peak memory	371684 kb
Host	smart-570198d3-9ff0-4ac3-a0c5-5ec04325134d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945508129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multip le_keys.945508129
Directory	/workspace/34.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/34.sram_ctrl_partial_access.3644226934
Short name	T680
Test name
Test status
Simulation time	118041209 ps
CPU time	30.03 seconds
Started	Jun 29 06:56:02 PM PDT 24
Finished	Jun 29 06:56:33 PM PDT 24
Peak memory	280528 kb
Host	smart-c82330d5-fbaa-49c8-8ae5-93475b324285
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644226934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34. sram_ctrl_partial_access.3644226934
Directory	/workspace/34.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2364702819
Short name	T414
Test name
Test status
Simulation time	12679674238 ps
CPU time	238.09 seconds
Started	Jun 29 06:56:04 PM PDT 24
Finished	Jun 29 07:00:03 PM PDT 24
Peak memory	202948 kb
Host	smart-06c435d6-eecd-4e66-a1fa-6b4cef157dc1
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364702819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 34.sram_ctrl_partial_access_b2b.2364702819
Directory	/workspace/34.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/34.sram_ctrl_ram_cfg.3583443268
Short name	T378
Test name
Test status
Simulation time	47171487 ps
CPU time	0.79 seconds
Started	Jun 29 06:56:03 PM PDT 24
Finished	Jun 29 06:56:04 PM PDT 24
Peak memory	202876 kb
Host	smart-4bb21089-0fc7-4e43-8290-dcec89b53490
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583443268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.3583443268
Directory	/workspace/34.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/34.sram_ctrl_regwen.4224861318
Short name	T925
Test name
Test status
Simulation time	8087495792 ps
CPU time	47.92 seconds
Started	Jun 29 06:56:02 PM PDT 24
Finished	Jun 29 06:56:50 PM PDT 24
Peak memory	230216 kb
Host	smart-cca427da-bf65-4426-a162-b5fec41100bf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224861318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.4224861318
Directory	/workspace/34.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/34.sram_ctrl_smoke.2352629411
Short name	T362
Test name
Test status
Simulation time	71393503 ps
CPU time	1.13 seconds
Started	Jun 29 06:55:55 PM PDT 24
Finished	Jun 29 06:55:57 PM PDT 24
Peak memory	202628 kb
Host	smart-9e549ed6-fa18-4208-a462-ceed9a1b4ce3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352629411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.2352629411
Directory	/workspace/34.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.sram_ctrl_stress_all.3963835291
Short name	T702
Test name
Test status
Simulation time	23439735260 ps
CPU time	1956.8 seconds
Started	Jun 29 06:56:02 PM PDT 24
Finished	Jun 29 07:28:40 PM PDT 24
Peak memory	377564 kb
Host	smart-a6cdc2c6-083b-4b05-8506-a3150ef77d51
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963835291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 34.sram_ctrl_stress_all.3963835291
Directory	/workspace/34.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/34.sram_ctrl_stress_pipeline.1249980128
Short name	T394
Test name
Test status
Simulation time	6523462287 ps
CPU time	303.67 seconds
Started	Jun 29 06:56:03 PM PDT 24
Finished	Jun 29 07:01:07 PM PDT 24
Peak memory	202940 kb
Host	smart-3e2455a9-207b-4136-b028-71e1377fceea
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249980128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_stress_pipeline.1249980128
Directory	/workspace/34.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3935725215
Short name	T467
Test name
Test status
Simulation time	237482270 ps
CPU time	1.63 seconds
Started	Jun 29 06:56:02 PM PDT 24
Finished	Jun 29 06:56:04 PM PDT 24
Peak memory	211044 kb
Host	smart-3d715561-03d3-4d1e-b3e1-2f8a8c7b38ad
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935725215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.3935725215
Directory	/workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/35.sram_ctrl_access_during_key_req.2152903973
Short name	T227
Test name
Test status
Simulation time	640596954 ps
CPU time	104.98 seconds
Started	Jun 29 06:56:10 PM PDT 24
Finished	Jun 29 06:57:55 PM PDT 24
Peak memory	341064 kb
Host	smart-acab5ded-a494-45b0-b344-88ca940f635b
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152903973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 35.sram_ctrl_access_during_key_req.2152903973
Directory	/workspace/35.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/35.sram_ctrl_alert_test.1423746169
Short name	T814
Test name
Test status
Simulation time	34319543 ps
CPU time	0.65 seconds
Started	Jun 29 06:56:09 PM PDT 24
Finished	Jun 29 06:56:10 PM PDT 24
Peak memory	202628 kb
Host	smart-404bbb69-fe2b-4d4e-90d3-97180adf82e7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423746169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.1423746169
Directory	/workspace/35.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.sram_ctrl_bijection.4131297766
Short name	T216
Test name
Test status
Simulation time	1005245882 ps
CPU time	66.82 seconds
Started	Jun 29 06:56:02 PM PDT 24
Finished	Jun 29 06:57:10 PM PDT 24
Peak memory	202836 kb
Host	smart-9970ef81-b2d7-480f-a930-1922ac7e5e95
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131297766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection .4131297766
Directory	/workspace/35.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/35.sram_ctrl_executable.2763664175
Short name	T252
Test name
Test status
Simulation time	11516642974 ps
CPU time	203.95 seconds
Started	Jun 29 06:56:08 PM PDT 24
Finished	Jun 29 06:59:32 PM PDT 24
Peak memory	353132 kb
Host	smart-10f993c5-b7bf-42d4-8bac-be756607a697
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763664175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab le.2763664175
Directory	/workspace/35.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/35.sram_ctrl_lc_escalation.952201967
Short name	T575
Test name
Test status
Simulation time	2576059462 ps
CPU time	7.92 seconds
Started	Jun 29 06:56:09 PM PDT 24
Finished	Jun 29 06:56:18 PM PDT 24
Peak memory	211136 kb
Host	smart-09532c15-5391-4f25-81ea-ac16adb8565c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952201967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_esc alation.952201967
Directory	/workspace/35.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/35.sram_ctrl_max_throughput.99607323
Short name	T292
Test name
Test status
Simulation time	515839779 ps
CPU time	142.14 seconds
Started	Jun 29 06:56:10 PM PDT 24
Finished	Jun 29 06:58:32 PM PDT 24
Peak memory	370468 kb
Host	smart-0232fced-222a-466d-838a-04ac899b7df0
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99607323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 35.sram_ctrl_max_throughput.99607323
Directory	/workspace/35.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/35.sram_ctrl_mem_partial_access.3882270576
Short name	T692
Test name
Test status
Simulation time	108007735 ps
CPU time	3.28 seconds
Started	Jun 29 06:56:10 PM PDT 24
Finished	Jun 29 06:56:14 PM PDT 24
Peak memory	211040 kb
Host	smart-a9b5feca-4f5e-4526-b78c-0577a6f7b140
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882270576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_mem_partial_access.3882270576
Directory	/workspace/35.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/35.sram_ctrl_mem_walk.1945522792
Short name	T769
Test name
Test status
Simulation time	887872870 ps
CPU time	10.93 seconds
Started	Jun 29 06:56:10 PM PDT 24
Finished	Jun 29 06:56:22 PM PDT 24
Peak memory	211000 kb
Host	smart-03a0414b-edfb-400e-beb5-5166d10a5a88
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945522792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr l_mem_walk.1945522792
Directory	/workspace/35.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/35.sram_ctrl_multiple_keys.3380131190
Short name	T798
Test name
Test status
Simulation time	4780240371 ps
CPU time	1116.65 seconds
Started	Jun 29 06:56:02 PM PDT 24
Finished	Jun 29 07:14:39 PM PDT 24
Peak memory	374744 kb
Host	smart-b8664361-0d2e-4b73-a0c6-b575a0953d59
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380131190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi ple_keys.3380131190
Directory	/workspace/35.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/35.sram_ctrl_partial_access.12324189
Short name	T170
Test name
Test status
Simulation time	665251778 ps
CPU time	12.94 seconds
Started	Jun 29 06:56:04 PM PDT 24
Finished	Jun 29 06:56:18 PM PDT 24
Peak memory	249560 kb
Host	smart-54138431-0315-4a71-a9c0-93132c19049e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12324189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sr am_ctrl_partial_access.12324189
Directory	/workspace/35.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3863256836
Short name	T714
Test name
Test status
Simulation time	9195759171 ps
CPU time	347.86 seconds
Started	Jun 29 06:56:11 PM PDT 24
Finished	Jun 29 07:01:59 PM PDT 24
Peak memory	202948 kb
Host	smart-0012b310-d5b2-4b92-b4f8-d33cdd1dff81
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863256836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 35.sram_ctrl_partial_access_b2b.3863256836
Directory	/workspace/35.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/35.sram_ctrl_ram_cfg.745354829
Short name	T741
Test name
Test status
Simulation time	78932363 ps
CPU time	0.79 seconds
Started	Jun 29 06:56:12 PM PDT 24
Finished	Jun 29 06:56:13 PM PDT 24
Peak memory	202884 kb
Host	smart-b8780c17-f1ca-44c3-8fcb-543a1c9c39bb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745354829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.745354829
Directory	/workspace/35.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/35.sram_ctrl_regwen.4152303919
Short name	T706
Test name
Test status
Simulation time	3686984024 ps
CPU time	778.81 seconds
Started	Jun 29 06:56:09 PM PDT 24
Finished	Jun 29 07:09:08 PM PDT 24
Peak memory	370624 kb
Host	smart-3f5a6fcc-0780-445b-af5a-15b687f28327
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152303919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.4152303919
Directory	/workspace/35.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/35.sram_ctrl_smoke.872762123
Short name	T263
Test name
Test status
Simulation time	901064880 ps
CPU time	11.52 seconds
Started	Jun 29 06:56:04 PM PDT 24
Finished	Jun 29 06:56:17 PM PDT 24
Peak memory	202764 kb
Host	smart-486e599a-f4b5-4bd1-9e9e-3ed6cdd1ab30
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872762123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.872762123
Directory	/workspace/35.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.sram_ctrl_stress_all.3574779486
Short name	T318
Test name
Test status
Simulation time	45282499829 ps
CPU time	6048.1 seconds
Started	Jun 29 06:56:10 PM PDT 24
Finished	Jun 29 08:37:00 PM PDT 24
Peak memory	375784 kb
Host	smart-4e7d287a-dd63-4c20-9331-b60e7ed56437
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574779486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 35.sram_ctrl_stress_all.3574779486
Directory	/workspace/35.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2550057069
Short name	T112
Test name
Test status
Simulation time	372508912 ps
CPU time	11.24 seconds
Started	Jun 29 06:56:10 PM PDT 24
Finished	Jun 29 06:56:22 PM PDT 24
Peak memory	211156 kb
Host	smart-7bc1e0f6-10c4-47ed-a1ab-21bbdb912444
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2550057069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.2550057069
Directory	/workspace/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.sram_ctrl_stress_pipeline.1003481526
Short name	T389
Test name
Test status
Simulation time	2481405207 ps
CPU time	163.04 seconds
Started	Jun 29 06:56:04 PM PDT 24
Finished	Jun 29 06:58:48 PM PDT 24
Peak memory	202960 kb
Host	smart-4fcfed34-e492-459c-875b-b0f224ff02ec
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003481526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_stress_pipeline.1003481526
Directory	/workspace/35.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.3279458175
Short name	T744
Test name
Test status
Simulation time	42775623 ps
CPU time	1.24 seconds
Started	Jun 29 06:56:10 PM PDT 24
Finished	Jun 29 06:56:12 PM PDT 24
Peak memory	210812 kb
Host	smart-a30abd50-f624-4924-8b30-f1a382f1488c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279458175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.3279458175
Directory	/workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/36.sram_ctrl_access_during_key_req.4178939922
Short name	T430
Test name
Test status
Simulation time	2332312107 ps
CPU time	177.89 seconds
Started	Jun 29 06:56:17 PM PDT 24
Finished	Jun 29 06:59:16 PM PDT 24
Peak memory	366368 kb
Host	smart-1259d310-04c0-4f1b-bfe4-04a8f6226c0d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178939922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 36.sram_ctrl_access_during_key_req.4178939922
Directory	/workspace/36.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/36.sram_ctrl_alert_test.3012497836
Short name	T686
Test name
Test status
Simulation time	39856525 ps
CPU time	0.69 seconds
Started	Jun 29 06:56:25 PM PDT 24
Finished	Jun 29 06:56:26 PM PDT 24
Peak memory	202652 kb
Host	smart-6b657595-a750-4461-8c88-85790224cecb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012497836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.3012497836
Directory	/workspace/36.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.sram_ctrl_bijection.2689835831
Short name	T565
Test name
Test status
Simulation time	721065991 ps
CPU time	47.13 seconds
Started	Jun 29 06:56:10 PM PDT 24
Finished	Jun 29 06:56:58 PM PDT 24
Peak memory	202836 kb
Host	smart-6071fbd5-84c2-4375-9870-38ac5c2e6d87
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689835831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection .2689835831
Directory	/workspace/36.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/36.sram_ctrl_executable.1788726731
Short name	T177
Test name
Test status
Simulation time	19242864220 ps
CPU time	157.03 seconds
Started	Jun 29 06:56:17 PM PDT 24
Finished	Jun 29 06:58:54 PM PDT 24
Peak memory	305004 kb
Host	smart-fcba5e0d-cc74-44b6-906d-e8beab207482
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788726731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab le.1788726731
Directory	/workspace/36.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/36.sram_ctrl_lc_escalation.3402361655
Short name	T163
Test name
Test status
Simulation time	619472406 ps
CPU time	7.11 seconds
Started	Jun 29 06:56:09 PM PDT 24
Finished	Jun 29 06:56:17 PM PDT 24
Peak memory	202804 kb
Host	smart-ecf22ff4-7df3-4489-ab80-a6b7a73fdbbf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402361655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es calation.3402361655
Directory	/workspace/36.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/36.sram_ctrl_max_throughput.1718286090
Short name	T668
Test name
Test status
Simulation time	270561175 ps
CPU time	13.97 seconds
Started	Jun 29 06:56:10 PM PDT 24
Finished	Jun 29 06:56:25 PM PDT 24
Peak memory	259724 kb
Host	smart-b7e5547e-16d4-4d39-87ce-a7ff93331115
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718286090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 36.sram_ctrl_max_throughput.1718286090
Directory	/workspace/36.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/36.sram_ctrl_mem_partial_access.1168472139
Short name	T5
Test name
Test status
Simulation time	108781102 ps
CPU time	3.22 seconds
Started	Jun 29 06:56:18 PM PDT 24
Finished	Jun 29 06:56:22 PM PDT 24
Peak memory	211024 kb
Host	smart-e652d464-54db-4ed5-80fb-c0bd5cb2d102
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168472139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_mem_partial_access.1168472139
Directory	/workspace/36.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/36.sram_ctrl_mem_walk.3024021925
Short name	T936
Test name
Test status
Simulation time	132214034 ps
CPU time	4.52 seconds
Started	Jun 29 06:56:18 PM PDT 24
Finished	Jun 29 06:56:24 PM PDT 24
Peak memory	211084 kb
Host	smart-67cde4c8-6387-4d94-bc96-f7e7ef89923c
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024021925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr l_mem_walk.3024021925
Directory	/workspace/36.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/36.sram_ctrl_multiple_keys.423321352
Short name	T735
Test name
Test status
Simulation time	6252588764 ps
CPU time	352.21 seconds
Started	Jun 29 06:56:09 PM PDT 24
Finished	Jun 29 07:02:02 PM PDT 24
Peak memory	351192 kb
Host	smart-94ab59ba-ca0f-4314-a497-9eb98da6f944
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423321352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multip le_keys.423321352
Directory	/workspace/36.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/36.sram_ctrl_partial_access.556176895
Short name	T490
Test name
Test status
Simulation time	1920113354 ps
CPU time	19.1 seconds
Started	Jun 29 06:56:10 PM PDT 24
Finished	Jun 29 06:56:29 PM PDT 24
Peak memory	202728 kb
Host	smart-5daf60ff-c733-463e-9957-66b723661900
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556176895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.s ram_ctrl_partial_access.556176895
Directory	/workspace/36.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1511510822
Short name	T347
Test name
Test status
Simulation time	13248109639 ps
CPU time	241.84 seconds
Started	Jun 29 06:56:09 PM PDT 24
Finished	Jun 29 07:00:11 PM PDT 24
Peak memory	202900 kb
Host	smart-985e66ed-b5af-438c-8d18-fec2b21b12ee
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511510822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.sram_ctrl_partial_access_b2b.1511510822
Directory	/workspace/36.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/36.sram_ctrl_ram_cfg.2321394697
Short name	T342
Test name
Test status
Simulation time	121572594 ps
CPU time	0.76 seconds
Started	Jun 29 06:56:18 PM PDT 24
Finished	Jun 29 06:56:20 PM PDT 24
Peak memory	202860 kb
Host	smart-9343b078-c939-4345-bd48-62ed6c2eac4b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321394697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.2321394697
Directory	/workspace/36.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/36.sram_ctrl_regwen.3374224606
Short name	T286
Test name
Test status
Simulation time	8343304970 ps
CPU time	614.41 seconds
Started	Jun 29 06:56:18 PM PDT 24
Finished	Jun 29 07:06:33 PM PDT 24
Peak memory	367448 kb
Host	smart-caad2cb3-b2b2-4cf6-8b91-8805f2118e93
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374224606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.3374224606
Directory	/workspace/36.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/36.sram_ctrl_smoke.1508009510
Short name	T825
Test name
Test status
Simulation time	2049552835 ps
CPU time	8.05 seconds
Started	Jun 29 06:56:11 PM PDT 24
Finished	Jun 29 06:56:19 PM PDT 24
Peak memory	202824 kb
Host	smart-3cb4c2d3-a07a-4cf7-a341-da25aa4b3754
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508009510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.1508009510
Directory	/workspace/36.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.sram_ctrl_stress_all.865505889
Short name	T847
Test name
Test status
Simulation time	627848625750 ps
CPU time	2433.55 seconds
Started	Jun 29 06:56:19 PM PDT 24
Finished	Jun 29 07:36:53 PM PDT 24
Peak memory	375360 kb
Host	smart-cf6a1177-c940-40e9-87e8-0853fc5e4aa2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865505889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.sram_ctrl_stress_all.865505889
Directory	/workspace/36.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2265268013
Short name	T596
Test name
Test status
Simulation time	1952270021 ps
CPU time	47.55 seconds
Started	Jun 29 06:56:17 PM PDT 24
Finished	Jun 29 06:57:06 PM PDT 24
Peak memory	264220 kb
Host	smart-4dcec864-a5db-467a-9015-abd9af32f80b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2265268013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.2265268013
Directory	/workspace/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.sram_ctrl_stress_pipeline.808753342
Short name	T395
Test name
Test status
Simulation time	13866424395 ps
CPU time	343.84 seconds
Started	Jun 29 06:56:09 PM PDT 24
Finished	Jun 29 07:01:54 PM PDT 24
Peak memory	202984 kb
Host	smart-cb54f95f-6dbf-4ab3-ae85-b3d717651caa
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808753342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36 .sram_ctrl_stress_pipeline.808753342
Directory	/workspace/36.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.952429682
Short name	T934
Test name
Test status
Simulation time	650381257 ps
CPU time	137.82 seconds
Started	Jun 29 06:56:11 PM PDT 24
Finished	Jun 29 06:58:29 PM PDT 24
Peak memory	370168 kb
Host	smart-0b39a80b-eef4-4584-986a-2271bc8c7ba1
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952429682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 36.sram_ctrl_throughput_w_partial_write.952429682
Directory	/workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/37.sram_ctrl_access_during_key_req.3182194997
Short name	T625
Test name
Test status
Simulation time	4078776143 ps
CPU time	1059.49 seconds
Started	Jun 29 06:56:19 PM PDT 24
Finished	Jun 29 07:13:59 PM PDT 24
Peak memory	363464 kb
Host	smart-29f3ddd2-7776-4707-a115-fcc0142add28
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182194997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 37.sram_ctrl_access_during_key_req.3182194997
Directory	/workspace/37.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/37.sram_ctrl_alert_test.80190947
Short name	T397
Test name
Test status
Simulation time	37784795 ps
CPU time	0.67 seconds
Started	Jun 29 06:56:24 PM PDT 24
Finished	Jun 29 06:56:26 PM PDT 24
Peak memory	202616 kb
Host	smart-12b16f9d-a652-4bde-8e44-2c7b83f67b7b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80190947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_alert_test.80190947
Directory	/workspace/37.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.sram_ctrl_bijection.2795700689
Short name	T791
Test name
Test status
Simulation time	3648892418 ps
CPU time	29.54 seconds
Started	Jun 29 06:56:19 PM PDT 24
Finished	Jun 29 06:56:49 PM PDT 24
Peak memory	202940 kb
Host	smart-b66a7c23-3291-44d3-8050-7e8a66e8f75c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795700689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection .2795700689
Directory	/workspace/37.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/37.sram_ctrl_executable.3797810738
Short name	T698
Test name
Test status
Simulation time	17825970284 ps
CPU time	383.8 seconds
Started	Jun 29 06:56:19 PM PDT 24
Finished	Jun 29 07:02:43 PM PDT 24
Peak memory	369904 kb
Host	smart-268c58b4-016e-4b6d-8aff-cd58b9d5a0ad
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797810738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab le.3797810738
Directory	/workspace/37.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/37.sram_ctrl_lc_escalation.2983538668
Short name	T907
Test name
Test status
Simulation time	2091690589 ps
CPU time	6.92 seconds
Started	Jun 29 06:56:18 PM PDT 24
Finished	Jun 29 06:56:26 PM PDT 24
Peak memory	202796 kb
Host	smart-0edb5153-51ba-41df-9503-44c6ecd982e5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983538668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es calation.2983538668
Directory	/workspace/37.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/37.sram_ctrl_max_throughput.3931825385
Short name	T889
Test name
Test status
Simulation time	435554363 ps
CPU time	6.93 seconds
Started	Jun 29 06:56:18 PM PDT 24
Finished	Jun 29 06:56:25 PM PDT 24
Peak memory	235492 kb
Host	smart-3778646d-7eb7-4627-9a74-7d25ddb4b1f5
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931825385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 37.sram_ctrl_max_throughput.3931825385
Directory	/workspace/37.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/37.sram_ctrl_mem_partial_access.3120407682
Short name	T327
Test name
Test status
Simulation time	112647446 ps
CPU time	5.08 seconds
Started	Jun 29 06:56:18 PM PDT 24
Finished	Jun 29 06:56:24 PM PDT 24
Peak memory	211032 kb
Host	smart-f8077551-a38a-444a-ba3c-10504c36bdba
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120407682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_mem_partial_access.3120407682
Directory	/workspace/37.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/37.sram_ctrl_mem_walk.2486253833
Short name	T38
Test name
Test status
Simulation time	347043812 ps
CPU time	5.98 seconds
Started	Jun 29 06:56:17 PM PDT 24
Finished	Jun 29 06:56:24 PM PDT 24
Peak memory	211056 kb
Host	smart-f1ad2262-f90f-4d58-b6fe-6d7ba4232e1d
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486253833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr l_mem_walk.2486253833
Directory	/workspace/37.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/37.sram_ctrl_multiple_keys.4285716432
Short name	T866
Test name
Test status
Simulation time	3763285558 ps
CPU time	1004.14 seconds
Started	Jun 29 06:56:17 PM PDT 24
Finished	Jun 29 07:13:02 PM PDT 24
Peak memory	373684 kb
Host	smart-08b25899-f3ab-4220-921c-14cb062cd87e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285716432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi ple_keys.4285716432
Directory	/workspace/37.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/37.sram_ctrl_partial_access.1510130228
Short name	T897
Test name
Test status
Simulation time	1392495482 ps
CPU time	12.41 seconds
Started	Jun 29 06:56:18 PM PDT 24
Finished	Jun 29 06:56:31 PM PDT 24
Peak memory	202816 kb
Host	smart-8a7e8e35-dd29-47cd-a998-6a8a8e735f07
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510130228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37. sram_ctrl_partial_access.1510130228
Directory	/workspace/37.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3207868405
Short name	T806
Test name
Test status
Simulation time	61291181385 ps
CPU time	419.36 seconds
Started	Jun 29 06:56:19 PM PDT 24
Finished	Jun 29 07:03:19 PM PDT 24
Peak memory	202888 kb
Host	smart-517bf509-095e-40b0-b7ba-193ab57d5ef9
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207868405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 37.sram_ctrl_partial_access_b2b.3207868405
Directory	/workspace/37.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/37.sram_ctrl_ram_cfg.941960565
Short name	T496
Test name
Test status
Simulation time	41915216 ps
CPU time	0.76 seconds
Started	Jun 29 06:56:17 PM PDT 24
Finished	Jun 29 06:56:19 PM PDT 24
Peak memory	202888 kb
Host	smart-07bc187c-837e-43a5-8345-49ce6c28797d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941960565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.941960565
Directory	/workspace/37.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/37.sram_ctrl_regwen.2182790641
Short name	T838
Test name
Test status
Simulation time	12232121662 ps
CPU time	896.1 seconds
Started	Jun 29 06:56:19 PM PDT 24
Finished	Jun 29 07:11:15 PM PDT 24
Peak memory	362456 kb
Host	smart-1d6a9249-eea5-4543-a2ad-1a514814508f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182790641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.2182790641
Directory	/workspace/37.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/37.sram_ctrl_smoke.1195627148
Short name	T800
Test name
Test status
Simulation time	155743215 ps
CPU time	14.44 seconds
Started	Jun 29 06:56:17 PM PDT 24
Finished	Jun 29 06:56:32 PM PDT 24
Peak memory	254240 kb
Host	smart-2458562e-1792-493a-a410-2da42ec3840d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195627148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.1195627148
Directory	/workspace/37.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.sram_ctrl_stress_all.517717391
Short name	T371
Test name
Test status
Simulation time	109920236711 ps
CPU time	1589.05 seconds
Started	Jun 29 06:56:25 PM PDT 24
Finished	Jun 29 07:22:55 PM PDT 24
Peak memory	369672 kb
Host	smart-f51ffaba-4b73-4604-86a5-ebbe7fadd38d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517717391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 37.sram_ctrl_stress_all.517717391
Directory	/workspace/37.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1462305453
Short name	T310
Test name
Test status
Simulation time	5181689156 ps
CPU time	140.26 seconds
Started	Jun 29 06:56:18 PM PDT 24
Finished	Jun 29 06:58:39 PM PDT 24
Peak memory	319488 kb
Host	smart-c4818c0c-b48d-421d-83ec-ce54bb41bf56
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1462305453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.1462305453
Directory	/workspace/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.sram_ctrl_stress_pipeline.2573614237
Short name	T554
Test name
Test status
Simulation time	2460114761 ps
CPU time	255.63 seconds
Started	Jun 29 06:56:18 PM PDT 24
Finished	Jun 29 07:00:34 PM PDT 24
Peak memory	202988 kb
Host	smart-99008da8-5667-4860-8a69-97b3d37e3a45
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573614237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_stress_pipeline.2573614237
Directory	/workspace/37.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.267489747
Short name	T704
Test name
Test status
Simulation time	216684636 ps
CPU time	58.67 seconds
Started	Jun 29 06:56:18 PM PDT 24
Finished	Jun 29 06:57:18 PM PDT 24
Peak memory	308044 kb
Host	smart-e980f7ec-8ef3-4c6b-b521-5d49a510fe9c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267489747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 37.sram_ctrl_throughput_w_partial_write.267489747
Directory	/workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/38.sram_ctrl_access_during_key_req.640870100
Short name	T254
Test name
Test status
Simulation time	17297308019 ps
CPU time	1584.78 seconds
Started	Jun 29 06:56:25 PM PDT 24
Finished	Jun 29 07:22:51 PM PDT 24
Peak memory	373708 kb
Host	smart-a363eb11-0f6b-4672-94b5-bebd4ba22cde
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640870100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 38.sram_ctrl_access_during_key_req.640870100
Directory	/workspace/38.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/38.sram_ctrl_alert_test.49295774
Short name	T557
Test name
Test status
Simulation time	19883694 ps
CPU time	0.68 seconds
Started	Jun 29 06:56:25 PM PDT 24
Finished	Jun 29 06:56:27 PM PDT 24
Peak memory	202656 kb
Host	smart-5a592c92-0954-4aa0-a50d-7c774a7b9402
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49295774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_alert_test.49295774
Directory	/workspace/38.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.sram_ctrl_bijection.2552640324
Short name	T122
Test name
Test status
Simulation time	3241677238 ps
CPU time	55.25 seconds
Started	Jun 29 06:56:25 PM PDT 24
Finished	Jun 29 06:57:21 PM PDT 24
Peak memory	202956 kb
Host	smart-fd50e130-4f24-4347-9be9-b822ecddaaad
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552640324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection .2552640324
Directory	/workspace/38.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/38.sram_ctrl_executable.1495816427
Short name	T253
Test name
Test status
Simulation time	10531066251 ps
CPU time	846.27 seconds
Started	Jun 29 06:56:35 PM PDT 24
Finished	Jun 29 07:10:42 PM PDT 24
Peak memory	369700 kb
Host	smart-fd32eac2-cb0d-4638-b377-bb64b98344eb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495816427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab le.1495816427
Directory	/workspace/38.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/38.sram_ctrl_lc_escalation.3166809454
Short name	T340
Test name
Test status
Simulation time	111413880 ps
CPU time	1.42 seconds
Started	Jun 29 06:56:25 PM PDT 24
Finished	Jun 29 06:56:28 PM PDT 24
Peak memory	210816 kb
Host	smart-24b4e7f9-7300-490d-9f55-3cd646461756
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166809454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es calation.3166809454
Directory	/workspace/38.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/38.sram_ctrl_max_throughput.2414583328
Short name	T184
Test name
Test status
Simulation time	73087615 ps
CPU time	2.03 seconds
Started	Jun 29 06:56:25 PM PDT 24
Finished	Jun 29 06:56:28 PM PDT 24
Peak memory	211000 kb
Host	smart-6b41b55d-c58d-432d-b6a5-07b5993dbca3
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414583328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 38.sram_ctrl_max_throughput.2414583328
Directory	/workspace/38.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/38.sram_ctrl_mem_partial_access.2375146474
Short name	T326
Test name
Test status
Simulation time	209526991 ps
CPU time	5.8 seconds
Started	Jun 29 06:56:24 PM PDT 24
Finished	Jun 29 06:56:30 PM PDT 24
Peak memory	211084 kb
Host	smart-ec062d7a-4341-4cd0-acdc-d65178833993
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375146474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_mem_partial_access.2375146474
Directory	/workspace/38.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/38.sram_ctrl_mem_walk.624935947
Short name	T813
Test name
Test status
Simulation time	181910630 ps
CPU time	9.61 seconds
Started	Jun 29 06:56:26 PM PDT 24
Finished	Jun 29 06:56:36 PM PDT 24
Peak memory	211100 kb
Host	smart-98747ea2-067f-47c3-b944-8794017cc16c
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624935947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl _mem_walk.624935947
Directory	/workspace/38.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/38.sram_ctrl_multiple_keys.2554328940
Short name	T695
Test name
Test status
Simulation time	10491251703 ps
CPU time	1141.27 seconds
Started	Jun 29 06:56:17 PM PDT 24
Finished	Jun 29 07:15:19 PM PDT 24
Peak memory	366540 kb
Host	smart-0f3c7ef1-8ddc-4ab5-a671-071c866a546e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554328940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi ple_keys.2554328940
Directory	/workspace/38.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/38.sram_ctrl_partial_access.2305094583
Short name	T462
Test name
Test status
Simulation time	802217606 ps
CPU time	139.22 seconds
Started	Jun 29 06:56:27 PM PDT 24
Finished	Jun 29 06:58:47 PM PDT 24
Peak memory	367036 kb
Host	smart-dfc49422-ec2f-4c71-885d-19263e18db25
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305094583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38. sram_ctrl_partial_access.2305094583
Directory	/workspace/38.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.283835254
Short name	T652
Test name
Test status
Simulation time	30208188047 ps
CPU time	489.52 seconds
Started	Jun 29 06:56:33 PM PDT 24
Finished	Jun 29 07:04:43 PM PDT 24
Peak memory	202936 kb
Host	smart-586e1acc-0cc1-44b7-b040-705f9e87cf38
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283835254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 38.sram_ctrl_partial_access_b2b.283835254
Directory	/workspace/38.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/38.sram_ctrl_ram_cfg.2290715352
Short name	T789
Test name
Test status
Simulation time	53166586 ps
CPU time	0.75 seconds
Started	Jun 29 06:56:26 PM PDT 24
Finished	Jun 29 06:56:28 PM PDT 24
Peak memory	202860 kb
Host	smart-7832179d-5c44-4398-9443-1dd68c3f8155
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290715352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.2290715352
Directory	/workspace/38.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/38.sram_ctrl_regwen.4009943963
Short name	T139
Test name
Test status
Simulation time	13268772942 ps
CPU time	1478.95 seconds
Started	Jun 29 06:56:25 PM PDT 24
Finished	Jun 29 07:21:05 PM PDT 24
Peak memory	375084 kb
Host	smart-03f89551-7a7c-4681-8775-d8e00a4d8a48
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009943963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.4009943963
Directory	/workspace/38.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/38.sram_ctrl_smoke.3537031407
Short name	T270
Test name
Test status
Simulation time	961094892 ps
CPU time	4.98 seconds
Started	Jun 29 06:56:20 PM PDT 24
Finished	Jun 29 06:56:25 PM PDT 24
Peak memory	219724 kb
Host	smart-c66cb368-5a66-4268-af4e-1f8c57530c4b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537031407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.3537031407
Directory	/workspace/38.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.sram_ctrl_stress_all.1473374893
Short name	T471
Test name
Test status
Simulation time	80336707098 ps
CPU time	1875.24 seconds
Started	Jun 29 06:56:25 PM PDT 24
Finished	Jun 29 07:27:42 PM PDT 24
Peak memory	376788 kb
Host	smart-f991842c-2a38-472d-a787-0492d946e6fe
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473374893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 38.sram_ctrl_stress_all.1473374893
Directory	/workspace/38.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/38.sram_ctrl_stress_pipeline.1403091361
Short name	T570
Test name
Test status
Simulation time	45185540735 ps
CPU time	390.2 seconds
Started	Jun 29 06:56:20 PM PDT 24
Finished	Jun 29 07:02:51 PM PDT 24
Peak memory	202936 kb
Host	smart-6c80f603-6a6e-4aba-8920-87bed8e16a9d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403091361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_stress_pipeline.1403091361
Directory	/workspace/38.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.1304342319
Short name	T218
Test name
Test status
Simulation time	138748878 ps
CPU time	78.65 seconds
Started	Jun 29 06:56:27 PM PDT 24
Finished	Jun 29 06:57:46 PM PDT 24
Peak memory	340836 kb
Host	smart-0b812f9e-d46f-40c2-8dd6-a1ea43f27eac
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304342319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.1304342319
Directory	/workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/39.sram_ctrl_access_during_key_req.649875644
Short name	T891
Test name
Test status
Simulation time	8532271637 ps
CPU time	2835.17 seconds
Started	Jun 29 06:56:34 PM PDT 24
Finished	Jun 29 07:43:50 PM PDT 24
Peak memory	375500 kb
Host	smart-804f8038-767c-4159-a95a-dd2b759b8c81
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649875644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 39.sram_ctrl_access_during_key_req.649875644
Directory	/workspace/39.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/39.sram_ctrl_alert_test.2890556531
Short name	T590
Test name
Test status
Simulation time	25857126 ps
CPU time	0.75 seconds
Started	Jun 29 06:56:36 PM PDT 24
Finished	Jun 29 06:56:37 PM PDT 24
Peak memory	202304 kb
Host	smart-babeaba5-6018-4475-95d5-7f3905f5a121
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890556531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.2890556531
Directory	/workspace/39.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.sram_ctrl_bijection.1888726521
Short name	T612
Test name
Test status
Simulation time	23431615192 ps
CPU time	48.83 seconds
Started	Jun 29 06:56:27 PM PDT 24
Finished	Jun 29 06:57:16 PM PDT 24
Peak memory	202928 kb
Host	smart-ade7945f-695e-43dd-bb5e-285ef76acade
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888726521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection .1888726521
Directory	/workspace/39.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/39.sram_ctrl_executable.2988519873
Short name	T455
Test name
Test status
Simulation time	13876556723 ps
CPU time	1132.22 seconds
Started	Jun 29 06:56:36 PM PDT 24
Finished	Jun 29 07:15:29 PM PDT 24
Peak memory	370608 kb
Host	smart-5fd09c8c-92f6-4834-89c0-8ca8f9f23108
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988519873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab le.2988519873
Directory	/workspace/39.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/39.sram_ctrl_lc_escalation.4199838584
Short name	T705
Test name
Test status
Simulation time	1730012639 ps
CPU time	10.05 seconds
Started	Jun 29 06:56:35 PM PDT 24
Finished	Jun 29 06:56:46 PM PDT 24
Peak memory	202812 kb
Host	smart-524ddd45-0616-43ee-a5a8-d0d345b6f7de
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199838584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es calation.4199838584
Directory	/workspace/39.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/39.sram_ctrl_max_throughput.2112810832
Short name	T356
Test name
Test status
Simulation time	219887469 ps
CPU time	60.75 seconds
Started	Jun 29 06:56:28 PM PDT 24
Finished	Jun 29 06:57:29 PM PDT 24
Peak memory	325424 kb
Host	smart-68ccd766-4223-4fd6-80d0-4117aa1e7481
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112810832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.sram_ctrl_max_throughput.2112810832
Directory	/workspace/39.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/39.sram_ctrl_mem_partial_access.847996459
Short name	T707
Test name
Test status
Simulation time	803402867 ps
CPU time	6.36 seconds
Started	Jun 29 06:56:36 PM PDT 24
Finished	Jun 29 06:56:43 PM PDT 24
Peak memory	211080 kb
Host	smart-0a83b770-dc77-46b8-93e8-cf801c86dfce
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847996459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39 .sram_ctrl_mem_partial_access.847996459
Directory	/workspace/39.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/39.sram_ctrl_mem_walk.3370133561
Short name	T653
Test name
Test status
Simulation time	352147421 ps
CPU time	10.2 seconds
Started	Jun 29 06:56:32 PM PDT 24
Finished	Jun 29 06:56:43 PM PDT 24
Peak memory	211052 kb
Host	smart-4cabf955-6782-4e21-9b49-4c75848a41ec
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370133561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr l_mem_walk.3370133561
Directory	/workspace/39.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/39.sram_ctrl_multiple_keys.918916526
Short name	T632
Test name
Test status
Simulation time	54254280807 ps
CPU time	971.74 seconds
Started	Jun 29 06:56:28 PM PDT 24
Finished	Jun 29 07:12:40 PM PDT 24
Peak memory	373612 kb
Host	smart-0d262959-ebcd-4029-a9b2-23cee4c699cf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918916526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multip le_keys.918916526
Directory	/workspace/39.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/39.sram_ctrl_partial_access.2808878917
Short name	T624
Test name
Test status
Simulation time	7040709501 ps
CPU time	26.87 seconds
Started	Jun 29 06:56:26 PM PDT 24
Finished	Jun 29 06:56:54 PM PDT 24
Peak memory	272164 kb
Host	smart-16fa8cbf-c9e0-44dc-a5e5-2f05116513f4
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808878917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39. sram_ctrl_partial_access.2808878917
Directory	/workspace/39.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.136078199
Short name	T732
Test name
Test status
Simulation time	27751709912 ps
CPU time	357.36 seconds
Started	Jun 29 06:56:25 PM PDT 24
Finished	Jun 29 07:02:23 PM PDT 24
Peak memory	202932 kb
Host	smart-fd7be864-0603-48ce-bbe6-6a002adfd5ab
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136078199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 39.sram_ctrl_partial_access_b2b.136078199
Directory	/workspace/39.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/39.sram_ctrl_ram_cfg.1725809772
Short name	T372
Test name
Test status
Simulation time	45790842 ps
CPU time	0.76 seconds
Started	Jun 29 06:56:35 PM PDT 24
Finished	Jun 29 06:56:36 PM PDT 24
Peak memory	202896 kb
Host	smart-b3cab94c-6cf1-485a-908f-63a7a0038ed7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725809772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.1725809772
Directory	/workspace/39.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/39.sram_ctrl_regwen.3566336879
Short name	T586
Test name
Test status
Simulation time	49235122105 ps
CPU time	1093.13 seconds
Started	Jun 29 06:56:35 PM PDT 24
Finished	Jun 29 07:14:49 PM PDT 24
Peak memory	374844 kb
Host	smart-2d663d72-0f69-4a0f-87c3-5ef1435e5814
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566336879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.3566336879
Directory	/workspace/39.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/39.sram_ctrl_smoke.3288119927
Short name	T147
Test name
Test status
Simulation time	3061592910 ps
CPU time	149.16 seconds
Started	Jun 29 06:56:25 PM PDT 24
Finished	Jun 29 06:58:56 PM PDT 24
Peak memory	364328 kb
Host	smart-cbd72c42-689c-4f1a-b295-9dd7360810e6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288119927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.3288119927
Directory	/workspace/39.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.sram_ctrl_stress_all.489735224
Short name	T199
Test name
Test status
Simulation time	25800418051 ps
CPU time	3125.68 seconds
Started	Jun 29 06:56:36 PM PDT 24
Finished	Jun 29 07:48:42 PM PDT 24
Peak memory	374868 kb
Host	smart-c92889a2-143f-4673-b329-a49b6dad7233
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489735224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 39.sram_ctrl_stress_all.489735224
Directory	/workspace/39.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3687710615
Short name	T107
Test name
Test status
Simulation time	2156996528 ps
CPU time	72.47 seconds
Started	Jun 29 06:56:34 PM PDT 24
Finished	Jun 29 06:57:47 PM PDT 24
Peak memory	250140 kb
Host	smart-23fc3def-f752-41af-a611-de5f0c225680
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3687710615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.3687710615
Directory	/workspace/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.sram_ctrl_stress_pipeline.1663630242
Short name	T396
Test name
Test status
Simulation time	9867372933 ps
CPU time	256.33 seconds
Started	Jun 29 06:56:25 PM PDT 24
Finished	Jun 29 07:00:42 PM PDT 24
Peak memory	202952 kb
Host	smart-e4e15fb0-11bf-47f6-963d-70242785f183
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663630242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_stress_pipeline.1663630242
Directory	/workspace/39.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.4054004591
Short name	T683
Test name
Test status
Simulation time	44690261 ps
CPU time	1.46 seconds
Started	Jun 29 06:56:26 PM PDT 24
Finished	Jun 29 06:56:28 PM PDT 24
Peak memory	211056 kb
Host	smart-f91cc120-2474-49cb-bd59-c93a8125a1f4
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054004591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.4054004591
Directory	/workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/4.sram_ctrl_access_during_key_req.904937134
Short name	T412
Test name
Test status
Simulation time	14104816504 ps
CPU time	658.58 seconds
Started	Jun 29 06:54:05 PM PDT 24
Finished	Jun 29 07:05:04 PM PDT 24
Peak memory	353596 kb
Host	smart-12247161-fb98-492a-913f-1c68bec0e8ee
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904937134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 4.sram_ctrl_access_during_key_req.904937134
Directory	/workspace/4.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/4.sram_ctrl_alert_test.42041938
Short name	T903
Test name
Test status
Simulation time	41601020 ps
CPU time	0.68 seconds
Started	Jun 29 06:54:03 PM PDT 24
Finished	Jun 29 06:54:04 PM PDT 24
Peak memory	202612 kb
Host	smart-10f05e7b-a5fa-412d-a2c5-749a45de0017
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42041938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_alert_test.42041938
Directory	/workspace/4.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.sram_ctrl_bijection.3159084264
Short name	T892
Test name
Test status
Simulation time	4589113864 ps
CPU time	75.68 seconds
Started	Jun 29 06:54:10 PM PDT 24
Finished	Jun 29 06:55:26 PM PDT 24
Peak memory	202920 kb
Host	smart-8b49df06-db5e-4fa5-a021-88ef5b9ce9c4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159084264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection. 3159084264
Directory	/workspace/4.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/4.sram_ctrl_executable.2895270089
Short name	T402
Test name
Test status
Simulation time	1360169810 ps
CPU time	36.1 seconds
Started	Jun 29 06:54:04 PM PDT 24
Finished	Jun 29 06:54:41 PM PDT 24
Peak memory	250556 kb
Host	smart-0d97a0d8-122b-4d1d-92b4-7092408d81f5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895270089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl e.2895270089
Directory	/workspace/4.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/4.sram_ctrl_lc_escalation.879261655
Short name	T587
Test name
Test status
Simulation time	1409291624 ps
CPU time	4.38 seconds
Started	Jun 29 06:54:04 PM PDT 24
Finished	Jun 29 06:54:09 PM PDT 24
Peak memory	211024 kb
Host	smart-fefcd4cc-dc9a-45a9-a22c-c08cdc3cc9f1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879261655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esca lation.879261655
Directory	/workspace/4.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/4.sram_ctrl_max_throughput.2907864137
Short name	T183
Test name
Test status
Simulation time	514576349 ps
CPU time	112.51 seconds
Started	Jun 29 06:53:54 PM PDT 24
Finished	Jun 29 06:55:48 PM PDT 24
Peak memory	362324 kb
Host	smart-4020a7fd-b5ce-450f-aec1-20b8e7e784d4
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907864137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 4.sram_ctrl_max_throughput.2907864137
Directory	/workspace/4.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/4.sram_ctrl_mem_partial_access.3678493090
Short name	T890
Test name
Test status
Simulation time	163022249 ps
CPU time	5.68 seconds
Started	Jun 29 06:54:04 PM PDT 24
Finished	Jun 29 06:54:10 PM PDT 24
Peak memory	211048 kb
Host	smart-0e5f57b0-ebc1-4d5e-b8f0-70aab4ced4dd
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678493090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_mem_partial_access.3678493090
Directory	/workspace/4.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/4.sram_ctrl_mem_walk.2522968146
Short name	T809
Test name
Test status
Simulation time	283878589 ps
CPU time	4.91 seconds
Started	Jun 29 06:54:04 PM PDT 24
Finished	Jun 29 06:54:09 PM PDT 24
Peak memory	211072 kb
Host	smart-0ece2d65-8d73-4a7a-93cb-e8ff20b18559
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522968146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl _mem_walk.2522968146
Directory	/workspace/4.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/4.sram_ctrl_multiple_keys.319505283
Short name	T174
Test name
Test status
Simulation time	8075067227 ps
CPU time	448.38 seconds
Started	Jun 29 06:53:56 PM PDT 24
Finished	Jun 29 07:01:25 PM PDT 24
Peak memory	370352 kb
Host	smart-37d9a08b-6c2d-4bb1-89fb-4097c4f666af
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319505283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multipl e_keys.319505283
Directory	/workspace/4.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/4.sram_ctrl_partial_access.1517300486
Short name	T504
Test name
Test status
Simulation time	8771990364 ps
CPU time	106.43 seconds
Started	Jun 29 06:53:57 PM PDT 24
Finished	Jun 29 06:55:44 PM PDT 24
Peak memory	360484 kb
Host	smart-cf9bfcae-4819-49d7-ae97-c8d9bcbe6fab
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517300486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s ram_ctrl_partial_access.1517300486
Directory	/workspace/4.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2369857686
Short name	T619
Test name
Test status
Simulation time	56108579558 ps
CPU time	305.05 seconds
Started	Jun 29 06:53:57 PM PDT 24
Finished	Jun 29 06:59:03 PM PDT 24
Peak memory	202940 kb
Host	smart-28a878a1-99f1-4b31-bee7-bd03a5426a93
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369857686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.sram_ctrl_partial_access_b2b.2369857686
Directory	/workspace/4.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/4.sram_ctrl_ram_cfg.266533049
Short name	T245
Test name
Test status
Simulation time	32912008 ps
CPU time	0.83 seconds
Started	Jun 29 06:54:07 PM PDT 24
Finished	Jun 29 06:54:08 PM PDT 24
Peak memory	202876 kb
Host	smart-05ede7fc-3fba-400b-b0e2-57d1e6222c99
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266533049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.266533049
Directory	/workspace/4.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/4.sram_ctrl_regwen.388076257
Short name	T923
Test name
Test status
Simulation time	4389457873 ps
CPU time	1662.04 seconds
Started	Jun 29 06:54:07 PM PDT 24
Finished	Jun 29 07:21:50 PM PDT 24
Peak memory	375020 kb
Host	smart-074b373b-a5c1-4961-a599-3910f228e36a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388076257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.388076257
Directory	/workspace/4.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/4.sram_ctrl_sec_cm.1861179601
Short name	T27
Test name
Test status
Simulation time	904743684 ps
CPU time	3.17 seconds
Started	Jun 29 06:54:03 PM PDT 24
Finished	Jun 29 06:54:06 PM PDT 24
Peak memory	224512 kb
Host	smart-ec853085-9419-4855-add5-a8ffe37ae0bc
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861179601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.1861179601
Directory	/workspace/4.sram_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/4.sram_ctrl_smoke.2523543728
Short name	T236
Test name
Test status
Simulation time	452603514 ps
CPU time	35.41 seconds
Started	Jun 29 06:53:57 PM PDT 24
Finished	Jun 29 06:54:33 PM PDT 24
Peak memory	292764 kb
Host	smart-f4f384cd-a3f3-4193-acd7-0dfca8a44f91
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523543728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.2523543728
Directory	/workspace/4.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.sram_ctrl_stress_all.1895396527
Short name	T909
Test name
Test status
Simulation time	13012331966 ps
CPU time	1159.88 seconds
Started	Jun 29 06:54:06 PM PDT 24
Finished	Jun 29 07:13:27 PM PDT 24
Peak memory	382236 kb
Host	smart-6f2f0ad0-a08c-4c91-8ecd-1c9934afa9cf
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895396527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 4.sram_ctrl_stress_all.1895396527
Directory	/workspace/4.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.sram_ctrl_stress_pipeline.261749080
Short name	T693
Test name
Test status
Simulation time	14962441102 ps
CPU time	103.24 seconds
Started	Jun 29 06:53:57 PM PDT 24
Finished	Jun 29 06:55:42 PM PDT 24
Peak memory	202908 kb
Host	smart-1fec9de9-846a-46b0-81b7-ebbf40f76c7b
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261749080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4. sram_ctrl_stress_pipeline.261749080
Directory	/workspace/4.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.2857626088
Short name	T433
Test name
Test status
Simulation time	248415720 ps
CPU time	91.8 seconds
Started	Jun 29 06:54:04 PM PDT 24
Finished	Jun 29 06:55:37 PM PDT 24
Peak memory	340768 kb
Host	smart-3baa411f-8035-4d9e-ac3b-a6fe188b4e96
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857626088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.2857626088
Directory	/workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/40.sram_ctrl_access_during_key_req.3812449533
Short name	T506
Test name
Test status
Simulation time	8105163314 ps
CPU time	1272.76 seconds
Started	Jun 29 06:56:35 PM PDT 24
Finished	Jun 29 07:17:49 PM PDT 24
Peak memory	374604 kb
Host	smart-19b3e3e4-4a3c-4901-96bc-b9d542e56363
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812449533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 40.sram_ctrl_access_during_key_req.3812449533
Directory	/workspace/40.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/40.sram_ctrl_alert_test.1159965471
Short name	T432
Test name
Test status
Simulation time	25056321 ps
CPU time	0.68 seconds
Started	Jun 29 06:56:35 PM PDT 24
Finished	Jun 29 06:56:37 PM PDT 24
Peak memory	202304 kb
Host	smart-6de9e6f1-aed6-4315-9b62-b7cfb4de4057
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159965471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.1159965471
Directory	/workspace/40.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.sram_ctrl_bijection.1231492550
Short name	T332
Test name
Test status
Simulation time	1125652192 ps
CPU time	60.14 seconds
Started	Jun 29 06:56:35 PM PDT 24
Finished	Jun 29 06:57:36 PM PDT 24
Peak memory	202844 kb
Host	smart-7c1bc9a1-6d86-4611-a8ec-2f4672f41dc8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231492550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection .1231492550
Directory	/workspace/40.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/40.sram_ctrl_executable.2056176650
Short name	T142
Test name
Test status
Simulation time	2312538093 ps
CPU time	824.06 seconds
Started	Jun 29 06:56:36 PM PDT 24
Finished	Jun 29 07:10:21 PM PDT 24
Peak memory	375788 kb
Host	smart-663c55a5-190b-49f2-b9b1-2c33e0432401
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056176650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab le.2056176650
Directory	/workspace/40.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/40.sram_ctrl_lc_escalation.2968833448
Short name	T690
Test name
Test status
Simulation time	1429914700 ps
CPU time	8.3 seconds
Started	Jun 29 06:56:35 PM PDT 24
Finished	Jun 29 06:56:45 PM PDT 24
Peak memory	214528 kb
Host	smart-c0c20d60-d19b-4685-9eff-c3fadd241063
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968833448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es calation.2968833448
Directory	/workspace/40.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/40.sram_ctrl_max_throughput.1421126893
Short name	T180
Test name
Test status
Simulation time	221462632 ps
CPU time	88.88 seconds
Started	Jun 29 06:56:33 PM PDT 24
Finished	Jun 29 06:58:02 PM PDT 24
Peak memory	328552 kb
Host	smart-a5b922c9-def7-443b-bfac-3bed11ac7b11
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421126893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 40.sram_ctrl_max_throughput.1421126893
Directory	/workspace/40.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/40.sram_ctrl_mem_partial_access.3890394777
Short name	T103
Test name
Test status
Simulation time	81345118 ps
CPU time	2.73 seconds
Started	Jun 29 06:56:34 PM PDT 24
Finished	Jun 29 06:56:37 PM PDT 24
Peak memory	211064 kb
Host	smart-8ac6d957-16c4-461e-8775-42110e6eb8b4
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890394777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_mem_partial_access.3890394777
Directory	/workspace/40.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/40.sram_ctrl_mem_walk.1107073184
Short name	T41
Test name
Test status
Simulation time	1839002855 ps
CPU time	10.87 seconds
Started	Jun 29 06:56:35 PM PDT 24
Finished	Jun 29 06:56:46 PM PDT 24
Peak memory	210992 kb
Host	smart-d6de1ca6-d5ab-4211-b6f8-a55049da82c4
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107073184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr l_mem_walk.1107073184
Directory	/workspace/40.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/40.sram_ctrl_multiple_keys.1571093796
Short name	T646
Test name
Test status
Simulation time	40400242791 ps
CPU time	535.02 seconds
Started	Jun 29 06:56:35 PM PDT 24
Finished	Jun 29 07:05:30 PM PDT 24
Peak memory	372676 kb
Host	smart-457157ea-18d1-421b-bab4-9fb3ea5da431
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571093796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi ple_keys.1571093796
Directory	/workspace/40.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/40.sram_ctrl_partial_access.2036957509
Short name	T545
Test name
Test status
Simulation time	445946242 ps
CPU time	41.09 seconds
Started	Jun 29 06:56:35 PM PDT 24
Finished	Jun 29 06:57:17 PM PDT 24
Peak memory	288768 kb
Host	smart-d753e9d3-95f8-43d5-b4e5-364e066d86a0
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036957509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40. sram_ctrl_partial_access.2036957509
Directory	/workspace/40.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.208258745
Short name	T502
Test name
Test status
Simulation time	73266640532 ps
CPU time	443.94 seconds
Started	Jun 29 06:56:36 PM PDT 24
Finished	Jun 29 07:04:00 PM PDT 24
Peak memory	202888 kb
Host	smart-15897e6b-7776-421d-8592-f2895edff92b
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208258745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 40.sram_ctrl_partial_access_b2b.208258745
Directory	/workspace/40.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/40.sram_ctrl_ram_cfg.4092289319
Short name	T515
Test name
Test status
Simulation time	198603024 ps
CPU time	0.77 seconds
Started	Jun 29 06:56:36 PM PDT 24
Finished	Jun 29 06:56:37 PM PDT 24
Peak memory	202868 kb
Host	smart-27581ba7-5e8a-4d9d-abbd-78936d8f5930
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092289319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.4092289319
Directory	/workspace/40.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/40.sram_ctrl_regwen.1511801198
Short name	T610
Test name
Test status
Simulation time	2321710568 ps
CPU time	826.91 seconds
Started	Jun 29 06:56:38 PM PDT 24
Finished	Jun 29 07:10:25 PM PDT 24
Peak memory	375020 kb
Host	smart-212538ff-d232-492d-b98d-88da9971fb5e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511801198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.1511801198
Directory	/workspace/40.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/40.sram_ctrl_smoke.1211126727
Short name	T664
Test name
Test status
Simulation time	435539200 ps
CPU time	49.55 seconds
Started	Jun 29 06:56:36 PM PDT 24
Finished	Jun 29 06:57:26 PM PDT 24
Peak memory	295372 kb
Host	smart-d9026312-ab01-4e9a-8c26-acd1b197d8e1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211126727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.1211126727
Directory	/workspace/40.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/40.sram_ctrl_stress_pipeline.3395804684
Short name	T765
Test name
Test status
Simulation time	4617395229 ps
CPU time	227.18 seconds
Started	Jun 29 06:56:34 PM PDT 24
Finished	Jun 29 07:00:21 PM PDT 24
Peak memory	202940 kb
Host	smart-76a0fb6d-73d4-4312-877c-8dcba0f4c5ae
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395804684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_stress_pipeline.3395804684
Directory	/workspace/40.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.4290155288
Short name	T674
Test name
Test status
Simulation time	118239251 ps
CPU time	52.61 seconds
Started	Jun 29 06:56:35 PM PDT 24
Finished	Jun 29 06:57:28 PM PDT 24
Peak memory	300940 kb
Host	smart-d6696eb7-5e25-494a-88de-ee06100b5704
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290155288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.4290155288
Directory	/workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/41.sram_ctrl_access_during_key_req.216061744
Short name	T179
Test name
Test status
Simulation time	2921393621 ps
CPU time	1426.66 seconds
Started	Jun 29 06:56:44 PM PDT 24
Finished	Jun 29 07:20:32 PM PDT 24
Peak memory	374584 kb
Host	smart-a0e78927-c6fc-45ae-a7ff-fb92e8994ae0
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216061744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 41.sram_ctrl_access_during_key_req.216061744
Directory	/workspace/41.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/41.sram_ctrl_alert_test.52565072
Short name	T217
Test name
Test status
Simulation time	14775444 ps
CPU time	0.68 seconds
Started	Jun 29 06:56:49 PM PDT 24
Finished	Jun 29 06:56:50 PM PDT 24
Peak memory	202824 kb
Host	smart-2788b283-3b1b-4ab4-9753-cd51efd68138
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52565072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_alert_test.52565072
Directory	/workspace/41.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.sram_ctrl_bijection.1343269074
Short name	T423
Test name
Test status
Simulation time	3019550338 ps
CPU time	57.9 seconds
Started	Jun 29 06:56:48 PM PDT 24
Finished	Jun 29 06:57:46 PM PDT 24
Peak memory	203152 kb
Host	smart-30969640-3c7e-44c8-9dd9-3fcaf12ede5f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343269074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection .1343269074
Directory	/workspace/41.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/41.sram_ctrl_executable.4278768585
Short name	T34
Test name
Test status
Simulation time	175645949381 ps
CPU time	1221.57 seconds
Started	Jun 29 06:56:44 PM PDT 24
Finished	Jun 29 07:17:07 PM PDT 24
Peak memory	363544 kb
Host	smart-cf80499d-5946-4a3d-b037-6d36844f64eb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278768585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab le.4278768585
Directory	/workspace/41.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/41.sram_ctrl_lc_escalation.938199549
Short name	T898
Test name
Test status
Simulation time	2217235844 ps
CPU time	6.19 seconds
Started	Jun 29 06:56:44 PM PDT 24
Finished	Jun 29 06:56:51 PM PDT 24
Peak memory	202968 kb
Host	smart-15fd4321-a0c0-4c39-befd-e8fa18ca00af
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938199549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_esc alation.938199549
Directory	/workspace/41.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/41.sram_ctrl_max_throughput.3649484859
Short name	T438
Test name
Test status
Simulation time	450425023 ps
CPU time	61.5 seconds
Started	Jun 29 06:56:44 PM PDT 24
Finished	Jun 29 06:57:46 PM PDT 24
Peak memory	308296 kb
Host	smart-914c1b9e-93a4-4031-aa44-61b471d75056
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649484859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 41.sram_ctrl_max_throughput.3649484859
Directory	/workspace/41.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/41.sram_ctrl_mem_partial_access.1407139326
Short name	T603
Test name
Test status
Simulation time	304707185 ps
CPU time	4.98 seconds
Started	Jun 29 06:56:44 PM PDT 24
Finished	Jun 29 06:56:50 PM PDT 24
Peak memory	211036 kb
Host	smart-1e6633ee-a7f4-4348-9587-790a0b6fac17
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407139326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_mem_partial_access.1407139326
Directory	/workspace/41.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/41.sram_ctrl_mem_walk.1425943313
Short name	T931
Test name
Test status
Simulation time	689573345 ps
CPU time	6.29 seconds
Started	Jun 29 06:56:45 PM PDT 24
Finished	Jun 29 06:56:52 PM PDT 24
Peak memory	211080 kb
Host	smart-b9a728d5-dcac-4105-9703-f57565d47af2
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425943313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr l_mem_walk.1425943313
Directory	/workspace/41.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/41.sram_ctrl_multiple_keys.1440546028
Short name	T660
Test name
Test status
Simulation time	7994645592 ps
CPU time	458.38 seconds
Started	Jun 29 06:56:47 PM PDT 24
Finished	Jun 29 07:04:25 PM PDT 24
Peak memory	374984 kb
Host	smart-3d84baf8-1e12-4f46-82bf-30db5cf86ce6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440546028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi ple_keys.1440546028
Directory	/workspace/41.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/41.sram_ctrl_partial_access.2198913198
Short name	T914
Test name
Test status
Simulation time	252804726 ps
CPU time	4.93 seconds
Started	Jun 29 06:56:48 PM PDT 24
Finished	Jun 29 06:56:54 PM PDT 24
Peak memory	203032 kb
Host	smart-3cc600bd-f5f6-47b2-80cc-fb1cbfe6c857
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198913198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41. sram_ctrl_partial_access.2198913198
Directory	/workspace/41.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.1165183653
Short name	T531
Test name
Test status
Simulation time	24444811741 ps
CPU time	436.71 seconds
Started	Jun 29 06:56:43 PM PDT 24
Finished	Jun 29 07:04:01 PM PDT 24
Peak memory	202964 kb
Host	smart-c3120e90-6e58-4393-9a9e-9f7fda1f56a5
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165183653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 41.sram_ctrl_partial_access_b2b.1165183653
Directory	/workspace/41.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/41.sram_ctrl_ram_cfg.2267245159
Short name	T649
Test name
Test status
Simulation time	76473254 ps
CPU time	0.76 seconds
Started	Jun 29 06:56:45 PM PDT 24
Finished	Jun 29 06:56:46 PM PDT 24
Peak memory	202876 kb
Host	smart-2e2d3940-f527-4115-847e-5d4569f69444
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267245159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.2267245159
Directory	/workspace/41.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/41.sram_ctrl_regwen.3653724433
Short name	T31
Test name
Test status
Simulation time	22778994865 ps
CPU time	2167.51 seconds
Started	Jun 29 06:56:43 PM PDT 24
Finished	Jun 29 07:32:52 PM PDT 24
Peak memory	375812 kb
Host	smart-edd3ba44-8921-4b0a-aca9-e92295fa62ae
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653724433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.3653724433
Directory	/workspace/41.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/41.sram_ctrl_smoke.1826132872
Short name	T503
Test name
Test status
Simulation time	806300418 ps
CPU time	17.25 seconds
Started	Jun 29 06:56:34 PM PDT 24
Finished	Jun 29 06:56:52 PM PDT 24
Peak memory	202792 kb
Host	smart-1eb5ea24-6174-4b00-81f4-09322bd248c2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826132872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.1826132872
Directory	/workspace/41.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.sram_ctrl_stress_all.4267004244
Short name	T211
Test name
Test status
Simulation time	22495495150 ps
CPU time	1950.45 seconds
Started	Jun 29 06:56:47 PM PDT 24
Finished	Jun 29 07:29:18 PM PDT 24
Peak memory	382900 kb
Host	smart-725ab478-2290-47b4-8d27-482f5bb4e9e8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267004244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 41.sram_ctrl_stress_all.4267004244
Directory	/workspace/41.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.995109300
Short name	T870
Test name
Test status
Simulation time	22131801006 ps
CPU time	451.81 seconds
Started	Jun 29 06:56:44 PM PDT 24
Finished	Jun 29 07:04:16 PM PDT 24
Peak memory	356252 kb
Host	smart-ec85d234-5897-4fb6-a9ff-1ff4cb554ffc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=995109300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.995109300
Directory	/workspace/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.sram_ctrl_stress_pipeline.2268844600
Short name	T235
Test name
Test status
Simulation time	3421982303 ps
CPU time	314.1 seconds
Started	Jun 29 06:56:43 PM PDT 24
Finished	Jun 29 07:01:58 PM PDT 24
Peak memory	202956 kb
Host	smart-8904ca0b-89b9-423d-bd7d-d6032e21f67f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268844600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_stress_pipeline.2268844600
Directory	/workspace/41.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3866101341
Short name	T354
Test name
Test status
Simulation time	54030943 ps
CPU time	3.96 seconds
Started	Jun 29 06:56:43 PM PDT 24
Finished	Jun 29 06:56:48 PM PDT 24
Peak memory	224284 kb
Host	smart-b083a68b-e115-4ea7-af14-2c99aa6d083e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866101341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.3866101341
Directory	/workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/42.sram_ctrl_access_during_key_req.1864947057
Short name	T269
Test name
Test status
Simulation time	35435283360 ps
CPU time	1213.5 seconds
Started	Jun 29 06:56:45 PM PDT 24
Finished	Jun 29 07:16:59 PM PDT 24
Peak memory	374996 kb
Host	smart-6b655394-04be-453d-a540-d118d92c87c7
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864947057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 42.sram_ctrl_access_during_key_req.1864947057
Directory	/workspace/42.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/42.sram_ctrl_alert_test.2594587392
Short name	T13
Test name
Test status
Simulation time	51580645 ps
CPU time	0.67 seconds
Started	Jun 29 06:56:53 PM PDT 24
Finished	Jun 29 06:56:54 PM PDT 24
Peak memory	202304 kb
Host	smart-41493a65-0ff2-4a78-aad0-3648e9d8019e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594587392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.2594587392
Directory	/workspace/42.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.sram_ctrl_bijection.2111554843
Short name	T537
Test name
Test status
Simulation time	1327034156 ps
CPU time	17.28 seconds
Started	Jun 29 06:56:44 PM PDT 24
Finished	Jun 29 06:57:02 PM PDT 24
Peak memory	202832 kb
Host	smart-b730ab73-ad5e-4057-bd4f-520b33e5a799
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111554843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection .2111554843
Directory	/workspace/42.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/42.sram_ctrl_executable.3456609582
Short name	T143
Test name
Test status
Simulation time	35864045847 ps
CPU time	1480.68 seconds
Started	Jun 29 06:56:44 PM PDT 24
Finished	Jun 29 07:21:25 PM PDT 24
Peak memory	375652 kb
Host	smart-d0f6b612-22a3-4648-8fd8-e8c088670146
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456609582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab le.3456609582
Directory	/workspace/42.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/42.sram_ctrl_lc_escalation.197716144
Short name	T740
Test name
Test status
Simulation time	434019378 ps
CPU time	4.94 seconds
Started	Jun 29 06:56:46 PM PDT 24
Finished	Jun 29 06:56:51 PM PDT 24
Peak memory	202784 kb
Host	smart-98d72d2a-d026-4f37-9adc-6ed80fdfe34d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197716144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_esc alation.197716144
Directory	/workspace/42.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/42.sram_ctrl_max_throughput.1679029168
Short name	T529
Test name
Test status
Simulation time	234813955 ps
CPU time	13.07 seconds
Started	Jun 29 06:56:47 PM PDT 24
Finished	Jun 29 06:57:00 PM PDT 24
Peak memory	255856 kb
Host	smart-a23a3f60-e019-4f3b-b41e-8e901d9fccfd
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679029168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 42.sram_ctrl_max_throughput.1679029168
Directory	/workspace/42.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/42.sram_ctrl_mem_partial_access.1341296070
Short name	T720
Test name
Test status
Simulation time	57012645 ps
CPU time	2.73 seconds
Started	Jun 29 06:56:52 PM PDT 24
Finished	Jun 29 06:56:55 PM PDT 24
Peak memory	211084 kb
Host	smart-ba17e632-0ec8-47a4-a57b-0492dd9a26d1
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341296070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_mem_partial_access.1341296070
Directory	/workspace/42.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/42.sram_ctrl_mem_walk.2420797075
Short name	T708
Test name
Test status
Simulation time	2213740529 ps
CPU time	6.13 seconds
Started	Jun 29 06:56:54 PM PDT 24
Finished	Jun 29 06:57:01 PM PDT 24
Peak memory	211224 kb
Host	smart-13c44dfb-772b-4d0a-8398-b26c5b18b365
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420797075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr l_mem_walk.2420797075
Directory	/workspace/42.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/42.sram_ctrl_multiple_keys.1565874197
Short name	T622
Test name
Test status
Simulation time	71687401430 ps
CPU time	1572.06 seconds
Started	Jun 29 06:56:44 PM PDT 24
Finished	Jun 29 07:22:56 PM PDT 24
Peak memory	375740 kb
Host	smart-dea3d407-aca2-4f85-844d-f5c44c6fe57c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565874197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi ple_keys.1565874197
Directory	/workspace/42.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/42.sram_ctrl_partial_access.342535241
Short name	T878
Test name
Test status
Simulation time	2381123737 ps
CPU time	90.25 seconds
Started	Jun 29 06:56:44 PM PDT 24
Finished	Jun 29 06:58:15 PM PDT 24
Peak memory	333680 kb
Host	smart-d4c61129-0398-4c37-a583-2d7b4c28c50e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342535241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.s ram_ctrl_partial_access.342535241
Directory	/workspace/42.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1908527618
Short name	T493
Test name
Test status
Simulation time	11581745172 ps
CPU time	313.78 seconds
Started	Jun 29 06:56:45 PM PDT 24
Finished	Jun 29 07:01:59 PM PDT 24
Peak memory	202960 kb
Host	smart-724c0c36-ad31-496a-a748-a9202a207dc4
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908527618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 42.sram_ctrl_partial_access_b2b.1908527618
Directory	/workspace/42.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/42.sram_ctrl_ram_cfg.3156259146
Short name	T696
Test name
Test status
Simulation time	61514363 ps
CPU time	0.77 seconds
Started	Jun 29 06:56:52 PM PDT 24
Finished	Jun 29 06:56:53 PM PDT 24
Peak memory	202884 kb
Host	smart-ee96fe70-b3c1-4820-bf63-c09990d8b92f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156259146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.3156259146
Directory	/workspace/42.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/42.sram_ctrl_regwen.1690057673
Short name	T831
Test name
Test status
Simulation time	17862022357 ps
CPU time	752.29 seconds
Started	Jun 29 06:56:45 PM PDT 24
Finished	Jun 29 07:09:17 PM PDT 24
Peak memory	374756 kb
Host	smart-a58cc5ba-af7b-4527-8b54-e0660bf84775
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690057673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.1690057673
Directory	/workspace/42.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/42.sram_ctrl_smoke.1607471260
Short name	T837
Test name
Test status
Simulation time	1102289510 ps
CPU time	10.66 seconds
Started	Jun 29 06:56:44 PM PDT 24
Finished	Jun 29 06:56:55 PM PDT 24
Peak memory	202840 kb
Host	smart-b4d11a4e-260c-4751-968d-6eb94743e18f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607471260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.1607471260
Directory	/workspace/42.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.sram_ctrl_stress_all.1104078942
Short name	T678
Test name
Test status
Simulation time	3998781745 ps
CPU time	79.01 seconds
Started	Jun 29 06:56:52 PM PDT 24
Finished	Jun 29 06:58:11 PM PDT 24
Peak memory	312112 kb
Host	smart-59611e9b-c22f-4d95-9612-4887067fd8f6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104078942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 42.sram_ctrl_stress_all.1104078942
Directory	/workspace/42.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1401139812
Short name	T703
Test name
Test status
Simulation time	1541646987 ps
CPU time	85.69 seconds
Started	Jun 29 06:56:53 PM PDT 24
Finished	Jun 29 06:58:19 PM PDT 24
Peak memory	229892 kb
Host	smart-35d94ae1-7c59-4dec-b027-7395f092ef8e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1401139812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.1401139812
Directory	/workspace/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.sram_ctrl_stress_pipeline.3309422127
Short name	T739
Test name
Test status
Simulation time	12237941410 ps
CPU time	287.84 seconds
Started	Jun 29 06:56:45 PM PDT 24
Finished	Jun 29 07:01:33 PM PDT 24
Peak memory	202952 kb
Host	smart-7b0f9a08-e26c-41f6-8806-283da8db54fa
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309422127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_stress_pipeline.3309422127
Directory	/workspace/42.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.4219157276
Short name	T1
Test name
Test status
Simulation time	264923311 ps
CPU time	5.34 seconds
Started	Jun 29 06:56:43 PM PDT 24
Finished	Jun 29 06:56:48 PM PDT 24
Peak memory	226732 kb
Host	smart-2c4d36fc-a340-4a93-8c6a-07a521a5dd4b
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219157276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.4219157276
Directory	/workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/43.sram_ctrl_access_during_key_req.2312170808
Short name	T287
Test name
Test status
Simulation time	1710816412 ps
CPU time	539.39 seconds
Started	Jun 29 06:56:53 PM PDT 24
Finished	Jun 29 07:05:53 PM PDT 24
Peak memory	369232 kb
Host	smart-9e35a6b8-96f6-4048-9e20-1d106a10b652
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312170808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 43.sram_ctrl_access_during_key_req.2312170808
Directory	/workspace/43.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/43.sram_ctrl_alert_test.255357154
Short name	T380
Test name
Test status
Simulation time	11187617 ps
CPU time	0.66 seconds
Started	Jun 29 06:56:59 PM PDT 24
Finished	Jun 29 06:57:00 PM PDT 24
Peak memory	202620 kb
Host	smart-1fa9d96c-fe1f-4800-8099-5a8e1a9c86ac
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255357154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.255357154
Directory	/workspace/43.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.sram_ctrl_bijection.3310687186
Short name	T533
Test name
Test status
Simulation time	9729369877 ps
CPU time	40.88 seconds
Started	Jun 29 06:56:54 PM PDT 24
Finished	Jun 29 06:57:35 PM PDT 24
Peak memory	202944 kb
Host	smart-9e6bbaa4-f7c7-4b62-bf2e-05b25c856b73
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310687186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection .3310687186
Directory	/workspace/43.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/43.sram_ctrl_executable.1903932851
Short name	T460
Test name
Test status
Simulation time	13663480801 ps
CPU time	990.74 seconds
Started	Jun 29 06:56:52 PM PDT 24
Finished	Jun 29 07:13:23 PM PDT 24
Peak memory	373776 kb
Host	smart-1ab893ac-61d9-443e-8b89-7ebffef2b374
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903932851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab le.1903932851
Directory	/workspace/43.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/43.sram_ctrl_lc_escalation.3150579877
Short name	T247
Test name
Test status
Simulation time	2128089580 ps
CPU time	8.04 seconds
Started	Jun 29 06:56:56 PM PDT 24
Finished	Jun 29 06:57:04 PM PDT 24
Peak memory	211008 kb
Host	smart-935f9f08-68f3-41ae-823c-8330bad21d14
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150579877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es calation.3150579877
Directory	/workspace/43.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/43.sram_ctrl_max_throughput.552629107
Short name	T11
Test name
Test status
Simulation time	154615939 ps
CPU time	3.08 seconds
Started	Jun 29 06:56:52 PM PDT 24
Finished	Jun 29 06:56:56 PM PDT 24
Peak memory	219136 kb
Host	smart-06ba13ec-5142-4bdd-99a6-3ea2836a8c69
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552629107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 43.sram_ctrl_max_throughput.552629107
Directory	/workspace/43.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/43.sram_ctrl_mem_partial_access.3196979914
Short name	T207
Test name
Test status
Simulation time	101237590 ps
CPU time	3.21 seconds
Started	Jun 29 06:56:52 PM PDT 24
Finished	Jun 29 06:56:55 PM PDT 24
Peak memory	211124 kb
Host	smart-ce02eabe-b53f-4e1b-8430-8c9d68ac3c29
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196979914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_mem_partial_access.3196979914
Directory	/workspace/43.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/43.sram_ctrl_mem_walk.3470701150
Short name	T880
Test name
Test status
Simulation time	548499296 ps
CPU time	8.93 seconds
Started	Jun 29 06:56:52 PM PDT 24
Finished	Jun 29 06:57:01 PM PDT 24
Peak memory	211100 kb
Host	smart-22d71642-1ed4-4865-8bcb-0bd5044586ee
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470701150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr l_mem_walk.3470701150
Directory	/workspace/43.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/43.sram_ctrl_multiple_keys.2605181408
Short name	T520
Test name
Test status
Simulation time	12761304332 ps
CPU time	1003.36 seconds
Started	Jun 29 06:56:52 PM PDT 24
Finished	Jun 29 07:13:35 PM PDT 24
Peak memory	373672 kb
Host	smart-059de093-de5f-4150-9a7b-177e44f14acc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605181408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi ple_keys.2605181408
Directory	/workspace/43.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/43.sram_ctrl_partial_access.3124938449
Short name	T810
Test name
Test status
Simulation time	333374498 ps
CPU time	14.57 seconds
Started	Jun 29 06:56:56 PM PDT 24
Finished	Jun 29 06:57:11 PM PDT 24
Peak memory	202836 kb
Host	smart-1adc67d0-8669-4b27-a611-b706db22c13e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124938449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43. sram_ctrl_partial_access.3124938449
Directory	/workspace/43.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3571611631
Short name	T577
Test name
Test status
Simulation time	5055565435 ps
CPU time	398.33 seconds
Started	Jun 29 06:56:51 PM PDT 24
Finished	Jun 29 07:03:29 PM PDT 24
Peak memory	202924 kb
Host	smart-b8490bdd-535a-435a-83f6-4af86a273f1d
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571611631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.sram_ctrl_partial_access_b2b.3571611631
Directory	/workspace/43.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/43.sram_ctrl_ram_cfg.3326923736
Short name	T248
Test name
Test status
Simulation time	131983743 ps
CPU time	0.77 seconds
Started	Jun 29 06:56:53 PM PDT 24
Finished	Jun 29 06:56:54 PM PDT 24
Peak memory	202868 kb
Host	smart-3a9695f0-572a-433f-a9b2-a58c9569b609
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326923736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.3326923736
Directory	/workspace/43.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/43.sram_ctrl_regwen.2696702207
Short name	T115
Test name
Test status
Simulation time	505121965 ps
CPU time	217.01 seconds
Started	Jun 29 06:56:53 PM PDT 24
Finished	Jun 29 07:00:30 PM PDT 24
Peak memory	347400 kb
Host	smart-f56f1a5d-c4fc-4064-8b11-fe28426f910a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696702207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.2696702207
Directory	/workspace/43.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/43.sram_ctrl_smoke.4008658525
Short name	T345
Test name
Test status
Simulation time	842857264 ps
CPU time	14.9 seconds
Started	Jun 29 06:56:52 PM PDT 24
Finished	Jun 29 06:57:07 PM PDT 24
Peak memory	202828 kb
Host	smart-a8231755-5b74-4739-9e66-21bb5f21ccd8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008658525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.4008658525
Directory	/workspace/43.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.sram_ctrl_stress_all.3805244232
Short name	T146
Test name
Test status
Simulation time	54787075643 ps
CPU time	4280.94 seconds
Started	Jun 29 06:56:53 PM PDT 24
Finished	Jun 29 08:08:15 PM PDT 24
Peak memory	376784 kb
Host	smart-549f0d23-64e9-4053-95f9-8c20c53c3f15
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805244232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 43.sram_ctrl_stress_all.3805244232
Directory	/workspace/43.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3041008638
Short name	T18
Test name
Test status
Simulation time	2283632614 ps
CPU time	725.3 seconds
Started	Jun 29 06:56:54 PM PDT 24
Finished	Jun 29 07:09:00 PM PDT 24
Peak memory	369544 kb
Host	smart-332d9b20-40d8-4aa3-9382-d0820fc331db
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3041008638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.3041008638
Directory	/workspace/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.sram_ctrl_stress_pipeline.1781397174
Short name	T448
Test name
Test status
Simulation time	12357995628 ps
CPU time	299.99 seconds
Started	Jun 29 06:56:54 PM PDT 24
Finished	Jun 29 07:01:54 PM PDT 24
Peak memory	202928 kb
Host	smart-b2281b39-a2e8-435b-8081-55d4d5855c4c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781397174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_stress_pipeline.1781397174
Directory	/workspace/43.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.686208551
Short name	T156
Test name
Test status
Simulation time	514824225 ps
CPU time	111.68 seconds
Started	Jun 29 06:56:53 PM PDT 24
Finished	Jun 29 06:58:45 PM PDT 24
Peak memory	353552 kb
Host	smart-a1171b59-efc9-4500-a214-c2419b65b68a
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686208551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 43.sram_ctrl_throughput_w_partial_write.686208551
Directory	/workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/44.sram_ctrl_access_during_key_req.3039015864
Short name	T767
Test name
Test status
Simulation time	11809072504 ps
CPU time	1572.19 seconds
Started	Jun 29 06:56:59 PM PDT 24
Finished	Jun 29 07:23:12 PM PDT 24
Peak memory	374196 kb
Host	smart-94eb993e-5ccd-42b3-8611-0a11600d76a4
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039015864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 44.sram_ctrl_access_during_key_req.3039015864
Directory	/workspace/44.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/44.sram_ctrl_alert_test.1281335407
Short name	T14
Test name
Test status
Simulation time	24475691 ps
CPU time	0.69 seconds
Started	Jun 29 06:57:01 PM PDT 24
Finished	Jun 29 06:57:02 PM PDT 24
Peak memory	202248 kb
Host	smart-66b5bce6-2db6-4cf6-9419-1fc84416b0d4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281335407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.1281335407
Directory	/workspace/44.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.sram_ctrl_bijection.924154814
Short name	T753
Test name
Test status
Simulation time	2122753072 ps
CPU time	66.68 seconds
Started	Jun 29 06:57:02 PM PDT 24
Finished	Jun 29 06:58:09 PM PDT 24
Peak memory	202712 kb
Host	smart-3c07fbb8-284f-4cca-a7f2-d2e868235144
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924154814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection. 924154814
Directory	/workspace/44.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/44.sram_ctrl_executable.4225727170
Short name	T819
Test name
Test status
Simulation time	9054040536 ps
CPU time	871.85 seconds
Started	Jun 29 06:57:01 PM PDT 24
Finished	Jun 29 07:11:33 PM PDT 24
Peak memory	374732 kb
Host	smart-9f801004-240b-474f-a65b-02dff0ec111f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225727170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executab le.4225727170
Directory	/workspace/44.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/44.sram_ctrl_lc_escalation.1393958068
Short name	T351
Test name
Test status
Simulation time	485429841 ps
CPU time	4.39 seconds
Started	Jun 29 06:57:00 PM PDT 24
Finished	Jun 29 06:57:05 PM PDT 24
Peak memory	202808 kb
Host	smart-06974344-fe24-49bc-bc07-4f96b1f8a06a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393958068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es calation.1393958068
Directory	/workspace/44.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/44.sram_ctrl_max_throughput.1952825904
Short name	T585
Test name
Test status
Simulation time	125367559 ps
CPU time	75.72 seconds
Started	Jun 29 06:57:00 PM PDT 24
Finished	Jun 29 06:58:16 PM PDT 24
Peak memory	347828 kb
Host	smart-06ad3aba-3d69-48d2-9967-4c0115cc65db
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952825904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 44.sram_ctrl_max_throughput.1952825904
Directory	/workspace/44.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/44.sram_ctrl_mem_partial_access.902113075
Short name	T623
Test name
Test status
Simulation time	49536663 ps
CPU time	2.6 seconds
Started	Jun 29 06:57:00 PM PDT 24
Finished	Jun 29 06:57:02 PM PDT 24
Peak memory	211092 kb
Host	smart-d23c7a74-2788-4848-bd43-eae1aee1933d
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902113075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44 .sram_ctrl_mem_partial_access.902113075
Directory	/workspace/44.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/44.sram_ctrl_mem_walk.1115217140
Short name	T658
Test name
Test status
Simulation time	270996167 ps
CPU time	8.98 seconds
Started	Jun 29 06:57:00 PM PDT 24
Finished	Jun 29 06:57:09 PM PDT 24
Peak memory	211064 kb
Host	smart-6aa92a7c-76fc-4d46-9d6e-8d5acdc86925
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115217140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr l_mem_walk.1115217140
Directory	/workspace/44.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/44.sram_ctrl_multiple_keys.2712519079
Short name	T148
Test name
Test status
Simulation time	37203202965 ps
CPU time	1754.52 seconds
Started	Jun 29 06:56:59 PM PDT 24
Finished	Jun 29 07:26:14 PM PDT 24
Peak memory	375772 kb
Host	smart-4f8e54e1-1d47-4aea-9bc4-43598617c0b3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712519079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi ple_keys.2712519079
Directory	/workspace/44.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/44.sram_ctrl_partial_access.4116677937
Short name	T614
Test name
Test status
Simulation time	179115807 ps
CPU time	1.99 seconds
Started	Jun 29 06:57:00 PM PDT 24
Finished	Jun 29 06:57:03 PM PDT 24
Peak memory	202816 kb
Host	smart-419df6e5-b1fc-4a64-b24f-b0e7816d3613
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116677937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44. sram_ctrl_partial_access.4116677937
Directory	/workspace/44.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3772845562
Short name	T628
Test name
Test status
Simulation time	6690906418 ps
CPU time	265.75 seconds
Started	Jun 29 06:57:03 PM PDT 24
Finished	Jun 29 07:01:29 PM PDT 24
Peak memory	202876 kb
Host	smart-4f78ecfd-25d7-4cda-89f5-109f69a0534b
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772845562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 44.sram_ctrl_partial_access_b2b.3772845562
Directory	/workspace/44.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/44.sram_ctrl_ram_cfg.3183853378
Short name	T935
Test name
Test status
Simulation time	49237203 ps
CPU time	0.77 seconds
Started	Jun 29 06:57:01 PM PDT 24
Finished	Jun 29 06:57:02 PM PDT 24
Peak memory	202868 kb
Host	smart-4afb8eeb-d769-4895-b167-e9f118da2548
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183853378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.3183853378
Directory	/workspace/44.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/44.sram_ctrl_regwen.2005241184
Short name	T559
Test name
Test status
Simulation time	50140193798 ps
CPU time	1163.29 seconds
Started	Jun 29 06:57:03 PM PDT 24
Finished	Jun 29 07:16:26 PM PDT 24
Peak memory	371612 kb
Host	smart-28c36e4e-bee3-4397-b636-b850f5aa3484
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005241184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.2005241184
Directory	/workspace/44.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/44.sram_ctrl_smoke.3383173247
Short name	T859
Test name
Test status
Simulation time	68757023 ps
CPU time	8.52 seconds
Started	Jun 29 06:57:02 PM PDT 24
Finished	Jun 29 06:57:11 PM PDT 24
Peak memory	239280 kb
Host	smart-d4344f4f-818c-4ddf-9436-3f930f75aa85
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383173247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.3383173247
Directory	/workspace/44.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.sram_ctrl_stress_all.3790829301
Short name	T865
Test name
Test status
Simulation time	417053124628 ps
CPU time	7607.7 seconds
Started	Jun 29 06:57:02 PM PDT 24
Finished	Jun 29 09:03:51 PM PDT 24
Peak memory	384000 kb
Host	smart-7cb97fea-b26d-4055-be60-4888dca8f78f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790829301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 44.sram_ctrl_stress_all.3790829301
Directory	/workspace/44.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2703185645
Short name	T55
Test name
Test status
Simulation time	3337681612 ps
CPU time	614.93 seconds
Started	Jun 29 06:57:02 PM PDT 24
Finished	Jun 29 07:07:18 PM PDT 24
Peak memory	371832 kb
Host	smart-41e018b8-82b8-4772-8403-0c87c7a7276d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2703185645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.2703185645
Directory	/workspace/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2346159429
Short name	T618
Test name
Test status
Simulation time	2265200889 ps
CPU time	237.84 seconds
Started	Jun 29 06:57:00 PM PDT 24
Finished	Jun 29 07:00:58 PM PDT 24
Peak memory	202936 kb
Host	smart-5f3efa76-f5ec-4978-a7d9-80b4fac9900a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346159429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_stress_pipeline.2346159429
Directory	/workspace/44.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2822561691
Short name	T329
Test name
Test status
Simulation time	203930503 ps
CPU time	43.59 seconds
Started	Jun 29 06:57:02 PM PDT 24
Finished	Jun 29 06:57:46 PM PDT 24
Peak memory	300980 kb
Host	smart-22d9c3ad-b353-4466-a2b4-f2f72534b307
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822561691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.2822561691
Directory	/workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/45.sram_ctrl_access_during_key_req.942530276
Short name	T856
Test name
Test status
Simulation time	65414863758 ps
CPU time	829.37 seconds
Started	Jun 29 06:57:15 PM PDT 24
Finished	Jun 29 07:11:05 PM PDT 24
Peak memory	363444 kb
Host	smart-1df6010d-0701-47ed-a609-c181a6a3db6f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942530276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 45.sram_ctrl_access_during_key_req.942530276
Directory	/workspace/45.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/45.sram_ctrl_alert_test.3391360067
Short name	T700
Test name
Test status
Simulation time	47911197 ps
CPU time	0.67 seconds
Started	Jun 29 06:57:13 PM PDT 24
Finished	Jun 29 06:57:14 PM PDT 24
Peak memory	202316 kb
Host	smart-44acc4ea-287e-4fd1-b02f-68befb47be1e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391360067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.3391360067
Directory	/workspace/45.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.sram_ctrl_bijection.1690303566
Short name	T474
Test name
Test status
Simulation time	10944842669 ps
CPU time	19.97 seconds
Started	Jun 29 06:57:15 PM PDT 24
Finished	Jun 29 06:57:36 PM PDT 24
Peak memory	202848 kb
Host	smart-80c419ea-1fe2-419d-99ee-01ee0147541b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690303566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection .1690303566
Directory	/workspace/45.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/45.sram_ctrl_executable.257444193
Short name	T574
Test name
Test status
Simulation time	10401740001 ps
CPU time	709.74 seconds
Started	Jun 29 06:57:13 PM PDT 24
Finished	Jun 29 07:09:03 PM PDT 24
Peak memory	374952 kb
Host	smart-ee04752e-46f5-40dd-9028-72f709a5d5eb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257444193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executabl e.257444193
Directory	/workspace/45.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/45.sram_ctrl_lc_escalation.288263190
Short name	T787
Test name
Test status
Simulation time	624348238 ps
CPU time	6.5 seconds
Started	Jun 29 06:57:16 PM PDT 24
Finished	Jun 29 06:57:23 PM PDT 24
Peak memory	211008 kb
Host	smart-5fe26957-3022-4656-a36e-b3bf53d1fa33
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288263190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_esc alation.288263190
Directory	/workspace/45.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/45.sram_ctrl_max_throughput.219682278
Short name	T155
Test name
Test status
Simulation time	135100498 ps
CPU time	136.5 seconds
Started	Jun 29 06:57:13 PM PDT 24
Finished	Jun 29 06:59:30 PM PDT 24
Peak memory	363308 kb
Host	smart-c81889d3-bc8d-4fa8-aafe-ada59202a163
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219682278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 45.sram_ctrl_max_throughput.219682278
Directory	/workspace/45.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1716482007
Short name	T850
Test name
Test status
Simulation time	118522242 ps
CPU time	3.32 seconds
Started	Jun 29 06:57:14 PM PDT 24
Finished	Jun 29 06:57:18 PM PDT 24
Peak memory	211116 kb
Host	smart-bf419420-caf9-49af-9b65-9625e0dcd5ec
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716482007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_mem_partial_access.1716482007
Directory	/workspace/45.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/45.sram_ctrl_mem_walk.3114274381
Short name	T522
Test name
Test status
Simulation time	96241989 ps
CPU time	5.28 seconds
Started	Jun 29 06:57:15 PM PDT 24
Finished	Jun 29 06:57:21 PM PDT 24
Peak memory	211116 kb
Host	smart-5e83809d-5bb3-4fb6-8e28-24b75a86bb56
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114274381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr l_mem_walk.3114274381
Directory	/workspace/45.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/45.sram_ctrl_multiple_keys.1584321384
Short name	T317
Test name
Test status
Simulation time	2404886517 ps
CPU time	1149.08 seconds
Started	Jun 29 06:57:16 PM PDT 24
Finished	Jun 29 07:16:26 PM PDT 24
Peak memory	368548 kb
Host	smart-32464ef7-0faf-4527-b32c-d083f0a619c2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584321384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi ple_keys.1584321384
Directory	/workspace/45.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/45.sram_ctrl_partial_access.3189699943
Short name	T666
Test name
Test status
Simulation time	3253109396 ps
CPU time	16.35 seconds
Started	Jun 29 06:57:17 PM PDT 24
Finished	Jun 29 06:57:33 PM PDT 24
Peak memory	202920 kb
Host	smart-fd1cf48a-9c83-4afb-ba31-86f90884859e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189699943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45. sram_ctrl_partial_access.3189699943
Directory	/workspace/45.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.102770733
Short name	T774
Test name
Test status
Simulation time	36379456364 ps
CPU time	503.02 seconds
Started	Jun 29 06:57:14 PM PDT 24
Finished	Jun 29 07:05:37 PM PDT 24
Peak memory	202940 kb
Host	smart-e94ef970-4ade-4e4e-a068-d7013cb47adc
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102770733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 45.sram_ctrl_partial_access_b2b.102770733
Directory	/workspace/45.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/45.sram_ctrl_ram_cfg.3929383118
Short name	T426
Test name
Test status
Simulation time	82713942 ps
CPU time	0.79 seconds
Started	Jun 29 06:57:16 PM PDT 24
Finished	Jun 29 06:57:17 PM PDT 24
Peak memory	202880 kb
Host	smart-32782840-64bb-469a-9456-326d6907fa92
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929383118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.3929383118
Directory	/workspace/45.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/45.sram_ctrl_regwen.2402846006
Short name	T267
Test name
Test status
Simulation time	42183068843 ps
CPU time	1251.72 seconds
Started	Jun 29 06:57:14 PM PDT 24
Finished	Jun 29 07:18:07 PM PDT 24
Peak memory	374752 kb
Host	smart-1bf0ee93-6bb1-462c-bcec-0406e3c846b3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402846006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.2402846006
Directory	/workspace/45.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/45.sram_ctrl_smoke.2356404238
Short name	T647
Test name
Test status
Simulation time	527751488 ps
CPU time	44.22 seconds
Started	Jun 29 06:57:01 PM PDT 24
Finished	Jun 29 06:57:45 PM PDT 24
Peak memory	313032 kb
Host	smart-0922cde0-048b-4464-aee8-43d6ad04c2d5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356404238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.2356404238
Directory	/workspace/45.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.sram_ctrl_stress_all.1351201939
Short name	T631
Test name
Test status
Simulation time	32258354031 ps
CPU time	3032.41 seconds
Started	Jun 29 06:57:15 PM PDT 24
Finished	Jun 29 07:47:49 PM PDT 24
Peak memory	376780 kb
Host	smart-c3c32f16-6f2a-4bed-92af-3e22bdc12aef
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351201939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 45.sram_ctrl_stress_all.1351201939
Directory	/workspace/45.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3074362694
Short name	T605
Test name
Test status
Simulation time	7800691955 ps
CPU time	420.54 seconds
Started	Jun 29 06:57:15 PM PDT 24
Finished	Jun 29 07:04:17 PM PDT 24
Peak memory	374908 kb
Host	smart-74a53b6b-054e-413d-a19e-77cc7392ec21
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3074362694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.3074362694
Directory	/workspace/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2074805867
Short name	T209
Test name
Test status
Simulation time	4644458899 ps
CPU time	229.46 seconds
Started	Jun 29 06:57:15 PM PDT 24
Finished	Jun 29 07:01:06 PM PDT 24
Peak memory	202876 kb
Host	smart-6307ff76-88b7-41a3-b968-4067ec8e847e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074805867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_stress_pipeline.2074805867
Directory	/workspace/45.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1634538189
Short name	T673
Test name
Test status
Simulation time	700359739 ps
CPU time	21.86 seconds
Started	Jun 29 06:57:14 PM PDT 24
Finished	Jun 29 06:57:36 PM PDT 24
Peak memory	277312 kb
Host	smart-04bcd023-50ab-41d9-bcf5-550ef6338963
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634538189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.1634538189
Directory	/workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/46.sram_ctrl_access_during_key_req.478868147
Short name	T719
Test name
Test status
Simulation time	8609184478 ps
CPU time	569.87 seconds
Started	Jun 29 06:57:14 PM PDT 24
Finished	Jun 29 07:06:44 PM PDT 24
Peak memory	371652 kb
Host	smart-401b3981-c6b9-40ca-8ffc-658826ec53b5
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478868147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 46.sram_ctrl_access_during_key_req.478868147
Directory	/workspace/46.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/46.sram_ctrl_alert_test.3209148094
Short name	T635
Test name
Test status
Simulation time	62713041 ps
CPU time	0.67 seconds
Started	Jun 29 06:57:16 PM PDT 24
Finished	Jun 29 06:57:18 PM PDT 24
Peak memory	202404 kb
Host	smart-e044a3c7-5075-40e1-b637-c13166813208
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209148094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.3209148094
Directory	/workspace/46.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.sram_ctrl_bijection.2366331991
Short name	T526
Test name
Test status
Simulation time	37783104422 ps
CPU time	79.73 seconds
Started	Jun 29 06:57:16 PM PDT 24
Finished	Jun 29 06:58:36 PM PDT 24
Peak memory	202912 kb
Host	smart-08814838-8ec2-45f6-b1f9-1dfeeb7f73e0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366331991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection .2366331991
Directory	/workspace/46.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/46.sram_ctrl_executable.1585028109
Short name	T697
Test name
Test status
Simulation time	18545943186 ps
CPU time	426.47 seconds
Started	Jun 29 06:57:16 PM PDT 24
Finished	Jun 29 07:04:23 PM PDT 24
Peak memory	359644 kb
Host	smart-cb211121-0618-4f79-a181-a4c835aa03ce
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585028109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab le.1585028109
Directory	/workspace/46.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/46.sram_ctrl_lc_escalation.4099079956
Short name	T420
Test name
Test status
Simulation time	743108463 ps
CPU time	7.23 seconds
Started	Jun 29 06:57:23 PM PDT 24
Finished	Jun 29 06:57:31 PM PDT 24
Peak memory	202840 kb
Host	smart-3e1cd9a8-509f-4d2c-b5ea-10c8eac58e44
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099079956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es calation.4099079956
Directory	/workspace/46.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/46.sram_ctrl_max_throughput.785426515
Short name	T190
Test name
Test status
Simulation time	260217558 ps
CPU time	139.94 seconds
Started	Jun 29 06:57:15 PM PDT 24
Finished	Jun 29 06:59:36 PM PDT 24
Peak memory	361236 kb
Host	smart-9962ee1d-2ee2-4dfe-8ee3-0e9cef93df7c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785426515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 46.sram_ctrl_max_throughput.785426515
Directory	/workspace/46.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1854660758
Short name	T339
Test name
Test status
Simulation time	203920964 ps
CPU time	3.16 seconds
Started	Jun 29 06:57:13 PM PDT 24
Finished	Jun 29 06:57:17 PM PDT 24
Peak memory	211024 kb
Host	smart-b50db98d-d467-4c1e-aa0a-5f800b41fba4
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854660758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_mem_partial_access.1854660758
Directory	/workspace/46.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/46.sram_ctrl_mem_walk.1809957002
Short name	T459
Test name
Test status
Simulation time	809608654 ps
CPU time	8.78 seconds
Started	Jun 29 06:57:23 PM PDT 24
Finished	Jun 29 06:57:33 PM PDT 24
Peak memory	210728 kb
Host	smart-fbdce39e-83e7-4d68-81ff-f35a935f2b4d
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809957002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr l_mem_walk.1809957002
Directory	/workspace/46.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/46.sram_ctrl_multiple_keys.3458319336
Short name	T634
Test name
Test status
Simulation time	11156975357 ps
CPU time	782.54 seconds
Started	Jun 29 06:57:20 PM PDT 24
Finished	Jun 29 07:10:23 PM PDT 24
Peak memory	360832 kb
Host	smart-d5f617e8-6ae9-4fc3-9021-9d630c1ba04c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458319336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi ple_keys.3458319336
Directory	/workspace/46.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/46.sram_ctrl_partial_access.1299067346
Short name	T566
Test name
Test status
Simulation time	3892803730 ps
CPU time	20.12 seconds
Started	Jun 29 06:57:15 PM PDT 24
Finished	Jun 29 06:57:36 PM PDT 24
Peak memory	202948 kb
Host	smart-136f2dac-0f4d-4e41-94dc-eb496dea8e55
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299067346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46. sram_ctrl_partial_access.1299067346
Directory	/workspace/46.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3668474740
Short name	T563
Test name
Test status
Simulation time	3531493055 ps
CPU time	242.12 seconds
Started	Jun 29 06:57:15 PM PDT 24
Finished	Jun 29 07:01:18 PM PDT 24
Peak memory	202940 kb
Host	smart-58818c98-e28f-4ae6-bc5e-ef954c94832e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668474740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 46.sram_ctrl_partial_access_b2b.3668474740
Directory	/workspace/46.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/46.sram_ctrl_ram_cfg.314549331
Short name	T894
Test name
Test status
Simulation time	347455783 ps
CPU time	0.82 seconds
Started	Jun 29 06:57:17 PM PDT 24
Finished	Jun 29 06:57:18 PM PDT 24
Peak memory	202872 kb
Host	smart-bf244b05-e408-4337-8993-1daead1497c3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314549331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.314549331
Directory	/workspace/46.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/46.sram_ctrl_regwen.1049002679
Short name	T905
Test name
Test status
Simulation time	8683572688 ps
CPU time	770.29 seconds
Started	Jun 29 06:57:23 PM PDT 24
Finished	Jun 29 07:10:14 PM PDT 24
Peak memory	360092 kb
Host	smart-e7c3b2cd-6abe-4431-85f9-4be1e24ca41c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049002679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.1049002679
Directory	/workspace/46.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/46.sram_ctrl_smoke.1042417464
Short name	T562
Test name
Test status
Simulation time	2401248964 ps
CPU time	85.41 seconds
Started	Jun 29 06:57:13 PM PDT 24
Finished	Jun 29 06:58:39 PM PDT 24
Peak memory	331648 kb
Host	smart-06fa6f74-111f-4516-b8b5-8db2b76737f3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042417464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.1042417464
Directory	/workspace/46.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.sram_ctrl_stress_all.3457760050
Short name	T908
Test name
Test status
Simulation time	28839524622 ps
CPU time	4078.63 seconds
Started	Jun 29 06:57:15 PM PDT 24
Finished	Jun 29 08:05:15 PM PDT 24
Peak memory	375716 kb
Host	smart-7179daba-a273-4a0d-9434-49d4a0d4f89f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457760050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 46.sram_ctrl_stress_all.3457760050
Directory	/workspace/46.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2185148942
Short name	T510
Test name
Test status
Simulation time	1157756908 ps
CPU time	45.2 seconds
Started	Jun 29 06:57:15 PM PDT 24
Finished	Jun 29 06:58:01 PM PDT 24
Peak memory	308324 kb
Host	smart-19d41265-a17f-47e3-bce6-22cd511e31dd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2185148942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.2185148942
Directory	/workspace/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2211488544
Short name	T476
Test name
Test status
Simulation time	4767894979 ps
CPU time	242.6 seconds
Started	Jun 29 06:57:23 PM PDT 24
Finished	Jun 29 07:01:26 PM PDT 24
Peak memory	202992 kb
Host	smart-be223925-d1b3-41bb-a380-39750ffc13dc
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211488544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_stress_pipeline.2211488544
Directory	/workspace/46.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.152182252
Short name	T665
Test name
Test status
Simulation time	497772423 ps
CPU time	45.58 seconds
Started	Jun 29 06:57:19 PM PDT 24
Finished	Jun 29 06:58:05 PM PDT 24
Peak memory	314988 kb
Host	smart-460cb33d-e82b-4d34-8360-1f9a97617990
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152182252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 46.sram_ctrl_throughput_w_partial_write.152182252
Directory	/workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/47.sram_ctrl_access_during_key_req.407319433
Short name	T468
Test name
Test status
Simulation time	7179657977 ps
CPU time	534.8 seconds
Started	Jun 29 06:57:15 PM PDT 24
Finished	Jun 29 07:06:11 PM PDT 24
Peak memory	373960 kb
Host	smart-923ecf73-e589-4f6b-9140-f518f6516143
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407319433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 47.sram_ctrl_access_during_key_req.407319433
Directory	/workspace/47.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/47.sram_ctrl_alert_test.3131681321
Short name	T731
Test name
Test status
Simulation time	71770160 ps
CPU time	0.63 seconds
Started	Jun 29 06:57:23 PM PDT 24
Finished	Jun 29 06:57:24 PM PDT 24
Peak memory	202656 kb
Host	smart-d30815fd-9930-4115-ae24-9f9e8a35a2f2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131681321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.3131681321
Directory	/workspace/47.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.sram_ctrl_bijection.2218242251
Short name	T817
Test name
Test status
Simulation time	6451650415 ps
CPU time	60.03 seconds
Started	Jun 29 06:57:16 PM PDT 24
Finished	Jun 29 06:58:17 PM PDT 24
Peak memory	202864 kb
Host	smart-fc596367-b442-4e8f-8fd5-587bd0e84304
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218242251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection .2218242251
Directory	/workspace/47.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/47.sram_ctrl_executable.3024783387
Short name	T484
Test name
Test status
Simulation time	3228230554 ps
CPU time	262.31 seconds
Started	Jun 29 06:57:21 PM PDT 24
Finished	Jun 29 07:01:44 PM PDT 24
Peak memory	343412 kb
Host	smart-370c0ee3-92cf-48df-9740-219d4e1fc067
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024783387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab le.3024783387
Directory	/workspace/47.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/47.sram_ctrl_lc_escalation.4261480172
Short name	T869
Test name
Test status
Simulation time	1901369878 ps
CPU time	6.84 seconds
Started	Jun 29 06:57:23 PM PDT 24
Finished	Jun 29 06:57:30 PM PDT 24
Peak memory	202864 kb
Host	smart-6cc7f7d3-701b-485f-8205-6ae05754d033
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261480172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es calation.4261480172
Directory	/workspace/47.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/47.sram_ctrl_max_throughput.3243065297
Short name	T826
Test name
Test status
Simulation time	124714697 ps
CPU time	103.06 seconds
Started	Jun 29 06:57:23 PM PDT 24
Finished	Jun 29 06:59:07 PM PDT 24
Peak memory	347060 kb
Host	smart-b0fe466e-eef7-49a2-a865-333a80a1e7ef
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243065297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 47.sram_ctrl_max_throughput.3243065297
Directory	/workspace/47.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/47.sram_ctrl_mem_partial_access.4193415680
Short name	T564
Test name
Test status
Simulation time	115549449 ps
CPU time	3.31 seconds
Started	Jun 29 06:57:19 PM PDT 24
Finished	Jun 29 06:57:23 PM PDT 24
Peak memory	211060 kb
Host	smart-e00390de-f20e-4da0-8846-733a3f8f30f5
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193415680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_mem_partial_access.4193415680
Directory	/workspace/47.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/47.sram_ctrl_mem_walk.2826240171
Short name	T283
Test name
Test status
Simulation time	2743874903 ps
CPU time	5.78 seconds
Started	Jun 29 06:57:21 PM PDT 24
Finished	Jun 29 06:57:28 PM PDT 24
Peak memory	203004 kb
Host	smart-c686aecb-0ef5-4792-a063-5837269d3086
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826240171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr l_mem_walk.2826240171
Directory	/workspace/47.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/47.sram_ctrl_multiple_keys.1848454037
Short name	T691
Test name
Test status
Simulation time	17962869010 ps
CPU time	459.2 seconds
Started	Jun 29 06:57:14 PM PDT 24
Finished	Jun 29 07:04:54 PM PDT 24
Peak memory	360204 kb
Host	smart-8f5b8363-8e6b-49f7-92f7-16d2261bfc04
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848454037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi ple_keys.1848454037
Directory	/workspace/47.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/47.sram_ctrl_partial_access.2397499006
Short name	T10
Test name
Test status
Simulation time	1342779831 ps
CPU time	4.43 seconds
Started	Jun 29 06:57:16 PM PDT 24
Finished	Jun 29 06:57:21 PM PDT 24
Peak memory	202820 kb
Host	smart-51b27d14-5438-4843-be52-8190a65b77f7
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397499006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47. sram_ctrl_partial_access.2397499006
Directory	/workspace/47.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1657632767
Short name	T528
Test name
Test status
Simulation time	5710984619 ps
CPU time	412.28 seconds
Started	Jun 29 06:57:19 PM PDT 24
Finished	Jun 29 07:04:12 PM PDT 24
Peak memory	202924 kb
Host	smart-35c9e20b-a2fa-4e06-b30d-2bb6d5397661
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657632767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_partial_access_b2b.1657632767
Directory	/workspace/47.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/47.sram_ctrl_ram_cfg.3413384167
Short name	T24
Test name
Test status
Simulation time	78404054 ps
CPU time	0.79 seconds
Started	Jun 29 06:57:20 PM PDT 24
Finished	Jun 29 06:57:21 PM PDT 24
Peak memory	202880 kb
Host	smart-99b85422-05e5-4b80-a767-8ae2c9f71fde
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413384167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.3413384167
Directory	/workspace/47.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/47.sram_ctrl_regwen.3225351833
Short name	T32
Test name
Test status
Simulation time	38511576646 ps
CPU time	917.84 seconds
Started	Jun 29 06:57:20 PM PDT 24
Finished	Jun 29 07:12:38 PM PDT 24
Peak memory	372960 kb
Host	smart-5fe77170-2084-4268-adeb-8dc14afbf0d1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225351833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.3225351833
Directory	/workspace/47.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/47.sram_ctrl_smoke.2183467416
Short name	T500
Test name
Test status
Simulation time	1836685421 ps
CPU time	10.98 seconds
Started	Jun 29 06:57:15 PM PDT 24
Finished	Jun 29 06:57:27 PM PDT 24
Peak memory	202788 kb
Host	smart-b845958d-3415-426e-a84f-b9fd3088ff79
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183467416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.2183467416
Directory	/workspace/47.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.sram_ctrl_stress_all.1057573385
Short name	T233
Test name
Test status
Simulation time	14776029797 ps
CPU time	2285.97 seconds
Started	Jun 29 06:57:23 PM PDT 24
Finished	Jun 29 07:35:29 PM PDT 24
Peak memory	375816 kb
Host	smart-ce9d94b4-a1e2-4da7-a795-15fcc7ca9585
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057573385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 47.sram_ctrl_stress_all.1057573385
Directory	/workspace/47.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3042152989
Short name	T685
Test name
Test status
Simulation time	2488896504 ps
CPU time	185.74 seconds
Started	Jun 29 06:57:21 PM PDT 24
Finished	Jun 29 07:00:27 PM PDT 24
Peak memory	353328 kb
Host	smart-1a68a40e-337d-48c9-9bf5-9b7c59c6c2e6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3042152989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.3042152989
Directory	/workspace/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3636163101
Short name	T203
Test name
Test status
Simulation time	3363863830 ps
CPU time	317.07 seconds
Started	Jun 29 06:57:15 PM PDT 24
Finished	Jun 29 07:02:32 PM PDT 24
Peak memory	202940 kb
Host	smart-e55c59b7-d30c-4faa-a110-b0725a04e942
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636163101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_stress_pipeline.3636163101
Directory	/workspace/47.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2706479381
Short name	T922
Test name
Test status
Simulation time	168706286 ps
CPU time	0.99 seconds
Started	Jun 29 06:57:14 PM PDT 24
Finished	Jun 29 06:57:15 PM PDT 24
Peak memory	202620 kb
Host	smart-55a76777-089f-4b82-80ef-5695d970438e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706479381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.2706479381
Directory	/workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/48.sram_ctrl_access_during_key_req.4052457562
Short name	T333
Test name
Test status
Simulation time	3374531152 ps
CPU time	514.43 seconds
Started	Jun 29 06:57:28 PM PDT 24
Finished	Jun 29 07:06:02 PM PDT 24
Peak memory	347432 kb
Host	smart-31308dc3-659e-4faa-9486-9b951369f5a5
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052457562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 48.sram_ctrl_access_during_key_req.4052457562
Directory	/workspace/48.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/48.sram_ctrl_alert_test.1568213115
Short name	T835
Test name
Test status
Simulation time	16729424 ps
CPU time	0.69 seconds
Started	Jun 29 06:57:30 PM PDT 24
Finished	Jun 29 06:57:31 PM PDT 24
Peak memory	202508 kb
Host	smart-b3073c2e-4b67-4aa5-81fb-2b83ee698164
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568213115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.1568213115
Directory	/workspace/48.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.sram_ctrl_bijection.2180365213
Short name	T153
Test name
Test status
Simulation time	1754521045 ps
CPU time	40.74 seconds
Started	Jun 29 06:57:22 PM PDT 24
Finished	Jun 29 06:58:04 PM PDT 24
Peak memory	202792 kb
Host	smart-c1140c5a-9d1c-4c89-9ded-350b850be232
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180365213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection .2180365213
Directory	/workspace/48.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/48.sram_ctrl_executable.2216381494
Short name	T140
Test name
Test status
Simulation time	15236087499 ps
CPU time	950.16 seconds
Started	Jun 29 06:57:31 PM PDT 24
Finished	Jun 29 07:13:22 PM PDT 24
Peak memory	375036 kb
Host	smart-6417cb1a-389f-47da-9d65-7110c74db1a4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216381494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executab le.2216381494
Directory	/workspace/48.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/48.sram_ctrl_lc_escalation.3293177786
Short name	T299
Test name
Test status
Simulation time	1241939665 ps
CPU time	5.77 seconds
Started	Jun 29 06:57:30 PM PDT 24
Finished	Jun 29 06:57:36 PM PDT 24
Peak memory	202780 kb
Host	smart-dfa04b58-3b6c-4a3b-be11-74bbc8426e07
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293177786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es calation.3293177786
Directory	/workspace/48.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/48.sram_ctrl_max_throughput.1944467806
Short name	T828
Test name
Test status
Simulation time	187449762 ps
CPU time	28.27 seconds
Started	Jun 29 06:57:23 PM PDT 24
Finished	Jun 29 06:57:51 PM PDT 24
Peak memory	300404 kb
Host	smart-2d67058b-ec97-4037-aee8-cb147fb82ad3
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944467806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 48.sram_ctrl_max_throughput.1944467806
Directory	/workspace/48.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/48.sram_ctrl_mem_partial_access.4288691168
Short name	T421
Test name
Test status
Simulation time	437586532 ps
CPU time	3.55 seconds
Started	Jun 29 06:57:29 PM PDT 24
Finished	Jun 29 06:57:33 PM PDT 24
Peak memory	211132 kb
Host	smart-2ff6ccda-b518-47b7-827c-9547ad66e8ba
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288691168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_mem_partial_access.4288691168
Directory	/workspace/48.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/48.sram_ctrl_mem_walk.1150204200
Short name	T151
Test name
Test status
Simulation time	77509553 ps
CPU time	4.93 seconds
Started	Jun 29 06:57:29 PM PDT 24
Finished	Jun 29 06:57:34 PM PDT 24
Peak memory	211092 kb
Host	smart-fb5429bd-cc5b-4e5f-aae2-81947fb0d4e6
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150204200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr l_mem_walk.1150204200
Directory	/workspace/48.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/48.sram_ctrl_multiple_keys.4158282458
Short name	T383
Test name
Test status
Simulation time	52014494889 ps
CPU time	1006.86 seconds
Started	Jun 29 06:57:21 PM PDT 24
Finished	Jun 29 07:14:08 PM PDT 24
Peak memory	373580 kb
Host	smart-9626b53d-ca15-47ce-bcc0-da5351120945
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158282458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi ple_keys.4158282458
Directory	/workspace/48.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/48.sram_ctrl_partial_access.1695086634
Short name	T867
Test name
Test status
Simulation time	5434260924 ps
CPU time	18.69 seconds
Started	Jun 29 06:57:21 PM PDT 24
Finished	Jun 29 06:57:40 PM PDT 24
Peak memory	202884 kb
Host	smart-4e015c0e-8c03-4c71-99c3-081c31618ea0
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695086634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48. sram_ctrl_partial_access.1695086634
Directory	/workspace/48.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1497678149
Short name	T841
Test name
Test status
Simulation time	15601502685 ps
CPU time	354.22 seconds
Started	Jun 29 06:57:21 PM PDT 24
Finished	Jun 29 07:03:16 PM PDT 24
Peak memory	202940 kb
Host	smart-297c60e0-1f96-442f-9ae3-a51b8dc02b53
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497678149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 48.sram_ctrl_partial_access_b2b.1497678149
Directory	/workspace/48.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/48.sram_ctrl_ram_cfg.3865942706
Short name	T224
Test name
Test status
Simulation time	109753006 ps
CPU time	0.77 seconds
Started	Jun 29 06:57:30 PM PDT 24
Finished	Jun 29 06:57:31 PM PDT 24
Peak memory	202836 kb
Host	smart-1364eb56-0f9f-48dd-8bc9-ce8895da765c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865942706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.3865942706
Directory	/workspace/48.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/48.sram_ctrl_regwen.3203225061
Short name	T527
Test name
Test status
Simulation time	71145260904 ps
CPU time	2265.44 seconds
Started	Jun 29 06:57:31 PM PDT 24
Finished	Jun 29 07:35:17 PM PDT 24
Peak memory	375776 kb
Host	smart-37003194-172f-4bfa-9cb7-c4c9d7118c4b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203225061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.3203225061
Directory	/workspace/48.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/48.sram_ctrl_smoke.3262698036
Short name	T116
Test name
Test status
Simulation time	443644618 ps
CPU time	2.24 seconds
Started	Jun 29 06:57:21 PM PDT 24
Finished	Jun 29 06:57:24 PM PDT 24
Peak memory	202860 kb
Host	smart-c4d6d080-636b-4c6c-abea-39e868913c12
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262698036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.3262698036
Directory	/workspace/48.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.sram_ctrl_stress_all.2398307662
Short name	T330
Test name
Test status
Simulation time	133669907423 ps
CPU time	2280.32 seconds
Started	Jun 29 06:57:29 PM PDT 24
Finished	Jun 29 07:35:30 PM PDT 24
Peak memory	377856 kb
Host	smart-dd292bca-509f-4413-bd4d-1b533295064d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398307662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 48.sram_ctrl_stress_all.2398307662
Directory	/workspace/48.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3834517559
Short name	T66
Test name
Test status
Simulation time	7501711351 ps
CPU time	90.22 seconds
Started	Jun 29 06:57:29 PM PDT 24
Finished	Jun 29 06:58:59 PM PDT 24
Peak memory	304228 kb
Host	smart-25adfd9f-61a0-4cde-b22c-2151c98fb667
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3834517559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.3834517559
Directory	/workspace/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.sram_ctrl_stress_pipeline.336751968
Short name	T553
Test name
Test status
Simulation time	4761383293 ps
CPU time	228.13 seconds
Started	Jun 29 06:57:23 PM PDT 24
Finished	Jun 29 07:01:11 PM PDT 24
Peak memory	202936 kb
Host	smart-47c023e6-95e9-4722-8ab9-5fb4f020e098
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336751968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48 .sram_ctrl_stress_pipeline.336751968
Directory	/workspace/48.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3225184027
Short name	T509
Test name
Test status
Simulation time	83082551 ps
CPU time	3 seconds
Started	Jun 29 06:57:29 PM PDT 24
Finished	Jun 29 06:57:32 PM PDT 24
Peak memory	219212 kb
Host	smart-51d697fc-527a-451d-838f-1dafa3f4b6f6
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225184027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.3225184027
Directory	/workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2265702406
Short name	T479
Test name
Test status
Simulation time	2217788877 ps
CPU time	405.88 seconds
Started	Jun 29 06:57:38 PM PDT 24
Finished	Jun 29 07:04:24 PM PDT 24
Peak memory	332616 kb
Host	smart-803b49fb-18e6-4e17-9191-f06b67607a8d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265702406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 49.sram_ctrl_access_during_key_req.2265702406
Directory	/workspace/49.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/49.sram_ctrl_alert_test.700768429
Short name	T751
Test name
Test status
Simulation time	84153886 ps
CPU time	0.67 seconds
Started	Jun 29 06:57:38 PM PDT 24
Finished	Jun 29 06:57:39 PM PDT 24
Peak memory	202596 kb
Host	smart-61ad43e1-6402-415f-aff9-b5dd124e6677
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700768429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.700768429
Directory	/workspace/49.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.sram_ctrl_bijection.2544828334
Short name	T404
Test name
Test status
Simulation time	15557815407 ps
CPU time	37.09 seconds
Started	Jun 29 06:57:30 PM PDT 24
Finished	Jun 29 06:58:07 PM PDT 24
Peak memory	202968 kb
Host	smart-a76177cb-9443-4648-8c09-41a14e288d63
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544828334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection .2544828334
Directory	/workspace/49.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/49.sram_ctrl_executable.2621418830
Short name	T305
Test name
Test status
Simulation time	1028917527 ps
CPU time	244.05 seconds
Started	Jun 29 06:57:40 PM PDT 24
Finished	Jun 29 07:01:44 PM PDT 24
Peak memory	366840 kb
Host	smart-22620a99-73a5-48c2-b459-75a156aa8a9c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621418830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab le.2621418830
Directory	/workspace/49.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/49.sram_ctrl_lc_escalation.2177398826
Short name	T556
Test name
Test status
Simulation time	318495709 ps
CPU time	3.45 seconds
Started	Jun 29 06:57:30 PM PDT 24
Finished	Jun 29 06:57:34 PM PDT 24
Peak memory	202780 kb
Host	smart-90c2be31-1ede-4fb5-8f26-a5c9fee3a184
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177398826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es calation.2177398826
Directory	/workspace/49.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/49.sram_ctrl_max_throughput.3697232561
Short name	T857
Test name
Test status
Simulation time	110756532 ps
CPU time	44.25 seconds
Started	Jun 29 06:57:30 PM PDT 24
Finished	Jun 29 06:58:15 PM PDT 24
Peak memory	300944 kb
Host	smart-ed2768b1-f6f9-4dcd-83da-80408b75f7c4
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697232561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 49.sram_ctrl_max_throughput.3697232561
Directory	/workspace/49.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2700482000
Short name	T452
Test name
Test status
Simulation time	1043980199 ps
CPU time	5.98 seconds
Started	Jun 29 06:57:38 PM PDT 24
Finished	Jun 29 06:57:44 PM PDT 24
Peak memory	211292 kb
Host	smart-fb2d5ed6-4ba4-43cc-80ec-994d9d2af0fb
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700482000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_mem_partial_access.2700482000
Directory	/workspace/49.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/49.sram_ctrl_mem_walk.3251614694
Short name	T885
Test name
Test status
Simulation time	1316469938 ps
CPU time	10.44 seconds
Started	Jun 29 06:57:37 PM PDT 24
Finished	Jun 29 06:57:48 PM PDT 24
Peak memory	211084 kb
Host	smart-c41c7f2f-2f0d-4741-a82f-29e511d6a662
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251614694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr l_mem_walk.3251614694
Directory	/workspace/49.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/49.sram_ctrl_multiple_keys.1024394912
Short name	T910
Test name
Test status
Simulation time	422691037 ps
CPU time	62.28 seconds
Started	Jun 29 06:57:29 PM PDT 24
Finished	Jun 29 06:58:31 PM PDT 24
Peak memory	305312 kb
Host	smart-038aacaf-839e-426a-aea5-3c361b0a4f65
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024394912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi ple_keys.1024394912
Directory	/workspace/49.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/49.sram_ctrl_partial_access.434821057
Short name	T282
Test name
Test status
Simulation time	119171982 ps
CPU time	4.47 seconds
Started	Jun 29 06:57:30 PM PDT 24
Finished	Jun 29 06:57:35 PM PDT 24
Peak memory	202756 kb
Host	smart-022b390e-1db1-4543-9fbe-e837337667e8
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434821057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.s ram_ctrl_partial_access.434821057
Directory	/workspace/49.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1343756138
Short name	T499
Test name
Test status
Simulation time	6146755152 ps
CPU time	224.03 seconds
Started	Jun 29 06:57:30 PM PDT 24
Finished	Jun 29 07:01:14 PM PDT 24
Peak memory	202924 kb
Host	smart-d570913e-044a-44a8-af45-ef423a37f182
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343756138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 49.sram_ctrl_partial_access_b2b.1343756138
Directory	/workspace/49.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/49.sram_ctrl_ram_cfg.3072942863
Short name	T640
Test name
Test status
Simulation time	28804538 ps
CPU time	0.79 seconds
Started	Jun 29 06:57:36 PM PDT 24
Finished	Jun 29 06:57:37 PM PDT 24
Peak memory	202808 kb
Host	smart-7628ee06-83b4-47ce-b53c-f38c0b4c1469
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072942863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.3072942863
Directory	/workspace/49.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/49.sram_ctrl_regwen.2699306371
Short name	T349
Test name
Test status
Simulation time	16071019594 ps
CPU time	1073.63 seconds
Started	Jun 29 06:57:36 PM PDT 24
Finished	Jun 29 07:15:31 PM PDT 24
Peak memory	368624 kb
Host	smart-bf9b94b1-e25c-437c-9778-f8602be17b23
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699306371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.2699306371
Directory	/workspace/49.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/49.sram_ctrl_smoke.4280877598
Short name	T228
Test name
Test status
Simulation time	2731737116 ps
CPU time	159.34 seconds
Started	Jun 29 06:57:32 PM PDT 24
Finished	Jun 29 07:00:11 PM PDT 24
Peak memory	368164 kb
Host	smart-f79861ef-4f7f-440d-bd2a-67dc64440ad1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280877598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.4280877598
Directory	/workspace/49.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.sram_ctrl_stress_all.2694962087
Short name	T215
Test name
Test status
Simulation time	47723665614 ps
CPU time	1402.78 seconds
Started	Jun 29 06:57:39 PM PDT 24
Finished	Jun 29 07:21:03 PM PDT 24
Peak memory	370660 kb
Host	smart-b977b24c-f9ee-4f8c-add9-95edddfe86b9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694962087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 49.sram_ctrl_stress_all.2694962087
Directory	/workspace/49.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3758181731
Short name	T47
Test name
Test status
Simulation time	1951887447 ps
CPU time	118.68 seconds
Started	Jun 29 06:57:35 PM PDT 24
Finished	Jun 29 06:59:34 PM PDT 24
Peak memory	336620 kb
Host	smart-f89b2311-6a40-4194-831f-0ae8406b8a45
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3758181731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.3758181731
Directory	/workspace/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.sram_ctrl_stress_pipeline.3645902972
Short name	T567
Test name
Test status
Simulation time	1216987868 ps
CPU time	116.17 seconds
Started	Jun 29 06:57:29 PM PDT 24
Finished	Jun 29 06:59:25 PM PDT 24
Peak memory	202820 kb
Host	smart-19ead893-6685-4a9c-ae87-0bbc21bd6285
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645902972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_stress_pipeline.3645902972
Directory	/workspace/49.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2985728125
Short name	T868
Test name
Test status
Simulation time	102194925 ps
CPU time	6.93 seconds
Started	Jun 29 06:57:29 PM PDT 24
Finished	Jun 29 06:57:37 PM PDT 24
Peak memory	235580 kb
Host	smart-a28e257c-b4fe-41f1-8189-00ecce78c390
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985728125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.2985728125
Directory	/workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/5.sram_ctrl_access_during_key_req.782466896
Short name	T472
Test name
Test status
Simulation time	2588747111 ps
CPU time	882.14 seconds
Started	Jun 29 06:54:15 PM PDT 24
Finished	Jun 29 07:08:58 PM PDT 24
Peak memory	373672 kb
Host	smart-e555f00c-61b0-4ef6-adcb-214e1b18512c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782466896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 5.sram_ctrl_access_during_key_req.782466896
Directory	/workspace/5.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/5.sram_ctrl_alert_test.2233556794
Short name	T175
Test name
Test status
Simulation time	21527527 ps
CPU time	0.73 seconds
Started	Jun 29 06:54:03 PM PDT 24
Finished	Jun 29 06:54:04 PM PDT 24
Peak memory	202304 kb
Host	smart-be23efe3-f65e-40a6-80b3-46aa8f3c927b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233556794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.2233556794
Directory	/workspace/5.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.sram_ctrl_bijection.3233768451
Short name	T534
Test name
Test status
Simulation time	1022942564 ps
CPU time	62.66 seconds
Started	Jun 29 06:54:09 PM PDT 24
Finished	Jun 29 06:55:13 PM PDT 24
Peak memory	202836 kb
Host	smart-91704861-2098-4e30-9f02-48222f8c80a1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233768451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection. 3233768451
Directory	/workspace/5.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/5.sram_ctrl_executable.4165608626
Short name	T535
Test name
Test status
Simulation time	15930664079 ps
CPU time	1896.25 seconds
Started	Jun 29 06:54:07 PM PDT 24
Finished	Jun 29 07:25:44 PM PDT 24
Peak memory	371736 kb
Host	smart-34e47a9e-07ed-4e00-ba41-5172d538b9a0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165608626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl e.4165608626
Directory	/workspace/5.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/5.sram_ctrl_lc_escalation.4231825738
Short name	T325
Test name
Test status
Simulation time	2029336029 ps
CPU time	8.48 seconds
Started	Jun 29 06:54:09 PM PDT 24
Finished	Jun 29 06:54:18 PM PDT 24
Peak memory	210988 kb
Host	smart-48a55d36-f330-43b4-a6a9-fc57da434164
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231825738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc alation.4231825738
Directory	/workspace/5.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/5.sram_ctrl_max_throughput.602345879
Short name	T242
Test name
Test status
Simulation time	162386268 ps
CPU time	23.79 seconds
Started	Jun 29 06:54:15 PM PDT 24
Finished	Jun 29 06:54:40 PM PDT 24
Peak memory	284436 kb
Host	smart-85c6ec45-3e32-4128-a15d-ebcbf9c75c2f
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602345879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.sram_ctrl_max_throughput.602345879
Directory	/workspace/5.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3292598670
Short name	T308
Test name
Test status
Simulation time	2883543040 ps
CPU time	6.01 seconds
Started	Jun 29 06:54:02 PM PDT 24
Finished	Jun 29 06:54:08 PM PDT 24
Peak memory	211180 kb
Host	smart-e1dab5fa-742b-4ff5-85ee-7f53bbee8874
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292598670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_mem_partial_access.3292598670
Directory	/workspace/5.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/5.sram_ctrl_mem_walk.2233486988
Short name	T243
Test name
Test status
Simulation time	2725114466 ps
CPU time	11.7 seconds
Started	Jun 29 06:54:05 PM PDT 24
Finished	Jun 29 06:54:17 PM PDT 24
Peak memory	211176 kb
Host	smart-256457e6-f2e5-4684-a0ef-947b164ddde0
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233486988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl _mem_walk.2233486988
Directory	/workspace/5.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/5.sram_ctrl_multiple_keys.815276112
Short name	T285
Test name
Test status
Simulation time	18255218950 ps
CPU time	1510.3 seconds
Started	Jun 29 06:54:15 PM PDT 24
Finished	Jun 29 07:19:26 PM PDT 24
Peak memory	371288 kb
Host	smart-495c0dca-34e6-426d-a083-f62df47734f8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815276112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multipl e_keys.815276112
Directory	/workspace/5.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/5.sram_ctrl_partial_access.3566804599
Short name	T642
Test name
Test status
Simulation time	579774018 ps
CPU time	79.98 seconds
Started	Jun 29 06:54:13 PM PDT 24
Finished	Jun 29 06:55:33 PM PDT 24
Peak memory	356092 kb
Host	smart-415e2879-8f39-4d1f-b8d0-0883826e2299
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566804599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s ram_ctrl_partial_access.3566804599
Directory	/workspace/5.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.860641054
Short name	T896
Test name
Test status
Simulation time	56156119744 ps
CPU time	379.82 seconds
Started	Jun 29 06:54:03 PM PDT 24
Finished	Jun 29 07:00:23 PM PDT 24
Peak memory	202952 kb
Host	smart-990362d6-6af6-4182-b049-b9e44840c3c4
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860641054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 5.sram_ctrl_partial_access_b2b.860641054
Directory	/workspace/5.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/5.sram_ctrl_ram_cfg.3092862461
Short name	T398
Test name
Test status
Simulation time	31020352 ps
CPU time	0.81 seconds
Started	Jun 29 06:54:10 PM PDT 24
Finished	Jun 29 06:54:12 PM PDT 24
Peak memory	202876 kb
Host	smart-54df9c17-ea2f-47a1-ade1-71fb12bf2341
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092862461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.3092862461
Directory	/workspace/5.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/5.sram_ctrl_regwen.2439150591
Short name	T822
Test name
Test status
Simulation time	2042873013 ps
CPU time	482.33 seconds
Started	Jun 29 06:54:09 PM PDT 24
Finished	Jun 29 07:02:11 PM PDT 24
Peak memory	357720 kb
Host	smart-5f658e3d-f246-4587-b655-b96a3dcffab5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439150591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.2439150591
Directory	/workspace/5.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/5.sram_ctrl_smoke.1632973475
Short name	T756
Test name
Test status
Simulation time	1106289251 ps
CPU time	21.59 seconds
Started	Jun 29 06:54:08 PM PDT 24
Finished	Jun 29 06:54:30 PM PDT 24
Peak memory	267904 kb
Host	smart-95235cac-11de-4d65-bf22-adf56a0de3ca
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632973475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.1632973475
Directory	/workspace/5.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.sram_ctrl_stress_all.210811402
Short name	T390
Test name
Test status
Simulation time	40377024041 ps
CPU time	3453.91 seconds
Started	Jun 29 06:54:09 PM PDT 24
Finished	Jun 29 07:51:44 PM PDT 24
Peak memory	376444 kb
Host	smart-77db644e-1fe3-45f2-8a1d-ba89497c5b9b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210811402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.sram_ctrl_stress_all.210811402
Directory	/workspace/5.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2687831056
Short name	T807
Test name
Test status
Simulation time	6297285632 ps
CPU time	302.91 seconds
Started	Jun 29 06:54:05 PM PDT 24
Finished	Jun 29 06:59:09 PM PDT 24
Peak memory	202972 kb
Host	smart-7d8a6840-ab6e-4daa-9a72-d50e4826cc17
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687831056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_stress_pipeline.2687831056
Directory	/workspace/5.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2961397440
Short name	T604
Test name
Test status
Simulation time	140446003 ps
CPU time	76.24 seconds
Started	Jun 29 06:54:06 PM PDT 24
Finished	Jun 29 06:55:23 PM PDT 24
Peak memory	331748 kb
Host	smart-542bf34e-b165-4d72-ba1d-cc644515eb70
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961397440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.2961397440
Directory	/workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1790546245
Short name	T191
Test name
Test status
Simulation time	6073626592 ps
CPU time	433.15 seconds
Started	Jun 29 06:54:04 PM PDT 24
Finished	Jun 29 07:01:18 PM PDT 24
Peak memory	365740 kb
Host	smart-5b78146f-9789-49b0-8ba8-c08345df5c2f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790546245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_access_during_key_req.1790546245
Directory	/workspace/6.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/6.sram_ctrl_alert_test.3466567550
Short name	T220
Test name
Test status
Simulation time	22060993 ps
CPU time	0.66 seconds
Started	Jun 29 06:54:07 PM PDT 24
Finished	Jun 29 06:54:08 PM PDT 24
Peak memory	202296 kb
Host	smart-64dd3a0f-e2b7-452a-b928-8d2a11732dba
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466567550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.3466567550
Directory	/workspace/6.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.sram_ctrl_bijection.71235333
Short name	T266
Test name
Test status
Simulation time	28758586906 ps
CPU time	89.23 seconds
Started	Jun 29 06:54:09 PM PDT 24
Finished	Jun 29 06:55:39 PM PDT 24
Peak memory	203000 kb
Host	smart-61d5e9fc-7857-4d73-a58d-6d9d5ec46f5f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71235333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.71235333
Directory	/workspace/6.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/6.sram_ctrl_executable.4178008210
Short name	T495
Test name
Test status
Simulation time	12891887025 ps
CPU time	898.35 seconds
Started	Jun 29 06:54:06 PM PDT 24
Finished	Jun 29 07:09:05 PM PDT 24
Peak memory	374764 kb
Host	smart-015b1379-0267-4ade-9c76-657c509849a6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178008210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl e.4178008210
Directory	/workspace/6.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/6.sram_ctrl_lc_escalation.3054918718
Short name	T458
Test name
Test status
Simulation time	1241954714 ps
CPU time	9.97 seconds
Started	Jun 29 06:54:06 PM PDT 24
Finished	Jun 29 06:54:16 PM PDT 24
Peak memory	214404 kb
Host	smart-0aa3ba7f-9435-44ee-bcb5-0ec1a2b7bbd4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054918718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc alation.3054918718
Directory	/workspace/6.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/6.sram_ctrl_max_throughput.751128749
Short name	T251
Test name
Test status
Simulation time	129654544 ps
CPU time	89.43 seconds
Started	Jun 29 06:54:04 PM PDT 24
Finished	Jun 29 06:55:35 PM PDT 24
Peak memory	347000 kb
Host	smart-5e1144ee-5e1e-488e-90ac-b5edc8781ebc
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751128749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 6.sram_ctrl_max_throughput.751128749
Directory	/workspace/6.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2692826098
Short name	T335
Test name
Test status
Simulation time	256675438 ps
CPU time	4.75 seconds
Started	Jun 29 06:54:09 PM PDT 24
Finished	Jun 29 06:54:15 PM PDT 24
Peak memory	211092 kb
Host	smart-4cd6228c-c93a-4022-9b7b-33532ad7fe70
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692826098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_mem_partial_access.2692826098
Directory	/workspace/6.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/6.sram_ctrl_mem_walk.188642885
Short name	T551
Test name
Test status
Simulation time	77328774 ps
CPU time	4.45 seconds
Started	Jun 29 06:54:07 PM PDT 24
Finished	Jun 29 06:54:12 PM PDT 24
Peak memory	202892 kb
Host	smart-016fd17f-03af-49bc-8e4d-a4d4c1295c17
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188642885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ mem_walk.188642885
Directory	/workspace/6.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/6.sram_ctrl_multiple_keys.2484710584
Short name	T716
Test name
Test status
Simulation time	18698342277 ps
CPU time	655.89 seconds
Started	Jun 29 06:54:08 PM PDT 24
Finished	Jun 29 07:05:04 PM PDT 24
Peak memory	370504 kb
Host	smart-d9776390-9f76-4520-b970-33ff2b000981
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484710584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip le_keys.2484710584
Directory	/workspace/6.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/6.sram_ctrl_partial_access.1371145785
Short name	T937
Test name
Test status
Simulation time	693948840 ps
CPU time	14.53 seconds
Started	Jun 29 06:54:07 PM PDT 24
Finished	Jun 29 06:54:22 PM PDT 24
Peak memory	255656 kb
Host	smart-f95b959c-a902-4f41-a79e-58418edb3b3e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371145785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s ram_ctrl_partial_access.1371145785
Directory	/workspace/6.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3500068751
Short name	T541
Test name
Test status
Simulation time	14160175741 ps
CPU time	379.1 seconds
Started	Jun 29 06:54:07 PM PDT 24
Finished	Jun 29 07:00:27 PM PDT 24
Peak memory	202908 kb
Host	smart-a9b3542b-e3aa-46d5-8b1e-487f9ce8370f
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500068751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.sram_ctrl_partial_access_b2b.3500068751
Directory	/workspace/6.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/6.sram_ctrl_ram_cfg.138972077
Short name	T795
Test name
Test status
Simulation time	50962928 ps
CPU time	0.77 seconds
Started	Jun 29 06:54:09 PM PDT 24
Finished	Jun 29 06:54:10 PM PDT 24
Peak memory	202868 kb
Host	smart-25b6de3c-e6eb-44a6-beb0-5604125e122f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138972077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.138972077
Directory	/workspace/6.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/6.sram_ctrl_regwen.4207685405
Short name	T654
Test name
Test status
Simulation time	1432423445 ps
CPU time	22.61 seconds
Started	Jun 29 06:54:06 PM PDT 24
Finished	Jun 29 06:54:30 PM PDT 24
Peak memory	284596 kb
Host	smart-f895e889-2e8a-47a6-a2b4-c3d9afc1c714
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207685405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.4207685405
Directory	/workspace/6.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/6.sram_ctrl_smoke.1024574739
Short name	T188
Test name
Test status
Simulation time	706554149 ps
CPU time	11.47 seconds
Started	Jun 29 06:54:09 PM PDT 24
Finished	Jun 29 06:54:21 PM PDT 24
Peak memory	202816 kb
Host	smart-398b32d8-1ee8-4513-9d04-cc93f8fe5fdb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024574739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.1024574739
Directory	/workspace/6.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.sram_ctrl_stress_all.901628524
Short name	T932
Test name
Test status
Simulation time	37031846816 ps
CPU time	1651.13 seconds
Started	Jun 29 06:54:09 PM PDT 24
Finished	Jun 29 07:21:40 PM PDT 24
Peak memory	383816 kb
Host	smart-e8fc30fa-d86d-40b2-924e-9dedacb34242
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901628524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.sram_ctrl_stress_all.901628524
Directory	/workspace/6.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/6.sram_ctrl_stress_pipeline.687305726
Short name	T491
Test name
Test status
Simulation time	9438987718 ps
CPU time	219.48 seconds
Started	Jun 29 06:54:04 PM PDT 24
Finished	Jun 29 06:57:45 PM PDT 24
Peak memory	202944 kb
Host	smart-17efef96-b785-4ac1-b0ae-3da2d064c67e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687305726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6. sram_ctrl_stress_pipeline.687305726
Directory	/workspace/6.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2184125990
Short name	T497
Test name
Test status
Simulation time	123790143 ps
CPU time	57.28 seconds
Started	Jun 29 06:54:12 PM PDT 24
Finished	Jun 29 06:55:10 PM PDT 24
Peak memory	318244 kb
Host	smart-375f2513-ca33-4bfc-9ad9-69255b7071fb
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184125990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.2184125990
Directory	/workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/7.sram_ctrl_access_during_key_req.949277791
Short name	T43
Test name
Test status
Simulation time	3577007150 ps
CPU time	1371.45 seconds
Started	Jun 29 06:54:11 PM PDT 24
Finished	Jun 29 07:17:03 PM PDT 24
Peak memory	374776 kb
Host	smart-af0bd282-fbf9-4a20-9874-fbbbc2a1b7ea
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949277791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 7.sram_ctrl_access_during_key_req.949277791
Directory	/workspace/7.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/7.sram_ctrl_alert_test.3275223726
Short name	T505
Test name
Test status
Simulation time	13996944 ps
CPU time	0.67 seconds
Started	Jun 29 06:54:14 PM PDT 24
Finished	Jun 29 06:54:15 PM PDT 24
Peak memory	202624 kb
Host	smart-c300e735-451c-48ae-9933-ad1cae326ce8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275223726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.3275223726
Directory	/workspace/7.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.sram_ctrl_bijection.170261005
Short name	T519
Test name
Test status
Simulation time	4100954241 ps
CPU time	64.02 seconds
Started	Jun 29 06:54:06 PM PDT 24
Finished	Jun 29 06:55:10 PM PDT 24
Peak memory	202924 kb
Host	smart-2df71a22-12ca-48ea-8e52-db6397894408
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170261005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.170261005
Directory	/workspace/7.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/7.sram_ctrl_executable.447559341
Short name	T168
Test name
Test status
Simulation time	1254117875 ps
CPU time	27.06 seconds
Started	Jun 29 06:54:20 PM PDT 24
Finished	Jun 29 06:54:47 PM PDT 24
Peak memory	235236 kb
Host	smart-4c8e2fc8-fb2b-452a-befb-2c6ec25ec599
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447559341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable .447559341
Directory	/workspace/7.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/7.sram_ctrl_lc_escalation.1473041457
Short name	T877
Test name
Test status
Simulation time	537205385 ps
CPU time	7.32 seconds
Started	Jun 29 06:54:08 PM PDT 24
Finished	Jun 29 06:54:16 PM PDT 24
Peak memory	202760 kb
Host	smart-293f1bdb-e8f9-4074-a094-6ba3860ab04c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473041457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc alation.1473041457
Directory	/workspace/7.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/7.sram_ctrl_max_throughput.1986332337
Short name	T573
Test name
Test status
Simulation time	412629819 ps
CPU time	64.67 seconds
Started	Jun 29 06:54:07 PM PDT 24
Finished	Jun 29 06:55:12 PM PDT 24
Peak memory	312920 kb
Host	smart-d91409ff-c28b-4906-872c-72c555c14848
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986332337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_max_throughput.1986332337
Directory	/workspace/7.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/7.sram_ctrl_mem_partial_access.2991632684
Short name	T271
Test name
Test status
Simulation time	166757407 ps
CPU time	5.45 seconds
Started	Jun 29 06:54:12 PM PDT 24
Finished	Jun 29 06:54:18 PM PDT 24
Peak memory	211084 kb
Host	smart-66778844-1575-4fe9-911c-b28ab0683af4
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991632684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_mem_partial_access.2991632684
Directory	/workspace/7.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/7.sram_ctrl_mem_walk.2794433525
Short name	T818
Test name
Test status
Simulation time	234656151 ps
CPU time	5.77 seconds
Started	Jun 29 06:54:11 PM PDT 24
Finished	Jun 29 06:54:17 PM PDT 24
Peak memory	210992 kb
Host	smart-b30eb2b2-4ae7-4afa-a734-2de22dea7bb6
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794433525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl _mem_walk.2794433525
Directory	/workspace/7.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/7.sram_ctrl_multiple_keys.3019623557
Short name	T675
Test name
Test status
Simulation time	8159352854 ps
CPU time	759.28 seconds
Started	Jun 29 06:54:08 PM PDT 24
Finished	Jun 29 07:06:48 PM PDT 24
Peak memory	370688 kb
Host	smart-1c01ae57-395b-45c5-a96f-c91fe533492e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019623557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip le_keys.3019623557
Directory	/workspace/7.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/7.sram_ctrl_partial_access.1185259464
Short name	T275
Test name
Test status
Simulation time	398829861 ps
CPU time	13.06 seconds
Started	Jun 29 06:54:12 PM PDT 24
Finished	Jun 29 06:54:25 PM PDT 24
Peak memory	260368 kb
Host	smart-de4a06ee-a15f-45ec-b0df-9dee24a5496e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185259464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s ram_ctrl_partial_access.1185259464
Directory	/workspace/7.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1541016034
Short name	T613
Test name
Test status
Simulation time	13946090636 ps
CPU time	342.61 seconds
Started	Jun 29 06:54:09 PM PDT 24
Finished	Jun 29 06:59:52 PM PDT 24
Peak memory	202948 kb
Host	smart-36da997a-97e1-4fd7-9709-8511596a1196
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541016034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 7.sram_ctrl_partial_access_b2b.1541016034
Directory	/workspace/7.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/7.sram_ctrl_ram_cfg.3911471195
Short name	T717
Test name
Test status
Simulation time	87102115 ps
CPU time	0.79 seconds
Started	Jun 29 06:54:12 PM PDT 24
Finished	Jun 29 06:54:13 PM PDT 24
Peak memory	202888 kb
Host	smart-a51b6f8d-1a37-43c6-a074-0ba4b9e39982
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911471195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.3911471195
Directory	/workspace/7.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/7.sram_ctrl_regwen.2518059050
Short name	T44
Test name
Test status
Simulation time	22479279612 ps
CPU time	1233.32 seconds
Started	Jun 29 06:54:12 PM PDT 24
Finished	Jun 29 07:14:46 PM PDT 24
Peak memory	374752 kb
Host	smart-7ed54d54-920e-478a-bedc-aad63609de84
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518059050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.2518059050
Directory	/workspace/7.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/7.sram_ctrl_smoke.1503937963
Short name	T757
Test name
Test status
Simulation time	104156241 ps
CPU time	32.12 seconds
Started	Jun 29 06:54:11 PM PDT 24
Finished	Jun 29 06:54:44 PM PDT 24
Peak memory	284860 kb
Host	smart-b0d2a737-41bb-41d5-a02c-3466b8d99120
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503937963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.1503937963
Directory	/workspace/7.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1567719323
Short name	T53
Test name
Test status
Simulation time	3312888608 ps
CPU time	321.03 seconds
Started	Jun 29 06:54:10 PM PDT 24
Finished	Jun 29 06:59:32 PM PDT 24
Peak memory	371468 kb
Host	smart-db0040b1-b741-42a4-bb4b-3291e144f26a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1567719323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.1567719323
Directory	/workspace/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1229906418
Short name	T363
Test name
Test status
Simulation time	2346021321 ps
CPU time	216.63 seconds
Started	Jun 29 06:54:11 PM PDT 24
Finished	Jun 29 06:57:49 PM PDT 24
Peak memory	202652 kb
Host	smart-a97298a2-064f-4827-9f4f-102845efde9f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229906418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_stress_pipeline.1229906418
Directory	/workspace/7.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.400170994
Short name	T369
Test name
Test status
Simulation time	54987923 ps
CPU time	4.34 seconds
Started	Jun 29 06:54:15 PM PDT 24
Finished	Jun 29 06:54:20 PM PDT 24
Peak memory	223928 kb
Host	smart-d99b4a83-fd16-4d40-91b2-7b9177712518
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400170994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_throughput_w_partial_write.400170994
Directory	/workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2850622975
Short name	T749
Test name
Test status
Simulation time	7434091713 ps
CPU time	710.56 seconds
Started	Jun 29 06:54:13 PM PDT 24
Finished	Jun 29 07:06:05 PM PDT 24
Peak memory	371660 kb
Host	smart-95a8886e-63a5-4ddb-8256-e5782ecf5fd8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850622975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_access_during_key_req.2850622975
Directory	/workspace/8.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/8.sram_ctrl_alert_test.1322509938
Short name	T915
Test name
Test status
Simulation time	13628158 ps
CPU time	0.64 seconds
Started	Jun 29 06:54:13 PM PDT 24
Finished	Jun 29 06:54:14 PM PDT 24
Peak memory	202548 kb
Host	smart-83ca41c6-e7fa-49ea-bc33-7b648996343f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322509938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.1322509938
Directory	/workspace/8.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.sram_ctrl_bijection.216389651
Short name	T760
Test name
Test status
Simulation time	2415244252 ps
CPU time	47.38 seconds
Started	Jun 29 06:54:14 PM PDT 24
Finished	Jun 29 06:55:02 PM PDT 24
Peak memory	202896 kb
Host	smart-104c0617-690d-4bbf-92fe-be9a3344921f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216389651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.216389651
Directory	/workspace/8.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/8.sram_ctrl_executable.2791851846
Short name	T748
Test name
Test status
Simulation time	34134141190 ps
CPU time	1468.39 seconds
Started	Jun 29 06:54:10 PM PDT 24
Finished	Jun 29 07:18:39 PM PDT 24
Peak memory	374708 kb
Host	smart-45dce75c-c0fb-4f23-a5f0-f340dd3f224e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791851846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl e.2791851846
Directory	/workspace/8.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/8.sram_ctrl_lc_escalation.3183828821
Short name	T498
Test name
Test status
Simulation time	2186401277 ps
CPU time	7.14 seconds
Started	Jun 29 06:54:13 PM PDT 24
Finished	Jun 29 06:54:21 PM PDT 24
Peak memory	201940 kb
Host	smart-104e2efd-ff5b-4a26-bd02-f9a1ab0f2a82
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183828821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc alation.3183828821
Directory	/workspace/8.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/8.sram_ctrl_max_throughput.3915552454
Short name	T316
Test name
Test status
Simulation time	120427725 ps
CPU time	109.15 seconds
Started	Jun 29 06:54:14 PM PDT 24
Finished	Jun 29 06:56:04 PM PDT 24
Peak memory	341868 kb
Host	smart-a08f78d5-9328-40ec-964f-ff88356ebbf3
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915552454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 8.sram_ctrl_max_throughput.3915552454
Directory	/workspace/8.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/8.sram_ctrl_mem_partial_access.2411095380
Short name	T728
Test name
Test status
Simulation time	196624912 ps
CPU time	3.15 seconds
Started	Jun 29 06:54:14 PM PDT 24
Finished	Jun 29 06:54:17 PM PDT 24
Peak memory	211068 kb
Host	smart-25be1a55-351e-43c1-bdee-64d6b4327800
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411095380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_mem_partial_access.2411095380
Directory	/workspace/8.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/8.sram_ctrl_mem_walk.2422071875
Short name	T482
Test name
Test status
Simulation time	458084601 ps
CPU time	9.62 seconds
Started	Jun 29 06:54:11 PM PDT 24
Finished	Jun 29 06:54:21 PM PDT 24
Peak memory	202872 kb
Host	smart-ed0921eb-ae61-4765-b6f5-bee11e330479
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422071875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl _mem_walk.2422071875
Directory	/workspace/8.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/8.sram_ctrl_multiple_keys.1015134787
Short name	T273
Test name
Test status
Simulation time	13044852601 ps
CPU time	807.93 seconds
Started	Jun 29 06:54:17 PM PDT 24
Finished	Jun 29 07:07:46 PM PDT 24
Peak memory	358036 kb
Host	smart-66ed9542-4ea7-44fa-9b2f-a8ada015e40d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015134787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip le_keys.1015134787
Directory	/workspace/8.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/8.sram_ctrl_partial_access.2574057634
Short name	T298
Test name
Test status
Simulation time	109518637 ps
CPU time	3.29 seconds
Started	Jun 29 06:54:13 PM PDT 24
Finished	Jun 29 06:54:17 PM PDT 24
Peak memory	210692 kb
Host	smart-bc54f5d1-bc3f-40f6-a21f-e7c35e589b24
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574057634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s ram_ctrl_partial_access.2574057634
Directory	/workspace/8.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.732235129
Short name	T198
Test name
Test status
Simulation time	4518915585 ps
CPU time	312.59 seconds
Started	Jun 29 06:54:12 PM PDT 24
Finished	Jun 29 06:59:25 PM PDT 24
Peak memory	202888 kb
Host	smart-1e61452c-bc82-4f50-9d80-71ce01e675ce
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732235129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 8.sram_ctrl_partial_access_b2b.732235129
Directory	/workspace/8.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/8.sram_ctrl_ram_cfg.526076085
Short name	T166
Test name
Test status
Simulation time	29362921 ps
CPU time	0.8 seconds
Started	Jun 29 06:54:13 PM PDT 24
Finished	Jun 29 06:54:15 PM PDT 24
Peak memory	201792 kb
Host	smart-8136fda1-bb7d-4686-813f-53c465d3d623
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526076085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.526076085
Directory	/workspace/8.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/8.sram_ctrl_regwen.308283880
Short name	T187
Test name
Test status
Simulation time	14886680123 ps
CPU time	1032.56 seconds
Started	Jun 29 06:54:14 PM PDT 24
Finished	Jun 29 07:11:27 PM PDT 24
Peak memory	368568 kb
Host	smart-6d3b3d94-7427-4ffb-b597-858bf2d08e89
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308283880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.308283880
Directory	/workspace/8.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/8.sram_ctrl_smoke.2925045697
Short name	T547
Test name
Test status
Simulation time	113674264 ps
CPU time	1.73 seconds
Started	Jun 29 06:54:20 PM PDT 24
Finished	Jun 29 06:54:23 PM PDT 24
Peak memory	202808 kb
Host	smart-751f9624-3883-42be-ba28-b96bc6d51001
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925045697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.2925045697
Directory	/workspace/8.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.sram_ctrl_stress_all.2210111315
Short name	T924
Test name
Test status
Simulation time	192530138927 ps
CPU time	3755.38 seconds
Started	Jun 29 06:54:13 PM PDT 24
Finished	Jun 29 07:56:49 PM PDT 24
Peak memory	376912 kb
Host	smart-665b97fe-e4b1-4a31-8598-16b28d2a984b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210111315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 8.sram_ctrl_stress_all.2210111315
Directory	/workspace/8.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/8.sram_ctrl_stress_pipeline.4185333069
Short name	T477
Test name
Test status
Simulation time	3597607890 ps
CPU time	366.95 seconds
Started	Jun 29 06:54:18 PM PDT 24
Finished	Jun 29 07:00:26 PM PDT 24
Peak memory	202956 kb
Host	smart-5fe11eb5-794e-482e-9418-b168416c6fa6
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185333069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_stress_pipeline.4185333069
Directory	/workspace/8.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3802871401
Short name	T469
Test name
Test status
Simulation time	117411248 ps
CPU time	43.36 seconds
Started	Jun 29 06:54:13 PM PDT 24
Finished	Jun 29 06:54:57 PM PDT 24
Peak memory	300364 kb
Host	smart-d6ef93d2-a6bb-4d8b-b575-255176b9a58d
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802871401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.3802871401
Directory	/workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3411169737
Short name	T599
Test name
Test status
Simulation time	8735684251 ps
CPU time	419.7 seconds
Started	Jun 29 06:54:11 PM PDT 24
Finished	Jun 29 07:01:11 PM PDT 24
Peak memory	363256 kb
Host	smart-11f5523b-60e1-493d-b55f-9a76c39f3a98
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411169737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_access_during_key_req.3411169737
Directory	/workspace/9.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/9.sram_ctrl_alert_test.2424207024
Short name	T160
Test name
Test status
Simulation time	12304206 ps
CPU time	0.63 seconds
Started	Jun 29 06:54:20 PM PDT 24
Finished	Jun 29 06:54:22 PM PDT 24
Peak memory	202592 kb
Host	smart-ad4df5a7-b9f2-4cad-8557-e39f51fdb296
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424207024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.2424207024
Directory	/workspace/9.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.sram_ctrl_bijection.780044644
Short name	T659
Test name
Test status
Simulation time	7232706673 ps
CPU time	81.25 seconds
Started	Jun 29 06:54:13 PM PDT 24
Finished	Jun 29 06:55:35 PM PDT 24
Peak memory	202992 kb
Host	smart-ee7d53fc-27c4-4eff-8358-9f331516b587
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780044644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.780044644
Directory	/workspace/9.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/9.sram_ctrl_executable.1676298118
Short name	T742
Test name
Test status
Simulation time	12237113903 ps
CPU time	59.45 seconds
Started	Jun 29 06:54:14 PM PDT 24
Finished	Jun 29 06:55:14 PM PDT 24
Peak memory	235680 kb
Host	smart-30b513ad-7ce8-4f0a-b3a6-8b7597a48cd8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676298118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl e.1676298118
Directory	/workspace/9.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/9.sram_ctrl_lc_escalation.3250007966
Short name	T811
Test name
Test status
Simulation time	594681346 ps
CPU time	8.11 seconds
Started	Jun 29 06:54:10 PM PDT 24
Finished	Jun 29 06:54:19 PM PDT 24
Peak memory	202876 kb
Host	smart-8f896496-83cf-4b02-ab86-a4915f22fbb3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250007966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc alation.3250007966
Directory	/workspace/9.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/9.sram_ctrl_max_throughput.3980083522
Short name	T832
Test name
Test status
Simulation time	1377864759 ps
CPU time	85.17 seconds
Started	Jun 29 06:54:11 PM PDT 24
Finished	Jun 29 06:55:36 PM PDT 24
Peak memory	361252 kb
Host	smart-620aca95-7b71-47ff-83fd-dcc3d578c3fe
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980083522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_max_throughput.3980083522
Directory	/workspace/9.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1340174749
Short name	T827
Test name
Test status
Simulation time	159073084 ps
CPU time	5.34 seconds
Started	Jun 29 06:54:19 PM PDT 24
Finished	Jun 29 06:54:25 PM PDT 24
Peak memory	211048 kb
Host	smart-da5a5818-508b-446b-87ae-d37b0acb45d2
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340174749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_mem_partial_access.1340174749
Directory	/workspace/9.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/9.sram_ctrl_mem_walk.2388887290
Short name	T51
Test name
Test status
Simulation time	2493605747 ps
CPU time	5.93 seconds
Started	Jun 29 06:54:20 PM PDT 24
Finished	Jun 29 06:54:27 PM PDT 24
Peak memory	211200 kb
Host	smart-ebf5c88a-0687-4068-ae5c-4014aa3357b6
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388887290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl _mem_walk.2388887290
Directory	/workspace/9.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/9.sram_ctrl_multiple_keys.620757573
Short name	T429
Test name
Test status
Simulation time	13243715280 ps
CPU time	570.97 seconds
Started	Jun 29 06:54:13 PM PDT 24
Finished	Jun 29 07:03:44 PM PDT 24
Peak memory	372960 kb
Host	smart-d8823e3e-572a-42e1-adbd-f15755cadd46
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620757573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multipl e_keys.620757573
Directory	/workspace/9.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/9.sram_ctrl_partial_access.3248221911
Short name	T9
Test name
Test status
Simulation time	453860294 ps
CPU time	37.51 seconds
Started	Jun 29 06:54:13 PM PDT 24
Finished	Jun 29 06:54:51 PM PDT 24
Peak memory	283656 kb
Host	smart-bc631253-eea4-4296-800c-8214507fd037
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248221911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s ram_ctrl_partial_access.3248221911
Directory	/workspace/9.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2327780259
Short name	T517
Test name
Test status
Simulation time	4674997968 ps
CPU time	158.5 seconds
Started	Jun 29 06:54:11 PM PDT 24
Finished	Jun 29 06:56:51 PM PDT 24
Peak memory	202920 kb
Host	smart-014bc5d4-6bd2-487c-af23-886853f56c5f
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327780259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.sram_ctrl_partial_access_b2b.2327780259
Directory	/workspace/9.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/9.sram_ctrl_ram_cfg.3791415569
Short name	T701
Test name
Test status
Simulation time	41233181 ps
CPU time	0.81 seconds
Started	Jun 29 06:54:13 PM PDT 24
Finished	Jun 29 06:54:15 PM PDT 24
Peak memory	202856 kb
Host	smart-dff37f49-4246-425a-a216-d7c36b41d3f2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791415569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.3791415569
Directory	/workspace/9.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/9.sram_ctrl_regwen.2038948260
Short name	T681
Test name
Test status
Simulation time	329458423 ps
CPU time	92.12 seconds
Started	Jun 29 06:54:11 PM PDT 24
Finished	Jun 29 06:55:44 PM PDT 24
Peak memory	314588 kb
Host	smart-ee2973f9-2e8c-42a8-81ed-f31265e14a26
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038948260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.2038948260
Directory	/workspace/9.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/9.sram_ctrl_smoke.4041261154
Short name	T812
Test name
Test status
Simulation time	49631410 ps
CPU time	1.8 seconds
Started	Jun 29 06:54:11 PM PDT 24
Finished	Jun 29 06:54:14 PM PDT 24
Peak memory	202816 kb
Host	smart-8eddec86-c1d8-47fc-82c7-90f3eb918401
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041261154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.4041261154
Directory	/workspace/9.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.sram_ctrl_stress_all.3219232496
Short name	T523
Test name
Test status
Simulation time	249839166058 ps
CPU time	4201.33 seconds
Started	Jun 29 06:54:18 PM PDT 24
Finished	Jun 29 08:04:21 PM PDT 24
Peak memory	375652 kb
Host	smart-267c36a1-64b1-4084-93f2-9225e0d0fbf7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219232496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 9.sram_ctrl_stress_all.3219232496
Directory	/workspace/9.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.529314329
Short name	T108
Test name
Test status
Simulation time	1358080239 ps
CPU time	160.56 seconds
Started	Jun 29 06:54:21 PM PDT 24
Finished	Jun 29 06:57:02 PM PDT 24
Peak memory	351580 kb
Host	smart-b2773dea-0596-4b72-906a-c7fbf7823d5a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=529314329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.529314329
Directory	/workspace/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1724915792
Short name	T410
Test name
Test status
Simulation time	10983689905 ps
CPU time	265.7 seconds
Started	Jun 29 06:54:13 PM PDT 24
Finished	Jun 29 06:58:39 PM PDT 24
Peak memory	202952 kb
Host	smart-c9ee1dd7-a335-4163-9efb-8e0ffc98fc0c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724915792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_stress_pipeline.1724915792
Directory	/workspace/9.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.434703396
Short name	T409
Test name
Test status
Simulation time	98899770 ps
CPU time	27.98 seconds
Started	Jun 29 06:54:20 PM PDT 24
Finished	Jun 29 06:54:49 PM PDT 24
Peak memory	286636 kb
Host	smart-780f5e0c-9648-4ad3-85a3-273c2bdc9ebc
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434703396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_throughput_w_partial_write.434703396
Directory	/workspace/9.sram_ctrl_throughput_w_partial_write/latest