Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14003820	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

61706476

1

T1

514433

T3

276375

T5

14336

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37736857	1			T1	282471		T3	151952		T5	7168
values[0x0]	17588726	1			T1	136370		T3	73073		T5	3569
values[0x1]	20384713	1			T1	146729		T3	78786		T5	3599

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6976648	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

68733648

1

T1

540178

T3

290213

T5

14336

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	309504	1			T1	2214		T3	1144		T5	127
valid_sources[0x01]	319135	1			T1	2183		T3	1137		T5	178
valid_sources[0x02]	269338	1			T1	2165		T3	1176		T5	125
valid_sources[0x03]	336749	1			T1	2315		T3	1097		T4	8
valid_sources[0x04]	285062	1			T1	2266		T3	1175		T5	245
valid_sources[0x05]	256380	1			T1	2163		T3	1125		T5	71
valid_sources[0x06]	357504	1			T1	2151		T3	1118		T5	71
valid_sources[0x07]	285320	1			T1	2195		T3	1178		T5	3
valid_sources[0x08]	303647	1			T1	2194		T3	1180		T5	10
valid_sources[0x09]	298317	1			T1	2238		T3	1143		T4	45
valid_sources[0x0a]	308631	1			T1	2255		T3	1115		T5	18
valid_sources[0x0b]	314394	1			T1	2187		T3	1145		T5	28
valid_sources[0x0c]	309219	1			T1	2277		T3	1105		T5	204
valid_sources[0x0d]	385039	1			T1	2268		T3	1153		T5	104
valid_sources[0x0e]	283089	1			T1	2186		T3	1152		T4	23
valid_sources[0x0f]	280000	1			T1	2157		T3	1177		T5	46
valid_sources[0x10]	261088	1			T1	2190		T3	1264		T5	34
valid_sources[0x11]	333647	1			T1	2262		T3	1219		T5	137
valid_sources[0x12]	282860	1			T1	2217		T3	1187		T5	66
valid_sources[0x13]	300939	1			T1	2260		T3	1177		T4	20
valid_sources[0x14]	310714	1			T1	2109		T3	1192		T4	26
valid_sources[0x15]	384872	1			T1	2241		T3	1205		T4	19
valid_sources[0x16]	332628	1			T1	2257		T3	1233		T5	105
valid_sources[0x17]	327550	1			T1	2279		T3	1224		T5	46
valid_sources[0x18]	297256	1			T1	2152		T3	1205		T5	86
valid_sources[0x19]	247399	1			T1	2210		T3	1159		T5	22
valid_sources[0x1a]	270415	1			T1	2225		T3	1173		T5	203
valid_sources[0x1b]	285098	1			T1	2133		T3	1165		T5	60
valid_sources[0x1c]	343237	1			T1	2155		T3	1239		T5	18
valid_sources[0x1d]	275266	1			T1	2262		T3	1153		T5	68
valid_sources[0x1e]	253162	1			T1	2236		T3	1194		T5	21
valid_sources[0x1f]	269129	1			T1	2193		T3	1197		T5	129
valid_sources[0x20]	290407	1			T1	2201		T3	1249		T5	47
valid_sources[0x21]	311289	1			T1	2206		T3	1212		T5	6
valid_sources[0x22]	263917	1			T1	2131		T3	1126		T5	139
valid_sources[0x23]	262100	1			T1	2251		T3	1239		T5	51
valid_sources[0x24]	332122	1			T1	2297		T3	1262		T5	56
valid_sources[0x25]	271541	1			T1	2260		T3	1233		T5	24
valid_sources[0x26]	284771	1			T1	2254		T3	1193		T5	64
valid_sources[0x27]	253045	1			T1	2215		T3	1344		T4	15
valid_sources[0x28]	301612	1			T1	2292		T3	1171		T5	93
valid_sources[0x29]	272379	1			T1	2261		T3	1158		T5	5
valid_sources[0x2a]	310737	1			T1	2192		T3	1182		T5	71
valid_sources[0x2b]	286026	1			T1	2169		T3	1208		T5	6
valid_sources[0x2c]	265864	1			T1	2213		T3	1240		T5	67
valid_sources[0x2d]	291164	1			T1	2273		T3	1131		T4	26
valid_sources[0x2e]	327990	1			T1	2216		T3	1104		T5	143
valid_sources[0x2f]	275262	1			T1	2321		T3	1180		T5	203
valid_sources[0x30]	374127	1			T1	2306		T3	1154		T5	109
valid_sources[0x31]	298336	1			T1	2210		T3	1162		T5	114
valid_sources[0x32]	264612	1			T1	2246		T3	1147		T4	18
valid_sources[0x33]	392301	1			T1	2189		T3	1117		T5	61
valid_sources[0x34]	256718	1			T1	2120		T3	1187		T5	48
valid_sources[0x35]	313158	1			T1	2227		T3	1207		T5	180
valid_sources[0x36]	311540	1			T1	2306		T3	1187		T5	96
valid_sources[0x37]	312206	1			T1	2182		T3	1178		T5	77
valid_sources[0x38]	252418	1			T1	2208		T3	1204		T5	68
valid_sources[0x39]	281783	1			T1	2216		T3	1168		T5	64
valid_sources[0x3a]	269532	1			T1	2087		T3	1127		T5	66
valid_sources[0x3b]	303381	1			T1	2220		T3	1179		T5	9
valid_sources[0x3c]	286042	1			T1	2062		T3	1287		T5	27
valid_sources[0x3d]	259406	1			T1	2202		T3	1207		T5	52
valid_sources[0x3e]	281483	1			T1	2168		T3	1200		T4	8
valid_sources[0x3f]	413490	1			T1	2232		T3	1151		T5	120
valid_sources[0x40]	291763	1			T1	2213		T3	1284		T5	24
valid_sources[0x41]	254418	1			T1	2210		T3	1277		T4	14
valid_sources[0x42]	307203	1			T1	2193		T3	1155		T5	116
valid_sources[0x43]	277619	1			T1	2210		T3	1162		T4	20
valid_sources[0x44]	307837	1			T1	2239		T3	1171		T5	75
valid_sources[0x45]	349703	1			T1	2156		T3	1263		T4	21
valid_sources[0x46]	251756	1			T1	2263		T3	1121		T4	13
valid_sources[0x47]	417847	1			T1	2245		T3	1184		T5	26
valid_sources[0x48]	330376	1			T1	2378		T3	1175		T5	194
valid_sources[0x49]	294651	1			T1	2202		T3	1097		T5	66
valid_sources[0x4a]	292362	1			T1	2271		T3	1109		T5	65
valid_sources[0x4b]	301463	1			T1	2196		T3	1136		T5	119
valid_sources[0x4c]	273743	1			T1	2272		T3	1130		T5	123
valid_sources[0x4d]	312011	1			T1	2215		T3	1211		T5	69
valid_sources[0x4e]	381313	1			T1	2186		T3	1158		T5	79
valid_sources[0x4f]	303000	1			T1	2223		T3	1170		T5	258
valid_sources[0x50]	295232	1			T1	2155		T3	1254		T5	55
valid_sources[0x51]	311250	1			T1	2189		T3	1166		T5	64
valid_sources[0x52]	274968	1			T1	2247		T3	1137		T5	53
valid_sources[0x53]	274837	1			T1	2152		T3	1112		T5	43
valid_sources[0x54]	296164	1			T1	2164		T3	1157		T5	23
valid_sources[0x55]	253655	1			T1	2142		T3	1247		T5	23
valid_sources[0x56]	264882	1			T1	2161		T3	1244		T5	3
valid_sources[0x57]	250207	1			T1	2193		T3	1196		T5	4
valid_sources[0x58]	302154	1			T1	2263		T3	1146		T5	63
valid_sources[0x59]	275849	1			T1	2218		T3	1138		T5	2
valid_sources[0x5a]	280023	1			T1	2231		T3	1168		T5	164
valid_sources[0x5b]	330312	1			T1	2230		T3	1184		T5	31
valid_sources[0x5c]	277887	1			T1	2191		T3	1197		T5	2
valid_sources[0x5d]	361466	1			T1	2076		T3	1128		T5	39
valid_sources[0x5e]	308997	1			T1	2260		T3	1172		T4	43
valid_sources[0x5f]	274523	1			T1	2229		T3	1142		T5	8
valid_sources[0x60]	294122	1			T1	2141		T3	1213		T5	69
valid_sources[0x61]	291520	1			T1	2168		T3	1210		T5	23
valid_sources[0x62]	290626	1			T1	2212		T3	1221		T5	23
valid_sources[0x63]	313661	1			T1	2259		T3	1210		T5	113
valid_sources[0x64]	323763	1			T1	2116		T3	1091		T5	22
valid_sources[0x65]	258487	1			T1	2265		T3	1101		T5	3
valid_sources[0x66]	262757	1			T1	2229		T3	1200		T5	68
valid_sources[0x67]	292749	1			T1	2173		T3	1200		T5	57
valid_sources[0x68]	275695	1			T1	2198		T3	1190		T5	66
valid_sources[0x69]	286246	1			T1	2314		T3	1180		T5	11
valid_sources[0x6a]	297286	1			T1	2198		T3	1151		T5	138
valid_sources[0x6b]	310511	1			T1	2195		T3	1242		T5	97
valid_sources[0x6c]	250063	1			T1	2190		T3	1187		T5	167
valid_sources[0x6d]	275175	1			T1	2271		T3	1178		T5	10
valid_sources[0x6e]	305774	1			T1	2183		T3	1161		T5	86
valid_sources[0x6f]	266609	1			T1	2187		T3	1093		T5	47
valid_sources[0x70]	298688	1			T1	2248		T3	1160		T5	63
valid_sources[0x71]	273774	1			T1	2144		T3	1306		T5	129
valid_sources[0x72]	359627	1			T1	2220		T3	1201		T4	31
valid_sources[0x73]	266070	1			T1	2276		T3	1194		T5	123
valid_sources[0x74]	259239	1			T1	2223		T3	1185		T5	72
valid_sources[0x75]	299648	1			T1	2210		T3	1150		T5	56
valid_sources[0x76]	353017	1			T1	2218		T3	1112		T5	42
valid_sources[0x77]	300645	1			T1	2181		T3	1190		T5	75
valid_sources[0x78]	264996	1			T1	2320		T3	1125		T4	65
valid_sources[0x79]	247549	1			T1	2190		T3	1230		T4	20
valid_sources[0x7a]	291100	1			T1	2090		T3	1137		T5	26
valid_sources[0x7b]	327564	1			T1	2222		T3	1195		T5	48
valid_sources[0x7c]	271107	1			T1	2188		T3	1196		T5	24
valid_sources[0x7d]	278520	1			T1	2292		T3	1295		T5	58
valid_sources[0x7e]	298299	1			T1	2210		T3	1115		T5	125
valid_sources[0x7f]	275574	1			T1	2224		T3	1167		T5	41
valid_sources[0x80]	325845	1			T1	2165		T3	1227		T5	26

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30739087

1

T1

256852

T3

138333

T5

7168

values[0x0]

all_enables

biggest_size

15486720

1

T1

128773

T3

68848

T5

3569

values[0x1]

all_enables

biggest_size

15480669

1

T1

128808

T3

69194

T5

3599

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38401	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

161085

1

T1

37

T3

1

T10

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	57215	1			T1	23		T8	12		T9	36
values[0x0]	68396	1			T1	62		T3	2		T10	6
values[0x1]	73875	1			T1	53		T2	1		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28821	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

170665

1

T1

47

T3

1

T10

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	597	1			T1	2		T67	9		T14	1
valid_sources[0x01]	602	1			T62	1		T26	1		T33	4
valid_sources[0x02]	736	1			T1	1		T18	1		T25	1
valid_sources[0x03]	773	1			T1	3		T18	1		T23	11
valid_sources[0x04]	1200	1			T1	2		T40	1		T32	2
valid_sources[0x05]	660	1			T18	1		T23	11		T24	5
valid_sources[0x06]	1410	1			T18	1		T14	2		T25	2
valid_sources[0x07]	629	1			T40	1		T62	1		T23	8
valid_sources[0x08]	714	1			T18	1		T23	11		T24	17
valid_sources[0x09]	749	1			T1	1		T23	19		T24	10
valid_sources[0x0a]	690	1			T1	1		T18	1		T23	7
valid_sources[0x0b]	914	1			T1	1		T18	1		T14	3
valid_sources[0x0c]	798	1			T18	3		T23	12		T24	2
valid_sources[0x0d]	805	1			T18	1		T37	2		T23	13
valid_sources[0x0e]	928	1			T18	4		T62	2		T25	2
valid_sources[0x0f]	630	1			T6	1		T18	1		T14	2
valid_sources[0x10]	610	1			T23	13		T24	4		T49	3
valid_sources[0x11]	687	1			T13	1		T18	1		T62	1
valid_sources[0x12]	733	1			T12	1		T18	1		T62	1
valid_sources[0x13]	1040	1			T8	1		T62	1		T23	19
valid_sources[0x14]	709	1			T62	1		T25	1		T23	11
valid_sources[0x15]	634	1			T37	5		T23	13		T24	3
valid_sources[0x16]	607	1			T1	3		T6	1		T23	8
valid_sources[0x17]	823	1			T1	1		T7	2		T40	1
valid_sources[0x18]	651	1			T23	11		T24	6		T148	2
valid_sources[0x19]	743	1			T1	1		T18	1		T23	9
valid_sources[0x1a]	946	1			T6	1		T23	10		T72	1
valid_sources[0x1b]	950	1			T23	15		T74	1		T24	12
valid_sources[0x1c]	898	1			T6	1		T23	24		T77	1
valid_sources[0x1d]	814	1			T9	3		T25	1		T23	14
valid_sources[0x1e]	1098	1			T23	10		T77	1		T24	6
valid_sources[0x1f]	647	1			T17	5		T18	2		T23	13
valid_sources[0x20]	742	1			T23	19		T24	10		T49	1
valid_sources[0x21]	902	1			T1	1		T3	7		T14	4
valid_sources[0x22]	772	1			T35	1		T23	20		T24	9
valid_sources[0x23]	684	1			T18	2		T25	1		T23	7
valid_sources[0x24]	682	1			T1	1		T18	1		T44	3
valid_sources[0x25]	889	1			T18	2		T23	13		T24	21
valid_sources[0x26]	574	1			T14	1		T25	1		T23	6
valid_sources[0x27]	807	1			T1	1		T62	1		T14	1
valid_sources[0x28]	875	1			T14	5		T25	1		T23	19
valid_sources[0x29]	813	1			T1	1		T23	27		T73	4
valid_sources[0x2a]	607	1			T18	1		T23	25		T24	3
valid_sources[0x2b]	1065	1			T9	1		T18	1		T14	2
valid_sources[0x2c]	821	1			T6	1		T62	1		T25	1
valid_sources[0x2d]	834	1			T1	2		T23	10		T77	1
valid_sources[0x2e]	742	1			T6	1		T12	1		T23	8
valid_sources[0x2f]	796	1			T8	1		T9	1		T18	1
valid_sources[0x30]	705	1			T18	3		T34	11		T23	8
valid_sources[0x31]	725	1			T1	2		T10	1		T31	6
valid_sources[0x32]	795	1			T9	5		T18	2		T23	11
valid_sources[0x33]	608	1			T23	12		T24	2		T20	5
valid_sources[0x34]	784	1			T53	1		T9	1		T18	1
valid_sources[0x35]	690	1			T14	2		T23	13		T24	6
valid_sources[0x36]	1437	1			T4	1		T9	2		T23	19
valid_sources[0x37]	753	1			T23	13		T74	1		T149	1
valid_sources[0x38]	696	1			T1	2		T5	1		T18	4
valid_sources[0x39]	1016	1			T1	1		T39	1		T23	13
valid_sources[0x3a]	1162	1			T1	5		T23	13		T24	8
valid_sources[0x3b]	677	1			T9	2		T18	1		T23	13
valid_sources[0x3c]	750	1			T18	1		T23	6		T48	2
valid_sources[0x3d]	731	1			T18	1		T62	2		T25	1
valid_sources[0x3e]	766	1			T62	1		T25	1		T23	12
valid_sources[0x3f]	674	1			T1	2		T9	1		T18	1
valid_sources[0x40]	864	1			T39	1		T23	15		T24	4
valid_sources[0x41]	603	1			T5	1		T44	5		T23	10
valid_sources[0x42]	739	1			T43	5		T23	7		T24	6
valid_sources[0x43]	829	1			T18	3		T23	13		T77	1
valid_sources[0x44]	710	1			T1	1		T23	24		T72	4
valid_sources[0x45]	619	1			T23	12		T77	1		T149	3
valid_sources[0x46]	767	1			T23	8		T74	1		T24	10
valid_sources[0x47]	689	1			T1	1		T18	3		T38	1
valid_sources[0x48]	763	1			T1	1		T40	1		T23	17
valid_sources[0x49]	776	1			T8	1		T67	19		T23	11
valid_sources[0x4a]	927	1			T40	1		T62	1		T14	3
valid_sources[0x4b]	1027	1			T1	1		T8	1		T9	5
valid_sources[0x4c]	963	1			T1	1		T22	1		T25	1
valid_sources[0x4d]	899	1			T1	2		T6	1		T18	1
valid_sources[0x4e]	754	1			T1	1		T23	25		T150	2
valid_sources[0x4f]	748	1			T1	2		T12	1		T25	2
valid_sources[0x50]	893	1			T8	2		T18	2		T62	1
valid_sources[0x51]	679	1			T1	1		T18	1		T25	1
valid_sources[0x52]	810	1			T23	8		T24	9		T145	3
valid_sources[0x53]	758	1			T1	4		T18	4		T23	15
valid_sources[0x54]	915	1			T1	1		T14	1		T23	8
valid_sources[0x55]	832	1			T23	9		T74	1		T24	8
valid_sources[0x56]	870	1			T1	1		T40	1		T13	1
valid_sources[0x57]	763	1			T18	1		T14	1		T25	1
valid_sources[0x58]	751	1			T9	1		T18	1		T25	1
valid_sources[0x59]	739	1			T1	2		T10	1		T18	2
valid_sources[0x5a]	562	1			T1	1		T62	1		T14	1
valid_sources[0x5b]	771	1			T27	1		T18	1		T23	8
valid_sources[0x5c]	634	1			T8	3		T62	1		T25	2
valid_sources[0x5d]	635	1			T5	1		T12	1		T23	9
valid_sources[0x5e]	665	1			T14	5		T25	1		T23	17
valid_sources[0x5f]	902	1			T1	2		T23	9		T24	3
valid_sources[0x60]	699	1			T1	2		T18	1		T23	16
valid_sources[0x61]	1145	1			T1	4		T5	1		T40	1
valid_sources[0x62]	608	1			T18	3		T62	1		T23	14
valid_sources[0x63]	679	1			T9	4		T36	1		T23	11
valid_sources[0x64]	726	1			T1	1		T14	3		T23	12
valid_sources[0x65]	1226	1			T1	1		T23	14		T24	2
valid_sources[0x66]	610	1			T1	1		T23	4		T77	1
valid_sources[0x67]	799	1			T1	1		T23	5		T24	1
valid_sources[0x68]	781	1			T61	1		T18	1		T62	1
valid_sources[0x69]	565	1			T18	3		T23	15		T24	1
valid_sources[0x6a]	844	1			T18	6		T23	13		T24	3
valid_sources[0x6b]	725	1			T62	1		T38	1		T23	14
valid_sources[0x6c]	592	1			T62	2		T23	24		T24	4
valid_sources[0x6d]	824	1			T23	26		T24	3		T19	6
valid_sources[0x6e]	795	1			T11	1		T18	6		T23	14
valid_sources[0x6f]	722	1			T1	1		T18	2		T62	1
valid_sources[0x70]	619	1			T1	1		T13	1		T25	1
valid_sources[0x71]	727	1			T18	1		T23	13		T77	1
valid_sources[0x72]	688	1			T1	2		T40	1		T18	1
valid_sources[0x73]	708	1			T18	4		T62	1		T23	15
valid_sources[0x74]	746	1			T7	2		T8	1		T9	1
valid_sources[0x75]	848	1			T1	1		T18	1		T14	3
valid_sources[0x76]	737	1			T9	1		T18	3		T62	1
valid_sources[0x77]	806	1			T1	1		T18	5		T62	1
valid_sources[0x78]	839	1			T1	1		T40	1		T9	6
valid_sources[0x79]	825	1			T18	7		T62	1		T23	12
valid_sources[0x7a]	840	1			T25	1		T23	16		T24	8
valid_sources[0x7b]	656	1			T12	2		T40	1		T9	2
valid_sources[0x7c]	647	1			T1	1		T18	1		T23	16
valid_sources[0x7d]	570	1			T14	1		T23	6		T24	3
valid_sources[0x7e]	654	1			T62	1		T23	13		T24	7
valid_sources[0x7f]	587	1			T59	1		T62	1		T26	1
valid_sources[0x80]	730	1			T18	1		T23	18		T77	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

43976

1

T1

10

T8

6

T9

17

values[0x0]

all_enables

biggest_size

59428

1

T1

17

T3

1

T10

3

values[0x1]

all_enables

biggest_size

57681

1

T1

10

T5

1

T11

1