Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13681901

1

T1

45819

T3

27436

T4

1062

full_word

56275379

1

T1

460727

T3

276375

T5

14336

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69956980	1			T1	506546		T3	303811		T5	14336
auto[TlIntgErrCmd]	104	1			T63	5		T64	3		T65	1
auto[TlIntgErrData]	105	1			T63	2		T64	6		T65	5
auto[TlIntgErrBoth]	91	1			T63	3		T64	1		T65	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31882715

1

T1

224474

T3

151952

T5

7168

auto[1]

38074565

1

T1

282072

T3

151859

T5

7168

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6506883	1			T1	20395		T3	13619		T4	538
auto[TlIntgErrNone]	partial	auto[1]	7174746	1			T1	25424		T3	13817		T4	524
auto[TlIntgErrNone]	full_word	auto[0]	25375688	1			T1	204079		T3	138333		T5	7168
auto[TlIntgErrNone]	full_word	auto[1]	30899663	1			T1	256648		T3	138042		T5	7168
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T63	2		T64	2		T134	3
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T63	3		T64	1		T65	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T127	1		T132	1		T136	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T128	1		T137	1		T135	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T63	2		T64	1		T65	3
auto[TlIntgErrData]	partial	auto[1]	46	1			T64	5		T65	1		T127	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T132	2		T137	2		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T65	1		T128	1		T137	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T63	1		T65	1		T134	1
auto[TlIntgErrBoth]	partial	auto[1]	44	1			T63	1		T64	1		T65	3
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T63	1		T134	1		T128	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T128	1		T130	1		T138	1