Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	718782	1			T1	23286		T7	73		T8	8
auto[1]	10917625	1			T1	5659		T3	126403		T4	2957
auto[2]	595570	1			T1	20930		T7	29		T8	5
auto[3]	10800140	1			T1	3161		T3	126488		T4	2871

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14988215	1			T1	41784		T3	211053		T4	3891
auto[1]	2195509	1			T1	5740		T3	20007		T4	876
auto[2]	2208403	1			T1	4829		T3	19937		T4	849
auto[3]	3639990	1			T1	683		T3	1894		T4	212

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8697543

1

T1

52987

T4

5823

T12

70603

auto[1]

14334574

1

T1

49

T3

252891

T4

5

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	281934	1			T1	19207		T8	6		T18	2861
auto[0]	auto[0]	auto[1]	29096	1			T1	1912		T7	2		T8	1
auto[0]	auto[0]	auto[2]	28951	1			T1	1929		T7	2		T8	1
auto[0]	auto[0]	auto[3]	6552	1			T1	215		T7	67		T18	30
auto[0]	auto[1]	auto[0]	3292200	1			T1	3192		T4	1959		T12	29134
auto[0]	auto[1]	auto[1]	343162	1			T1	1910		T4	460		T12	2850
auto[0]	auto[1]	auto[2]	335501	1			T1	335		T4	434		T12	2909
auto[0]	auto[1]	auto[3]	78496	1			T1	214		T4	104		T12	280
auto[0]	auto[2]	auto[0]	240862	1			T1	17744		T8	3		T18	2474
auto[0]	auto[2]	auto[1]	24727	1			T1	1780		T8	1		T18	293
auto[0]	auto[2]	auto[2]	26429	1			T1	1278		T7	1		T18	232
auto[0]	auto[2]	auto[3]	5540	1			T1	111		T7	28		T8	1
auto[0]	auto[3]	auto[0]	3251119	1			T1	1607		T4	1930		T12	29353
auto[0]	auto[3]	auto[1]	330020	1			T1	131		T4	415		T12	2899
auto[0]	auto[3]	auto[2]	342702	1			T1	1279		T4	413		T12	2897
auto[0]	auto[3]	auto[3]	80252	1			T1	143		T4	108		T12	281
auto[1]	auto[0]	auto[0]	12622	1			T1	17		T18	4		T36	95
auto[1]	auto[0]	auto[1]	55340	1			T1	4		T36	445		T73	2
auto[1]	auto[0]	auto[2]	55562	1			T1	2		T18	1		T36	406
auto[1]	auto[0]	auto[3]	248725	1			T7	2		T36	1841		T142	3936
auto[1]	auto[1]	auto[0]	3950814	1			T1	5		T3	105613		T12	27
auto[1]	auto[1]	auto[1]	697338	1			T1	2		T3	9458		T12	3
auto[1]	auto[1]	auto[2]	687453	1			T1	1		T3	10394		T12	2
auto[1]	auto[1]	auto[3]	1532661	1			T3	938		T59	309		T36	6342
auto[1]	auto[2]	auto[0]	9621	1			T1	12		T18	4		T73	3
auto[1]	auto[2]	auto[1]	42366	1			T1	1		T18	1		T73	1
auto[1]	auto[2]	auto[2]	44605	1			T1	4		T36	355		T75	1
auto[1]	auto[2]	auto[3]	201420	1			T36	1685		T142	3510		T143	2498
auto[1]	auto[3]	auto[0]	3949043	1			T3	105440		T4	2		T12	27
auto[1]	auto[3]	auto[1]	673460	1			T3	10549		T4	1		T12	3
auto[1]	auto[3]	auto[2]	687200	1			T1	1		T3	9543		T4	2
auto[1]	auto[3]	auto[3]	1486344	1			T3	956		T39	1		T59	315