Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	331978082	238722	0	0
ctrl_regwen_rd_A	331978082	3721	0	0
exec_rd_A	331978082	3505	0	0
exec_regwen_rd_A	331978082	3809	0	0
readback_rd_A	331978082	2033	0	0
readback_regwen_rd_A	331978082	1783	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331978082	238722	0	0
T19	0	2512	0	0
T23	115780	3949	0	0
T24	0	2394	0	0
T48	5540	0	0	0
T49	0	8010	0	0
T50	0	5596	0	0
T56	0	5014	0	0
T57	0	15125	0	0
T58	0	5957	0	0
T68	8389	0	0	0
T69	0	4409	0	0
T70	0	8820	0	0
T71	6821	0	0	0
T72	231630	0	0	0
T73	183446	0	0	0
T74	128735	0	0	0
T75	199762	0	0	0
T76	380665	0	0	0
T77	465667	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331978082	3721	0	0
T69	186317	386	0	0
T109	0	436	0	0
T110	0	113	0	0
T111	0	78	0	0
T112	0	219	0	0
T113	0	135	0	0
T114	0	50	0	0
T115	0	197	0	0
T116	0	160	0	0
T117	0	130	0	0
T118	7018	0	0	0
T119	2217	0	0	0
T120	996357	0	0	0
T121	346927	0	0	0
T122	1798	0	0	0
T123	141334	0	0	0
T124	121780	0	0	0
T125	17212	0	0	0
T126	17358	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331978082	3505	0	0
T69	186317	330	0	0
T109	0	444	0	0
T110	0	102	0	0
T111	0	80	0	0
T112	0	195	0	0
T113	0	78	0	0
T114	0	71	0	0
T115	0	144	0	0
T116	0	161	0	0
T117	0	105	0	0
T118	7018	0	0	0
T119	2217	0	0	0
T120	996357	0	0	0
T121	346927	0	0	0
T122	1798	0	0	0
T123	141334	0	0	0
T124	121780	0	0	0
T125	17212	0	0	0
T126	17358	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331978082	3809	0	0
T69	186317	399	0	0
T109	0	515	0	0
T110	0	122	0	0
T111	0	78	0	0
T112	0	223	0	0
T113	0	109	0	0
T114	0	49	0	0
T115	0	269	0	0
T116	0	123	0	0
T117	0	149	0	0
T118	7018	0	0	0
T119	2217	0	0	0
T120	996357	0	0	0
T121	346927	0	0	0
T122	1798	0	0	0
T123	141334	0	0	0
T124	121780	0	0	0
T125	17212	0	0	0
T126	17358	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331978082	2033	0	0
T69	186317	288	0	0
T109	0	518	0	0
T110	0	75	0	0
T111	0	107	0	0
T112	0	173	0	0
T113	0	111	0	0
T114	0	29	0	0
T115	0	219	0	0
T116	0	102	0	0
T117	0	77	0	0
T118	7018	0	0	0
T119	2217	0	0	0
T120	996357	0	0	0
T121	346927	0	0	0
T122	1798	0	0	0
T123	141334	0	0	0
T124	121780	0	0	0
T125	17212	0	0	0
T126	17358	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331978082	1783	0	0
T69	186317	356	0	0
T109	0	352	0	0
T110	0	41	0	0
T111	0	91	0	0
T112	0	194	0	0
T113	0	83	0	0
T114	0	55	0	0
T115	0	119	0	0
T116	0	127	0	0
T117	0	57	0	0
T118	7018	0	0	0
T119	2217	0	0	0
T120	996357	0	0	0
T121	346927	0	0	0
T122	1798	0	0	0
T123	141334	0	0	0
T124	121780	0	0	0
T125	17212	0	0	0
T126	17358	0	0	0