Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13889668	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

55079048

1

T1

9588

T2

132689

T3

39889

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34392160	1			T1	5313		T2	73022		T3	108659
values[0x0]	15900053	1			T1	2534		T2	34975		T3	37005
values[0x1]	18676503	1			T1	2705		T2	38032		T3	72431

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6919758	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

62048958

1

T1

10073

T2

139408

T3

129192

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	305264	1			T1	29		T2	585		T3	909
valid_sources[0x01]	295753	1			T1	46		T2	580		T3	912
valid_sources[0x02]	266454	1			T1	35		T2	590		T3	784
valid_sources[0x03]	278741	1			T1	50		T2	559		T3	899
valid_sources[0x04]	344979	1			T1	39		T2	593		T3	893
valid_sources[0x05]	255697	1			T1	44		T2	551		T3	889
valid_sources[0x06]	268072	1			T1	33		T2	561		T3	869
valid_sources[0x07]	266205	1			T1	47		T2	582		T3	867
valid_sources[0x08]	248175	1			T1	60		T2	599		T3	832
valid_sources[0x09]	253638	1			T1	41		T2	542		T3	783
valid_sources[0x0a]	265156	1			T1	45		T2	577		T3	820
valid_sources[0x0b]	266336	1			T1	42		T2	627		T3	869
valid_sources[0x0c]	254006	1			T1	33		T2	597		T3	854
valid_sources[0x0d]	267247	1			T1	28		T2	562		T3	870
valid_sources[0x0e]	270750	1			T1	53		T2	570		T3	835
valid_sources[0x0f]	257680	1			T1	43		T2	578		T3	873
valid_sources[0x10]	270137	1			T1	41		T2	567		T3	889
valid_sources[0x11]	260112	1			T1	36		T2	581		T3	849
valid_sources[0x12]	345760	1			T1	54		T2	578		T3	803
valid_sources[0x13]	251522	1			T1	55		T2	547		T3	862
valid_sources[0x14]	260379	1			T1	43		T2	575		T3	802
valid_sources[0x15]	231179	1			T1	47		T2	606		T3	863
valid_sources[0x16]	233016	1			T1	42		T2	583		T3	875
valid_sources[0x17]	239545	1			T1	56		T2	577		T3	935
valid_sources[0x18]	252016	1			T1	61		T2	556		T3	896
valid_sources[0x19]	264793	1			T1	34		T2	553		T3	836
valid_sources[0x1a]	276013	1			T1	47		T2	566		T3	902
valid_sources[0x1b]	264628	1			T1	42		T2	577		T3	896
valid_sources[0x1c]	262812	1			T1	39		T2	599		T3	801
valid_sources[0x1d]	290516	1			T1	42		T2	555		T3	826
valid_sources[0x1e]	351047	1			T1	42		T2	597		T3	847
valid_sources[0x1f]	336916	1			T1	41		T2	560		T3	859
valid_sources[0x20]	302100	1			T1	44		T2	574		T3	878
valid_sources[0x21]	337639	1			T1	55		T2	560		T3	796
valid_sources[0x22]	253601	1			T1	49		T2	628		T3	827
valid_sources[0x23]	255513	1			T1	50		T2	589		T3	889
valid_sources[0x24]	267445	1			T1	39		T2	516		T3	777
valid_sources[0x25]	250824	1			T1	49		T2	595		T3	854
valid_sources[0x26]	243428	1			T1	35		T2	573		T3	842
valid_sources[0x27]	311527	1			T1	40		T2	598		T3	832
valid_sources[0x28]	254133	1			T1	50		T2	556		T3	781
valid_sources[0x29]	289236	1			T1	34		T2	531		T3	849
valid_sources[0x2a]	363492	1			T1	41		T2	554		T3	788
valid_sources[0x2b]	279888	1			T1	32		T2	569		T3	798
valid_sources[0x2c]	279393	1			T1	39		T2	577		T3	753
valid_sources[0x2d]	250162	1			T1	51		T2	541		T3	840
valid_sources[0x2e]	256200	1			T1	29		T2	579		T3	835
valid_sources[0x2f]	230906	1			T1	33		T2	604		T3	763
valid_sources[0x30]	267546	1			T1	40		T2	554		T3	872
valid_sources[0x31]	304505	1			T1	62		T2	565		T3	866
valid_sources[0x32]	265820	1			T1	27		T2	569		T3	789
valid_sources[0x33]	291518	1			T1	48		T2	577		T3	865
valid_sources[0x34]	248216	1			T1	38		T2	547		T3	875
valid_sources[0x35]	256070	1			T1	38		T2	570		T3	906
valid_sources[0x36]	288619	1			T1	44		T2	552		T3	834
valid_sources[0x37]	247896	1			T1	36		T2	552		T3	843
valid_sources[0x38]	298056	1			T1	40		T2	613		T3	788
valid_sources[0x39]	242317	1			T1	51		T2	604		T3	913
valid_sources[0x3a]	246840	1			T1	54		T2	573		T3	837
valid_sources[0x3b]	306992	1			T1	37		T2	617		T3	863
valid_sources[0x3c]	239395	1			T1	51		T2	537		T3	855
valid_sources[0x3d]	239835	1			T1	51		T2	611		T3	917
valid_sources[0x3e]	288665	1			T1	48		T2	561		T3	798
valid_sources[0x3f]	283482	1			T1	41		T2	594		T3	841
valid_sources[0x40]	284299	1			T1	32		T2	590		T3	890
valid_sources[0x41]	258591	1			T1	40		T2	539		T3	837
valid_sources[0x42]	250777	1			T1	40		T2	584		T3	853
valid_sources[0x43]	247406	1			T1	38		T2	576		T3	869
valid_sources[0x44]	417581	1			T1	43		T2	562		T3	867
valid_sources[0x45]	253545	1			T1	39		T2	597		T3	890
valid_sources[0x46]	255184	1			T1	41		T2	535		T3	859
valid_sources[0x47]	330121	1			T1	29		T2	547		T3	864
valid_sources[0x48]	280417	1			T1	29		T2	573		T3	815
valid_sources[0x49]	261283	1			T1	39		T2	556		T3	874
valid_sources[0x4a]	254564	1			T1	36		T2	516		T3	849
valid_sources[0x4b]	264532	1			T1	37		T2	554		T3	812
valid_sources[0x4c]	280096	1			T1	53		T2	598		T3	844
valid_sources[0x4d]	238906	1			T1	33		T2	578		T3	762
valid_sources[0x4e]	299565	1			T1	49		T2	571		T3	801
valid_sources[0x4f]	276483	1			T1	40		T2	577		T3	820
valid_sources[0x50]	258091	1			T1	39		T2	613		T3	795
valid_sources[0x51]	236642	1			T1	35		T2	547		T3	827
valid_sources[0x52]	283629	1			T1	34		T2	618		T3	851
valid_sources[0x53]	255301	1			T1	48		T2	605		T3	824
valid_sources[0x54]	241738	1			T1	27		T2	575		T3	913
valid_sources[0x55]	291353	1			T1	44		T2	601		T3	850
valid_sources[0x56]	231627	1			T1	35		T2	525		T3	857
valid_sources[0x57]	267100	1			T1	36		T2	555		T3	810
valid_sources[0x58]	243766	1			T1	46		T2	531		T3	854
valid_sources[0x59]	255724	1			T1	32		T2	590		T3	846
valid_sources[0x5a]	245431	1			T1	45		T2	551		T3	826
valid_sources[0x5b]	247668	1			T1	37		T2	578		T3	869
valid_sources[0x5c]	250279	1			T1	37		T2	579		T3	918
valid_sources[0x5d]	283347	1			T1	49		T2	563		T3	814
valid_sources[0x5e]	281973	1			T1	40		T2	594		T3	882
valid_sources[0x5f]	288286	1			T1	33		T2	577		T3	804
valid_sources[0x60]	244596	1			T1	34		T2	574		T3	877
valid_sources[0x61]	230308	1			T1	34		T2	603		T3	856
valid_sources[0x62]	309059	1			T1	52		T2	607		T3	878
valid_sources[0x63]	294178	1			T1	19		T2	592		T3	868
valid_sources[0x64]	258103	1			T1	35		T2	582		T3	828
valid_sources[0x65]	266592	1			T1	35		T2	608		T3	831
valid_sources[0x66]	241885	1			T1	48		T2	570		T3	860
valid_sources[0x67]	295471	1			T1	32		T2	540		T3	827
valid_sources[0x68]	245263	1			T1	32		T2	586		T3	896
valid_sources[0x69]	283899	1			T1	41		T2	563		T3	821
valid_sources[0x6a]	295160	1			T1	46		T2	528		T3	870
valid_sources[0x6b]	291554	1			T1	47		T2	570		T3	890
valid_sources[0x6c]	247165	1			T1	49		T2	558		T3	841
valid_sources[0x6d]	258612	1			T1	45		T2	582		T3	821
valid_sources[0x6e]	254753	1			T1	39		T2	526		T3	811
valid_sources[0x6f]	248450	1			T1	39		T2	594		T3	794
valid_sources[0x70]	271659	1			T1	39		T2	587		T3	827
valid_sources[0x71]	279820	1			T1	47		T2	563		T3	910
valid_sources[0x72]	232619	1			T1	41		T2	607		T3	861
valid_sources[0x73]	261123	1			T1	45		T2	611		T3	825
valid_sources[0x74]	381970	1			T1	43		T2	506		T3	810
valid_sources[0x75]	295999	1			T1	35		T2	600		T3	889
valid_sources[0x76]	286164	1			T1	44		T2	575		T3	859
valid_sources[0x77]	272649	1			T1	49		T2	592		T3	844
valid_sources[0x78]	256759	1			T1	37		T2	546		T3	814
valid_sources[0x79]	235279	1			T1	39		T2	533		T3	898
valid_sources[0x7a]	348412	1			T1	48		T2	559		T3	789
valid_sources[0x7b]	246003	1			T1	37		T2	570		T3	873
valid_sources[0x7c]	285128	1			T1	44		T2	540		T3	811
valid_sources[0x7d]	249682	1			T1	25		T2	537		T3	860
valid_sources[0x7e]	253364	1			T1	54		T2	589		T3	900
valid_sources[0x7f]	291311	1			T1	45		T2	547		T3	838
valid_sources[0x80]	246121	1			T1	43		T2	586		T3	851

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27451460

1

T1

4802

T2

66424

T3

20029

values[0x0]

all_enables

biggest_size

13815440

1

T1

2414

T2

32985

T3

9925

values[0x1]

all_enables

biggest_size

13812148

1

T1

2372

T2

33280

T3

9935

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34365	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

112656

1

T1

1

T2

5

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	43750	1			T7	35		T8	18		T9	27
values[0x0]	49669	1			T1	1		T2	14		T3	1
values[0x1]	53602	1			T1	1		T2	9		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26299	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

120722

1

T1

1

T2

8

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	448	1			T97	4		T71	1		T80	2
valid_sources[0x01]	702	1			T7	15		T24	4		T81	1
valid_sources[0x02]	591	1			T18	2		T41	1		T23	2
valid_sources[0x03]	432	1			T30	1		T25	2		T31	7
valid_sources[0x04]	468	1			T55	2		T71	1		T24	1
valid_sources[0x05]	736	1			T10	1		T12	2		T60	5
valid_sources[0x06]	524	1			T24	1		T31	7		T32	6
valid_sources[0x07]	822	1			T34	1		T30	1		T25	2
valid_sources[0x08]	401	1			T71	3		T30	1		T76	2
valid_sources[0x09]	536	1			T45	4		T24	1		T25	1
valid_sources[0x0a]	584	1			T25	1		T143	1		T31	8
valid_sources[0x0b]	569	1			T149	3		T71	1		T30	61
valid_sources[0x0c]	599	1			T27	6		T9	26		T30	2
valid_sources[0x0d]	431	1			T24	2		T25	1		T31	10
valid_sources[0x0e]	523	1			T149	1		T111	1		T30	1
valid_sources[0x0f]	690	1			T150	4		T143	1		T31	4
valid_sources[0x10]	616	1			T34	2		T151	1		T139	3
valid_sources[0x11]	849	1			T139	2		T31	16		T32	7
valid_sources[0x12]	626	1			T71	3		T25	1		T152	2
valid_sources[0x13]	413	1			T34	1		T24	1		T25	2
valid_sources[0x14]	724	1			T25	1		T31	6		T32	6
valid_sources[0x15]	473	1			T21	1		T36	1		T98	1
valid_sources[0x16]	416	1			T151	1		T25	1		T139	2
valid_sources[0x17]	812	1			T78	1		T31	10		T32	10
valid_sources[0x18]	607	1			T71	1		T19	2		T31	12
valid_sources[0x19]	479	1			T112	1		T31	10		T32	8
valid_sources[0x1a]	442	1			T83	2		T153	2		T25	1
valid_sources[0x1b]	930	1			T23	4		T35	65		T24	1
valid_sources[0x1c]	660	1			T23	8		T80	1		T83	3
valid_sources[0x1d]	518	1			T47	1		T54	1		T25	3
valid_sources[0x1e]	409	1			T34	1		T71	1		T30	1
valid_sources[0x1f]	661	1			T10	1		T23	20		T71	1
valid_sources[0x20]	469	1			T71	1		T24	1		T30	3
valid_sources[0x21]	830	1			T149	2		T78	2		T25	1
valid_sources[0x22]	661	1			T97	3		T71	2		T19	2
valid_sources[0x23]	637	1			T10	1		T31	13		T32	3
valid_sources[0x24]	529	1			T23	6		T25	1		T31	9
valid_sources[0x25]	686	1			T9	1		T71	1		T24	1
valid_sources[0x26]	725	1			T21	1		T149	1		T71	1
valid_sources[0x27]	468	1			T10	1		T151	1		T24	1
valid_sources[0x28]	814	1			T23	6		T71	1		T19	2
valid_sources[0x29]	512	1			T97	2		T111	1		T23	1
valid_sources[0x2a]	677	1			T72	1		T34	2		T24	1
valid_sources[0x2b]	440	1			T49	5		T71	1		T154	1
valid_sources[0x2c]	921	1			T7	4		T9	2		T30	2
valid_sources[0x2d]	480	1			T71	1		T24	1		T30	3
valid_sources[0x2e]	437	1			T59	1		T151	1		T24	1
valid_sources[0x2f]	519	1			T25	1		T139	1		T31	7
valid_sources[0x30]	394	1			T26	2		T30	1		T83	1
valid_sources[0x31]	622	1			T78	1		T143	1		T31	18
valid_sources[0x32]	510	1			T41	1		T23	2		T71	3
valid_sources[0x33]	656	1			T34	1		T71	1		T25	2
valid_sources[0x34]	470	1			T24	1		T83	1		T31	10
valid_sources[0x35]	421	1			T25	1		T139	3		T155	1
valid_sources[0x36]	519	1			T71	2		T31	10		T32	8
valid_sources[0x37]	636	1			T47	1		T34	1		T71	1
valid_sources[0x38]	518	1			T76	4		T25	1		T139	2
valid_sources[0x39]	725	1			T13	20		T7	13		T30	1
valid_sources[0x3a]	629	1			T41	2		T30	1		T25	2
valid_sources[0x3b]	440	1			T18	3		T40	11		T34	1
valid_sources[0x3c]	705	1			T18	6		T23	4		T24	1
valid_sources[0x3d]	723	1			T42	2		T14	2		T25	1
valid_sources[0x3e]	383	1			T49	1		T83	1		T25	2
valid_sources[0x3f]	497	1			T71	1		T24	1		T25	2
valid_sources[0x40]	586	1			T1	1		T8	38		T55	1
valid_sources[0x41]	490	1			T92	4		T41	2		T23	1
valid_sources[0x42]	529	1			T26	4		T31	13		T32	7
valid_sources[0x43]	393	1			T31	8		T32	6		T53	12
valid_sources[0x44]	553	1			T149	3		T45	2		T156	1
valid_sources[0x45]	830	1			T25	2		T157	1		T31	15
valid_sources[0x46]	554	1			T23	4		T24	2		T80	1
valid_sources[0x47]	510	1			T37	1		T23	4		T71	1
valid_sources[0x48]	624	1			T71	1		T24	1		T30	1
valid_sources[0x49]	622	1			T21	2		T23	13		T78	1
valid_sources[0x4a]	453	1			T71	2		T24	1		T154	1
valid_sources[0x4b]	670	1			T30	1		T83	1		T25	1
valid_sources[0x4c]	486	1			T25	1		T139	1		T31	10
valid_sources[0x4d]	911	1			T24	1		T25	1		T139	7
valid_sources[0x4e]	476	1			T49	1		T76	1		T31	12
valid_sources[0x4f]	630	1			T34	1		T23	2		T80	1
valid_sources[0x50]	565	1			T158	2		T151	1		T71	1
valid_sources[0x51]	672	1			T21	1		T23	9		T71	2
valid_sources[0x52]	394	1			T71	1		T25	1		T143	2
valid_sources[0x53]	425	1			T159	4		T139	2		T31	5
valid_sources[0x54]	438	1			T10	1		T33	1		T25	1
valid_sources[0x55]	439	1			T97	1		T30	1		T139	2
valid_sources[0x56]	665	1			T29	1		T33	1		T111	1
valid_sources[0x57]	505	1			T23	18		T143	1		T31	13
valid_sources[0x58]	636	1			T151	1		T24	1		T98	1
valid_sources[0x59]	444	1			T10	1		T71	1		T30	1
valid_sources[0x5a]	558	1			T30	1		T25	4		T139	3
valid_sources[0x5b]	513	1			T6	3		T23	9		T24	1
valid_sources[0x5c]	645	1			T23	5		T56	3		T150	1
valid_sources[0x5d]	498	1			T33	1		T72	1		T143	1
valid_sources[0x5e]	460	1			T48	1		T80	1		T157	1
valid_sources[0x5f]	453	1			T76	1		T25	1		T159	4
valid_sources[0x60]	440	1			T97	1		T151	1		T30	1
valid_sources[0x61]	523	1			T71	1		T24	1		T160	1
valid_sources[0x62]	548	1			T3	1		T159	2		T143	1
valid_sources[0x63]	499	1			T10	1		T24	1		T139	3
valid_sources[0x64]	432	1			T11	2		T23	4		T71	1
valid_sources[0x65]	690	1			T41	3		T111	1		T71	3
valid_sources[0x66]	523	1			T40	9		T54	1		T80	1
valid_sources[0x67]	445	1			T10	1		T29	1		T71	1
valid_sources[0x68]	449	1			T29	1		T23	3		T71	1
valid_sources[0x69]	483	1			T97	6		T23	8		T30	3
valid_sources[0x6a]	479	1			T9	4		T149	1		T83	1
valid_sources[0x6b]	463	1			T97	5		T25	1		T31	13
valid_sources[0x6c]	533	1			T71	2		T31	9		T32	4
valid_sources[0x6d]	803	1			T9	6		T71	1		T24	1
valid_sources[0x6e]	545	1			T34	1		T24	1		T30	2
valid_sources[0x6f]	838	1			T10	1		T34	1		T30	2
valid_sources[0x70]	509	1			T24	2		T150	2		T143	1
valid_sources[0x71]	404	1			T71	2		T30	3		T143	1
valid_sources[0x72]	574	1			T73	1		T34	1		T71	2
valid_sources[0x73]	511	1			T22	31		T18	4		T24	1
valid_sources[0x74]	553	1			T156	1		T71	1		T24	1
valid_sources[0x75]	558	1			T23	1		T24	1		T30	1
valid_sources[0x76]	501	1			T30	1		T31	10		T161	1
valid_sources[0x77]	443	1			T55	1		T71	1		T80	1
valid_sources[0x78]	486	1			T4	6		T159	1		T31	8
valid_sources[0x79]	1019	1			T71	3		T30	80		T25	1
valid_sources[0x7a]	385	1			T10	1		T18	3		T34	1
valid_sources[0x7b]	563	1			T7	1		T24	1		T25	1
valid_sources[0x7c]	444	1			T54	1		T99	3		T25	1
valid_sources[0x7d]	451	1			T34	1		T31	9		T32	10
valid_sources[0x7e]	721	1			T10	1		T80	1		T25	1
valid_sources[0x7f]	470	1			T71	1		T25	2		T143	1
valid_sources[0x80]	484	1			T25	1		T143	1		T31	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

31513

1

T7

19

T8

11

T9

13

values[0x0]

all_enables

biggest_size

41441

1

T1

1

T2

4

T10

2

values[0x1]

all_enables

biggest_size

39702

1

T2

1

T3

1

T10

2