Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13577286

1

T1

964

T2

13340

T3

178206

full_word

50445051

1

T1

9588

T2

132689

T3

39889

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	64022047	1			T1	10552		T2	146029		T3	218095
auto[TlIntgErrCmd]	86	1			T66	2		T67	9		T68	7
auto[TlIntgErrData]	109	1			T66	4		T67	7		T68	3
auto[TlIntgErrBoth]	95	1			T66	4		T67	4		T68	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29421083

1

T1

5313

T2

73022

T3

108659

auto[1]

34601254

1

T1

5239

T2

73007

T3

109436

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6516923	1			T1	511		T2	6598		T3	88630
auto[TlIntgErrNone]	partial	auto[1]	7060098	1			T1	453		T2	6742		T3	89576
auto[TlIntgErrNone]	full_word	auto[0]	22904023	1			T1	4802		T2	66424		T3	20029
auto[TlIntgErrNone]	full_word	auto[1]	27541003	1			T1	4786		T2	66265		T3	19860
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T67	2		T68	2		T131	2
auto[TlIntgErrCmd]	partial	auto[1]	42	1			T66	2		T67	6		T68	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T67	1		T68	1		T136	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T68	2		T132	1		T137	2
auto[TlIntgErrData]	partial	auto[0]	53	1			T66	2		T67	5		T131	3
auto[TlIntgErrData]	partial	auto[1]	45	1			T66	2		T67	1		T68	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T67	1		T68	2		T131	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T131	1		T133	1		T136	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T66	3		T68	5		T133	2
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T66	1		T67	4		T68	5
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T138	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T135	1		T132	1		T137	1