Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	579394	1			T4	176		T5	954		T12	850
auto[1]	10169226	1			T1	15		T2	23447		T3	91443
auto[2]	481156	1			T4	149		T5	869		T12	620
auto[3]	10071489	1			T1	19		T2	23471		T3	92017

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	12822584	1			T1	26		T2	38593		T3	6220
auto[1]	2117109	1			T1	4		T2	4053		T3	27456
auto[2]	2137804	1			T1	4		T2	3859		T3	27095
auto[3]	4223768	1			T2	413		T3	122689		T10	283

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7293589

1

T1

34

T2

46870

T3

22

auto[1]

14007676

1

T2

48

T3

183438

T10

41

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	217378	1			T4	149		T5	38		T12	36
auto[0]	auto[0]	auto[1]	23586	1			T4	17		T5	156		T12	127
auto[0]	auto[0]	auto[2]	23541	1			T4	6		T5	171		T12	122
auto[0]	auto[0]	auto[3]	12248	1			T4	3		T5	589		T12	564
auto[0]	auto[1]	auto[0]	2774626	1			T1	11		T2	19262		T3	1
auto[0]	auto[1]	auto[1]	289572	1			T1	2		T2	2072		T3	2
auto[0]	auto[1]	auto[2]	277932	1			T1	2		T2	1887		T10	1463
auto[0]	auto[1]	auto[3]	67582	1			T2	200		T3	8		T10	139
auto[0]	auto[2]	auto[0]	182462	1			T4	130		T5	29		T12	24
auto[0]	auto[2]	auto[1]	20022	1			T4	14		T5	147		T12	122
auto[0]	auto[2]	auto[2]	24409	1			T4	4		T5	139		T12	91
auto[0]	auto[2]	auto[3]	10406	1			T4	1		T5	553		T12	382
auto[0]	auto[3]	auto[0]	2736392	1			T1	15		T2	19294		T10	14445
auto[0]	auto[3]	auto[1]	274175	1			T1	2		T2	1973		T3	2
auto[0]	auto[3]	auto[2]	291247	1			T1	2		T2	1969		T3	2
auto[0]	auto[3]	auto[3]	68011	1			T2	213		T3	7		T10	144
auto[1]	auto[0]	auto[0]	10184	1			T4	1		T13	15		T111	152
auto[1]	auto[0]	auto[1]	45146	1			T111	601		T145	5396		T146	588
auto[1]	auto[0]	auto[2]	45046	1			T13	2		T111	621		T139	1
auto[1]	auto[0]	auto[3]	202265	1			T12	1		T13	2		T111	2931
auto[1]	auto[1]	auto[0]	3449458	1			T2	21		T3	3112		T10	15
auto[1]	auto[1]	auto[1]	725720	1			T2	4		T3	13740		T10	3
auto[1]	auto[1]	auto[2]	720369	1			T2	1		T3	13515		T10	1
auto[1]	auto[1]	auto[3]	1863967	1			T3	61065		T5	1		T33	64378
auto[1]	auto[2]	auto[0]	7261	1			T13	12		T23	2		T139	3
auto[1]	auto[2]	auto[1]	32174	1			T12	1		T145	4954		T147	3
auto[1]	auto[2]	auto[2]	37280	1			T13	3		T111	558		T76	1
auto[1]	auto[2]	auto[3]	167142	1			T5	1		T111	2569		T82	2
auto[1]	auto[3]	auto[0]	3444823	1			T2	16		T3	3107		T10	16
auto[1]	auto[3]	auto[1]	706714	1			T2	4		T3	13712		T10	4
auto[1]	auto[3]	auto[2]	717980	1			T2	2		T3	13578		T10	2
auto[1]	auto[3]	auto[3]	1832147	1			T3	61609		T33	64733		T92	540