Unified Coverage Report :: Module :: tlul_cmd_intg_chk

Module : tlul_cmd_intg_chk

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_regs.u_chk	100.00	100.00					100.00
tb.dut.u_tlul_adapter_sram.gen_cmd_intg_check.u_cmd_intg_chk	100.00	100.00					100.00

---

Module Instance : tb.dut.u_reg_regs.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00		100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.58	100.00	98.31			100.00	100.00	u_reg_regs

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_chk	100.00			100.00
u_tlul_data_integ_dec	100.00	100.00		100.00

---

Module Instance : tb.dut.u_tlul_adapter_sram.gen_cmd_intg_check.u_cmd_intg_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00		100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.26	98.70	89.47			96.88	100.00	u_tlul_adapter_sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_chk	100.00			100.00
u_tlul_data_integ_dec	100.00	100.00		100.00

Line Coverage for Module : tlul_cmd_intg_chk

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	22	1	1	100.00
CONT_ASSIGN	44	0	0
CONT_ASSIGN	49	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	1	1
44		unreachable
49	1	1

---

Assert Coverage for Module : tlul_cmd_intg_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayLoadWidthCheck	1906	1906	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	1906	1906	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T10	2	2	0	0
T11	2	2	0	0
T12	2	2	0	0
T13	2	2	0	0

Line Coverage for Instance : tb.dut.u_reg_regs.u_chk

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	22	1	1	100.00
CONT_ASSIGN	44	0	0
CONT_ASSIGN	49	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	1	1
44		unreachable
49	1	1

---

Assert Coverage for Instance : tb.dut.u_reg_regs.u_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayLoadWidthCheck	1019	1019	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	1019	1019	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.gen_cmd_intg_check.u_cmd_intg_chk

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	22	1	1	100.00
CONT_ASSIGN	44	0	0
CONT_ASSIGN	49	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	1	1
44		unreachable
49	1	1

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.gen_cmd_intg_check.u_cmd_intg_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayLoadWidthCheck	887	887	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	887	887	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0