Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	302217760	160720	0	0
ctrl_regwen_rd_A	302217760	4353	0	0
exec_rd_A	302217760	4007	0	0
exec_regwen_rd_A	302217760	4143	0	0
readback_rd_A	302217760	2011	0	0
readback_regwen_rd_A	302217760	1837	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302217760	160720	0	0
T14	1357	0	0	0
T30	36809	2245	0	0
T31	0	4930	0	0
T32	0	3197	0	0
T53	0	2813	0	0
T61	0	4462	0	0
T63	0	5347	0	0
T64	0	3872	0	0
T65	0	2589	0	0
T74	0	3318	0	0
T75	0	2850	0	0
T76	124467	0	0	0
T77	2049	0	0	0
T78	207348	0	0	0
T79	826468	0	0	0
T80	119248	0	0	0
T81	5670	0	0	0
T82	64973	0	0	0
T83	36639	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302217760	4353	0	0
T32	76817	273	0	0
T52	0	325	0	0
T53	92215	0	0	0
T61	272877	445	0	0
T65	0	277	0	0
T70	0	19	0	0
T74	62249	0	0	0
T75	0	288	0	0
T85	0	72	0	0
T117	0	100	0	0
T118	0	63	0	0
T119	0	471	0	0
T120	56550	0	0	0
T121	45776	0	0	0
T122	3982	0	0	0
T123	14503	0	0	0
T124	172639	0	0	0
T125	22994	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302217760	4007	0	0
T32	76817	242	0	0
T52	0	291	0	0
T53	92215	0	0	0
T61	272877	293	0	0
T65	0	183	0	0
T70	0	20	0	0
T74	62249	0	0	0
T75	0	206	0	0
T85	0	86	0	0
T117	0	135	0	0
T118	0	57	0	0
T119	0	390	0	0
T120	56550	0	0	0
T121	45776	0	0	0
T122	3982	0	0	0
T123	14503	0	0	0
T124	172639	0	0	0
T125	22994	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302217760	4143	0	0
T32	76817	201	0	0
T52	0	277	0	0
T53	92215	0	0	0
T61	272877	400	0	0
T65	0	183	0	0
T70	0	7	0	0
T74	62249	0	0	0
T75	0	266	0	0
T85	0	95	0	0
T117	0	107	0	0
T118	0	70	0	0
T119	0	401	0	0
T120	56550	0	0	0
T121	45776	0	0	0
T122	3982	0	0	0
T123	14503	0	0	0
T124	172639	0	0	0
T125	22994	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302217760	2011	0	0
T32	76817	218	0	0
T52	0	277	0	0
T53	92215	0	0	0
T61	272877	291	0	0
T65	0	115	0	0
T74	62249	0	0	0
T75	0	290	0	0
T117	0	106	0	0
T118	0	42	0	0
T119	0	396	0	0
T120	56550	0	0	0
T121	45776	0	0	0
T122	3982	0	0	0
T123	14503	0	0	0
T124	172639	0	0	0
T125	22994	0	0	0
T126	0	4	0	0
T127	0	4	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302217760	1837	0	0
T32	76817	165	0	0
T52	0	289	0	0
T53	92215	0	0	0
T61	272877	308	0	0
T65	0	125	0	0
T74	62249	0	0	0
T75	0	243	0	0
T117	0	57	0	0
T118	0	59	0	0
T119	0	400	0	0
T120	56550	0	0	0
T121	45776	0	0	0
T122	3982	0	0	0
T123	14503	0	0	0
T124	172639	0	0	0
T125	22994	0	0	0
T126	0	16	0	0
T128	0	4	0	0