Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	148828990	1			T1	90112		T2	12284		T3	609028
instr_valid_dis	116101783	1			T1	90112		T2	12284		T3	591080
instr_en	23159458	1			T3	17948		T6	927180		T22	12156

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9943898	1			T3	6342		T6	169110		T22	68872
sram_ifetch_valid_disable	116899426	1			T1	90112		T2	12284		T3	573718
sram_ifetch_enable	21985666	1			T3	28968		T6	926860		T22	177802

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	148828990	1			T1	90112		T2	12284		T3	609028
hw_debug_en_valid_off	115856489	1			T1	90112		T2	12284		T3	590332
hw_debug_en_on	22047891	1			T3	17948		T6	591554		T22	63778

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	116899426	1			T1	90112		T2	12284		T3	573718
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	103160572	1			T1	90112		T2	12284		T3	573718
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9598777	1			T6	422700		T22	12156		T61	64404
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4266944	1			T3	5594		T6	19418		T22	15732
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1956842	1			T3	5594		T22	15732		T129	9708
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1735258	1			T6	19418		T61	17592		T18	5604
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3377444	1			T6	134390		T22	45112		T18	45820
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1235168	1			T22	45112		T129	15088		T28	15914
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1473736	1			T6	123766		T18	28252		T129	75074
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9704206	1			T6	223472		T22	18666		T61	72
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3874762	1			T6	416		T22	18666		T18	12712
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4239083	1			T6	194196		T61	72		T18	41418

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9418617	1			T3	17948		T6	345994		T18	59074
lc_exec_en	8966241	1			T3	17948		T6	233692		T18	117796
valid_exec_dis	111904527	1			T1	90112		T2	12284		T3	584738
invalid_exec_dis	31929564	1			T3	35310		T6	109597		T22	246674